kernel/arch/powerpc/boot/dts/gef_sbc310.dts

   1 /*
   2  * GE SBC310 Device Tree Source
   3  *
   4  * Copyright 2008 GE Intelligent Platforms Embedded Systems, Inc.
   5  *
   6  * This program is free software; you can redistribute  it and/or modify it
   7  * under  the terms of  the GNU General  Public License as published by the
   8  * Free Software Foundation;  either version 2 of the  License, or (at your
   9  * option) any later version.
  10  *
  11  * Based on: SBS CM6 Device Tree Source
  12  * Copyright 2007 SBS Technologies GmbH & Co. KG
  13  * And: mpc8641_hpcn.dts (MPC8641 HPCN Device Tree Source)
  14  * Copyright 2006 Freescale Semiconductor Inc.
  15  */
  16
  17 /*
  18  * Compiled with dtc -I dts -O dtb -o gef_sbc310.dtb gef_sbc310.dts
  19  */
  20
  21 /dts-v1/;
  22
  23 / {
  24         model = "GEF_SBC310";
  25         compatible = "gef,sbc310";
  26         #address-cells = <1>;
  27         #size-cells = <1>;
  28
  29         aliases {
  30                 ethernet0 = &enet0;
  31                 ethernet1 = &enet1;
  32                 serial0 = &serial0;
  33                 serial1 = &serial1;
  34                 pci0 = &pci0;
  35                 pci1 = &pci1;
  36         };
  37
  38         cpus {
  39                 #address-cells = <1>;
  40                 #size-cells = <0>;
  41
  42                 PowerPC,8641@0 {
  43                         device_type = "cpu";
  44                         reg = <0>;
  45                         d-cache-line-size = <32>;       // 32 bytes
  46                         i-cache-line-size = <32>;       // 32 bytes
  47                         d-cache-size = <32768>;         // L1, 32K
  48                         i-cache-size = <32768>;         // L1, 32K
  49                         timebase-frequency = <0>;       // From uboot
  50                         bus-frequency = <0>;            // From uboot
  51                         clock-frequency = <0>;          // From uboot
  52                 };
  53                 PowerPC,8641@1 {
  54                         device_type = "cpu";
  55                         reg = <1>;
  56                         d-cache-line-size = <32>;       // 32 bytes
  57                         i-cache-line-size = <32>;       // 32 bytes
  58                         d-cache-size = <32768>;         // L1, 32K
  59                         i-cache-size = <32768>;         // L1, 32K
  60                         timebase-frequency = <0>;       // From uboot
  61                         bus-frequency = <0>;            // From uboot
  62                         clock-frequency = <0>;          // From uboot
  63                 };
  64         };
  65
  66         memory {
  67                 device_type = "memory";
  68                 reg = <0x0 0x40000000>; // set by uboot
  69         };
  70
  71         localbus@fef05000 {
  72                 #address-cells = <2>;
  73                 #size-cells = <1>;
  74                 compatible = "fsl,mpc8641-localbus", "simple-bus";
  75                 reg = <0xfef05000 0x1000>;
  76                 interrupts = <19 2>;
  77                 interrupt-parent = <&mpic>;
  78
  79                 ranges = <0 0 0xff000000 0x01000000     // 16MB Boot flash
  80                           1 0 0xe0000000 0x08000000     // Paged Flash 0
  81                           2 0 0xe8000000 0x08000000     // Paged Flash 1
  82                           3 0 0xfc100000 0x00020000     // NVRAM
  83                           4 0 0xfc000000 0x00010000>;   // FPGA
  84
  85                 /* flash@0,0 is a mirror of part of the memory in flash@1,0
  86                 flash@0,0 {
  87                         compatible = "gef,sbc310-firmware-mirror", "cfi-flash";
  88                         reg = <0x0 0x0 0x01000000>;
  89                         bank-width = <2>;
  90                         device-width = <2>;
  91                         #address-cells = <1>;
  92                         #size-cells = <1>;
  93                         partition@0 {
  94                                 label = "firmware";
  95                                 reg = <0x0 0x01000000>;
  96                                 read-only;
  97                         };
  98                 };
  99                 */
 100
 101                 flash@1,0 {
 102                         compatible = "gef,sbc310-paged-flash", "cfi-flash";
 103                         reg = <0x1 0x0 0x8000000>;
 104                         bank-width = <2>;
 105                         device-width = <2>;
 106                         #address-cells = <1>;
 107                         #size-cells = <1>;
 108                         partition@0 {
 109                                 label = "user";
 110                                 reg = <0x0 0x7800000>;
 111                         };
 112                         partition@7800000 {
 113                                 label = "firmware";
 114                                 reg = <0x7800000 0x800000>;
 115                                 read-only;
 116                         };
 117                 };
 118
 119                 nvram@3,0 {
 120                         device_type = "nvram";
 121                         compatible = "simtek,stk14ca8";
 122                         reg = <0x3 0x0 0x20000>;
 123                 };
 124
 125                 fpga@4,0 {
 126                         compatible = "gef,fpga-regs";
 127                         reg = <0x4 0x0 0x40>;
 128                 };
 129
 130                 wdt@4,2000 {
 131                         compatible = "gef,sbc310-fpga-wdt", "gef,fpga-wdt-1.00",
 132                                 "gef,fpga-wdt";
 133                         reg = <0x4 0x2000 0x8>;
 134                         interrupts = <0x1a 0x4>;
 135                         interrupt-parent = <&gef_pic>;
 136                 };
 137 /*
 138                 wdt@4,2010 {
 139                         compatible = "gef,sbc310-fpga-wdt", "gef,fpga-wdt-1.00",
 140                                 "gef,fpga-wdt";
 141                         reg = <0x4 0x2010 0x8>;
 142                         interrupts = <0x1b 0x4>;
 143                         interrupt-parent = <&gef_pic>;
 144                 };
 145 */
 146                 gef_pic: pic@4,4000 {
 147                         #interrupt-cells = <1>;
 148                         interrupt-controller;
 149                         compatible = "gef,sbc310-fpga-pic", "gef,fpga-pic";
 150                         reg = <0x4 0x4000 0x20>;
 151                         interrupts = <0x8
 152                                       0x9>;
 153                         interrupt-parent = <&mpic>;
 154
 155                 };
 156                 gef_gpio: gpio@4,8000 {
 157                         #gpio-cells = <2>;
 158                         compatible = "gef,sbc310-gpio";
 159                         reg = <0x4 0x8000 0x24>;
 160                         gpio-controller;
 161                 };
 162         };
 163
 164         soc@fef00000 {
 165                 #address-cells = <1>;
 166                 #size-cells = <1>;
 167                 #interrupt-cells = <2>;
 168                 device_type = "soc";
 169                 compatible = "fsl,mpc8641-soc", "simple-bus";
 170                 ranges = <0x0 0xfef00000 0x00100000>;
 171                 bus-frequency = <33333333>;
 172
 173                 mcm-law@0 {
 174                         compatible = "fsl,mcm-law";
 175                         reg = <0x0 0x1000>;
 176                         fsl,num-laws = <10>;
 177                 };
 178
 179                 mcm@1000 {
 180                         compatible = "fsl,mpc8641-mcm", "fsl,mcm";
 181                         reg = <0x1000 0x1000>;
 182                         interrupts = <17 2>;
 183                         interrupt-parent = <&mpic>;
 184                 };
 185
 186                 i2c1: i2c@3000 {
 187                         #address-cells = <1>;
 188                         #size-cells = <0>;
 189                         compatible = "fsl-i2c";
 190                         reg = <0x3000 0x100>;
 191                         interrupts = <0x2b 0x2>;
 192                         interrupt-parent = <&mpic>;
 193                         dfsrr;
 194
 195                         rtc@51 {
 196                                 compatible = "epson,rx8581";
 197                                 reg = <0x00000051>;
 198                         };
 199                 };
 200
 201                 i2c2: i2c@3100 {
 202                         #address-cells = <1>;
 203                         #size-cells = <0>;
 204                         compatible = "fsl-i2c";
 205                         reg = <0x3100 0x100>;
 206                         interrupts = <0x2b 0x2>;
 207                         interrupt-parent = <&mpic>;
 208                         dfsrr;
 209
 210                         hwmon@48 {
 211                                 compatible = "national,lm92";
 212                                 reg = <0x48>;
 213                         };
 214
 215                         hwmon@4c {
 216                                 compatible = "adi,adt7461";
 217                                 reg = <0x4c>;
 218                         };
 219
 220                         eti@6b {
 221                                 compatible = "dallas,ds1682";
 222                                 reg = <0x6b>;
 223                         };
 224                 };
 225
 226                 dma@21300 {
 227                         #address-cells = <1>;
 228                         #size-cells = <1>;
 229                         compatible = "fsl,mpc8641-dma", "fsl,eloplus-dma";
 230                         reg = <0x21300 0x4>;
 231                         ranges = <0x0 0x21100 0x200>;
 232                         cell-index = <0>;
 233                         dma-channel@0 {
 234                                 compatible = "fsl,mpc8641-dma-channel",
 235                                            "fsl,eloplus-dma-channel";
 236                                 reg = <0x0 0x80>;
 237                                 cell-index = <0>;
 238                                 interrupt-parent = <&mpic>;
 239                                 interrupts = <20 2>;
 240                         };
 241                         dma-channel@80 {
 242                                 compatible = "fsl,mpc8641-dma-channel",
 243                                            "fsl,eloplus-dma-channel";
 244                                 reg = <0x80 0x80>;
 245                                 cell-index = <1>;
 246                                 interrupt-parent = <&mpic>;
 247                                 interrupts = <21 2>;
 248                         };
 249                         dma-channel@100 {
 250                                 compatible = "fsl,mpc8641-dma-channel",
 251                                            "fsl,eloplus-dma-channel";
 252                                 reg = <0x100 0x80>;
 253                                 cell-index = <2>;
 254                                 interrupt-parent = <&mpic>;
 255                                 interrupts = <22 2>;
 256                         };
 257                         dma-channel@180 {
 258                                 compatible = "fsl,mpc8641-dma-channel",
 259                                            "fsl,eloplus-dma-channel";
 260                                 reg = <0x180 0x80>;
 261                                 cell-index = <3>;
 262                                 interrupt-parent = <&mpic>;
 263                                 interrupts = <23 2>;
 264                         };
 265                 };
 266
 267                 enet0: ethernet@24000 {
 268                         #address-cells = <1>;
 269                         #size-cells = <1>;
 270                         cell-index = <0>;
 271                         device_type = "network";
 272                         model = "TSEC";
 273                         compatible = "gianfar";
 274                         reg = <0x24000 0x1000>;
 275                         ranges = <0x0 0x24000 0x1000>;
 276                         local-mac-address = [ 00 00 00 00 00 00 ];
 277                         interrupts = <29 2 30  2 34 2>;
 278                         interrupt-parent = <&mpic>;
 279                         tbi-handle = <&tbi0>;
 280                         phy-handle = <&phy0>;
 281                         phy-connection-type = "gmii";
 282
 283                         mdio@520 {
 284                                 #address-cells = <1>;
 285                                 #size-cells = <0>;
 286                                 compatible = "fsl,gianfar-mdio";
 287                                 reg = <0x520 0x20>;
 288
 289                                 phy0: ethernet-phy@0 {
 290                                         interrupt-parent = <&gef_pic>;
 291                                         interrupts = <0x9 0x4>;
 292                                         reg = <1>;
 293                                 };
 294                                 phy2: ethernet-phy@2 {
 295                                         interrupt-parent = <&gef_pic>;
 296                                         interrupts = <0x8 0x4>;
 297                                         reg = <3>;
 298                                 };
 299                                 tbi0: tbi-phy@11 {
 300                                         reg = <0x11>;
 301                                         device_type = "tbi-phy";
 302                                 };
 303                         };
 304                 };
 305
 306                 enet1: ethernet@26000 {
 307                         #address-cells = <1>;
 308                         #size-cells = <1>;
 309                         cell-index = <2>;
 310                         device_type = "network";
 311                         model = "TSEC";
 312                         compatible = "gianfar";
 313                         reg = <0x26000 0x1000>;
 314                         ranges = <0x0 0x26000 0x1000>;
 315                         local-mac-address = [ 00 00 00 00 00 00 ];
 316                         interrupts = <31 2 32 2 33 2>;
 317                         interrupt-parent = <&mpic>;
 318                         tbi-handle = <&tbi2>;
 319                         phy-handle = <&phy2>;
 320                         phy-connection-type = "gmii";
 321
 322                         mdio@520 {
 323                                 #address-cells = <1>;
 324                                 #size-cells = <0>;
 325                                 compatible = "fsl,gianfar-tbi";
 326                                 reg = <0x520 0x20>;
 327
 328                                 tbi2: tbi-phy@11 {
 329                                         reg = <0x11>;
 330                                         device_type = "tbi-phy";
 331                                 };
 332                         };
 333                 };
 334
 335                 serial0: serial@4500 {
 336                         cell-index = <0>;
 337                         device_type = "serial";
 338                         compatible = "fsl,ns16550", "ns16550";
 339                         reg = <0x4500 0x100>;
 340                         clock-frequency = <0>;
 341                         interrupts = <0x2a 0x2>;
 342                         interrupt-parent = <&mpic>;
 343                 };
 344
 345                 serial1: serial@4600 {
 346                         cell-index = <1>;
 347                         device_type = "serial";
 348                         compatible = "fsl,ns16550", "ns16550";
 349                         reg = <0x4600 0x100>;
 350                         clock-frequency = <0>;
 351                         interrupts = <0x1c 0x2>;
 352                         interrupt-parent = <&mpic>;
 353                 };
 354
 355                 mpic: pic@40000 {
 356                         clock-frequency = <0>;
 357                         interrupt-controller;
 358                         #address-cells = <0>;
 359                         #interrupt-cells = <2>;
 360                         reg = <0x40000 0x40000>;
 361                         compatible = "chrp,open-pic";
 362                         device_type = "open-pic";
 363                 };
 364
 365                 msi@41600 {
 366                         compatible = "fsl,mpc8641-msi", "fsl,mpic-msi";
 367                         reg = <0x41600 0x80>;
 368                         msi-available-ranges = <0 0x100>;
 369                         interrupts = <
 370                                 0xe0 0
 371                                 0xe1 0
 372                                 0xe2 0
 373                                 0xe3 0
 374                                 0xe4 0
 375                                 0xe5 0
 376                                 0xe6 0
 377                                 0xe7 0>;
 378                         interrupt-parent = <&mpic>;
 379                 };
 380
 381                 global-utilities@e0000 {
 382                         compatible = "fsl,mpc8641-guts";
 383                         reg = <0xe0000 0x1000>;
 384                         fsl,has-rstcr;
 385                 };
 386         };
 387
 388         pci0: pcie@fef08000 {
 389                 compatible = "fsl,mpc8641-pcie";
 390                 device_type = "pci";
 391                 #interrupt-cells = <1>;
 392                 #size-cells = <2>;
 393                 #address-cells = <3>;
 394                 reg = <0xfef08000 0x1000>;
 395                 bus-range = <0x0 0xff>;
 396                 ranges = <0x02000000 0x0 0x80000000 0x80000000 0x0 0x40000000
 397                           0x01000000 0x0 0x00000000 0xfe000000 0x0 0x00400000>;
 398                 clock-frequency = <33333333>;
 399                 interrupt-parent = <&mpic>;
 400                 interrupts = <0x18 0x2>;
 401                 interrupt-map-mask = <0xff00 0x0 0x0 0x7>;
 402                 interrupt-map = <
 403                         0x0000 0x0 0x0 0x1 &mpic 0x0 0x2
 404                         0x0000 0x0 0x0 0x2 &mpic 0x1 0x2
 405                         0x0000 0x0 0x0 0x3 &mpic 0x2 0x2
 406                         0x0000 0x0 0x0 0x4 &mpic 0x3 0x2
 407                 >;
 408
 409                 pcie@0 {
 410                         reg = <0 0 0 0 0>;
 411                         #size-cells = <2>;
 412                         #address-cells = <3>;
 413                         device_type = "pci";
 414                         ranges = <0x02000000 0x0 0x80000000
 415                                   0x02000000 0x0 0x80000000
 416                                   0x0 0x40000000
 417
 418                                   0x01000000 0x0 0x00000000
 419                                   0x01000000 0x0 0x00000000
 420                                   0x0 0x00400000>;
 421                 };
 422         };
 423
 424         pci1: pcie@fef09000 {
 425                 compatible = "fsl,mpc8641-pcie";
 426                 device_type = "pci";
 427                 #interrupt-cells = <1>;
 428                 #size-cells = <2>;
 429                 #address-cells = <3>;
 430                 reg = <0xfef09000 0x1000>;
 431                 bus-range = <0x0 0xff>;
 432                 ranges = <0x02000000 0x0 0xc0000000 0xc0000000 0x0 0x20000000
 433                           0x01000000 0x0 0x00000000 0xfe400000 0x0 0x00400000>;
 434                 clock-frequency = <33333333>;
 435                 interrupt-parent = <&mpic>;
 436                 interrupts = <0x19 0x2>;
 437                 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
 438                 interrupt-map = <
 439                         0x0000 0x0 0x0 0x1 &mpic 0x4 0x2
 440                         0x0000 0x0 0x0 0x2 &mpic 0x5 0x2
 441                         0x0000 0x0 0x0 0x3 &mpic 0x6 0x2
 442                         0x0000 0x0 0x0 0x4 &mpic 0x7 0x2
 443                         >;
 444
 445                 pcie@0 {
 446                         reg = <0 0 0 0 0>;
 447                         #size-cells = <2>;
 448                         #address-cells = <3>;
 449                         device_type = "pci";
 450                         ranges = <0x02000000 0x0 0xc0000000
 451                                   0x02000000 0x0 0xc0000000
 452                                   0x0 0x20000000
 453
 454                                   0x01000000 0x0 0x00000000
 455                                   0x01000000 0x0 0x00000000
 456                                   0x0 0x00400000>;
 457                 };
 458         };
 459 };