kernel/arch/powerpc/boot/dts/fsl/t4240si-pre.dtsi

   1 /*
   2  * T4240 Silicon/SoC Device Tree Source (pre include)
   3  *
   4  * Copyright 2012 Freescale Semiconductor Inc.
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions are met:
   8  *     * Redistributions of source code must retain the above copyright
   9  *       notice, this list of conditions and the following disclaimer.
  10  *     * Redistributions in binary form must reproduce the above copyright
  11  *       notice, this list of conditions and the following disclaimer in the
  12  *       documentation and/or other materials provided with the distribution.
  13  *     * Neither the name of Freescale Semiconductor nor the
  14  *       names of its contributors may be used to endorse or promote products
  15  *       derived from this software without specific prior written permission.
  16  *
  17  *
  18  * ALTERNATIVELY, this software may be distributed under the terms of the
  19  * GNU General Public License ("GPL") as published by the Free Software
  20  * Foundation, either version 2 of that License or (at your option) any
  21  * later version.
  22  *
  23  * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
  24  * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  25  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  26  * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
  27  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  28  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  29  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
  30  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  31  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  32  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  33  */
  34
  35 /dts-v1/;
  36
  37 /include/ "e6500_power_isa.dtsi"
  38
  39 / {
  40         compatible = "fsl,T4240";
  41         #address-cells = <2>;
  42         #size-cells = <2>;
  43         interrupt-parent = <&mpic>;
  44
  45         aliases {
  46                 ccsr = &soc;
  47                 dcsr = &dcsr;
  48
  49                 serial0 = &serial0;
  50                 serial1 = &serial1;
  51                 serial2 = &serial2;
  52                 serial3 = &serial3;
  53                 crypto = &crypto;
  54                 pci0 = &pci0;
  55                 pci1 = &pci1;
  56                 pci2 = &pci2;
  57                 pci3 = &pci3;
  58                 dma0 = &dma0;
  59                 dma1 = &dma1;
  60                 dma2 = &dma2;
  61                 sdhc = &sdhc;
  62         };
  63
  64         cpus {
  65                 #address-cells = <1>;
  66                 #size-cells = <0>;
  67
  68                 cpu0: PowerPC,e6500@0 {
  69                         device_type = "cpu";
  70                         reg = <0 1>;
  71                         clocks = <&mux0>;
  72                         next-level-cache = <&L2_1>;
  73                         fsl,portid-mapping = <0x80000000>;
  74                 };
  75                 cpu1: PowerPC,e6500@2 {
  76                         device_type = "cpu";
  77                         reg = <2 3>;
  78                         clocks = <&mux0>;
  79                         next-level-cache = <&L2_1>;
  80                         fsl,portid-mapping = <0x80000000>;
  81                 };
  82                 cpu2: PowerPC,e6500@4 {
  83                         device_type = "cpu";
  84                         reg = <4 5>;
  85                         clocks = <&mux0>;
  86                         next-level-cache = <&L2_1>;
  87                         fsl,portid-mapping = <0x80000000>;
  88                 };
  89                 cpu3: PowerPC,e6500@6 {
  90                         device_type = "cpu";
  91                         reg = <6 7>;
  92                         clocks = <&mux0>;
  93                         next-level-cache = <&L2_1>;
  94                         fsl,portid-mapping = <0x80000000>;
  95                 };
  96                 cpu4: PowerPC,e6500@8 {
  97                         device_type = "cpu";
  98                         reg = <8 9>;
  99                         clocks = <&mux1>;
 100                         next-level-cache = <&L2_2>;
 101                         fsl,portid-mapping = <0x40000000>;
 102                 };
 103                 cpu5: PowerPC,e6500@10 {
 104                         device_type = "cpu";
 105                         reg = <10 11>;
 106                         clocks = <&mux1>;
 107                         next-level-cache = <&L2_2>;
 108                         fsl,portid-mapping = <0x40000000>;
 109                 };
 110                 cpu6: PowerPC,e6500@12 {
 111                         device_type = "cpu";
 112                         reg = <12 13>;
 113                         clocks = <&mux1>;
 114                         next-level-cache = <&L2_2>;
 115                         fsl,portid-mapping = <0x40000000>;
 116                 };
 117                 cpu7: PowerPC,e6500@14 {
 118                         device_type = "cpu";
 119                         reg = <14 15>;
 120                         clocks = <&mux1>;
 121                         next-level-cache = <&L2_2>;
 122                         fsl,portid-mapping = <0x40000000>;
 123                 };
 124                 cpu8: PowerPC,e6500@16 {
 125                         device_type = "cpu";
 126                         reg = <16 17>;
 127                         clocks = <&mux2>;
 128                         next-level-cache = <&L2_3>;
 129                         fsl,portid-mapping = <0x20000000>;
 130                 };
 131                 cpu9: PowerPC,e6500@18 {
 132                         device_type = "cpu";
 133                         reg = <18 19>;
 134                         clocks = <&mux2>;
 135                         next-level-cache = <&L2_3>;
 136                         fsl,portid-mapping = <0x20000000>;
 137                 };
 138                 cpu10: PowerPC,e6500@20 {
 139                         device_type = "cpu";
 140                         reg = <20 21>;
 141                         clocks = <&mux2>;
 142                         next-level-cache = <&L2_3>;
 143                         fsl,portid-mapping = <0x20000000>;
 144                 };
 145                 cpu11: PowerPC,e6500@22 {
 146                         device_type = "cpu";
 147                         reg = <22 23>;
 148                         clocks = <&mux2>;
 149                         next-level-cache = <&L2_3>;
 150                         fsl,portid-mapping = <0x20000000>;
 151                 };
 152         };
 153 };