kernel/arch/powerpc/boot/dts/fsl/t2081si-post.dtsi

   1 /*
   2  * T2081 Silicon/SoC Device Tree Source (post include)
   3  *
   4  * Copyright 2013 - 2014 Freescale Semiconductor Inc.
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions are met:
   8  *     * Redistributions of source code must retain the above copyright
   9  *       notice, this list of conditions and the following disclaimer.
  10  *     * Redistributions in binary form must reproduce the above copyright
  11  *       notice, this list of conditions and the following disclaimer in the
  12  *       documentation and/or other materials provided with the distribution.
  13  *     * Neither the name of Freescale Semiconductor nor the
  14  *       names of its contributors may be used to endorse or promote products
  15  *       derived from this software without specific prior written permission.
  16  *
  17  *
  18  * ALTERNATIVELY, this software may be distributed under the terms of the
  19  * GNU General Public License ("GPL") as published by the Free Software
  20  * Foundation, either version 2 of that License or (at your option) any
  21  * later version.
  22  *
  23  * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor "AS IS" AND ANY
  24  * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  25  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  26  * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
  27  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  28  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  29  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
  30  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  31  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  32  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  33  */
  34
  35 &bman_fbpr {
  36         compatible = "fsl,bman-fbpr";
  37         alloc-ranges = <0 0 0x10000 0>;
  38 };
  39
  40 &ifc {
  41         #address-cells = <2>;
  42         #size-cells = <1>;
  43         compatible = "fsl,ifc", "simple-bus";
  44         interrupts = <25 2 0 0>;
  45 };
  46
  47 /* controller at 0x240000 */
  48 &pci0 {
  49         compatible = "fsl,t2080-pcie", "fsl,qoriq-pcie-v3.0", "fsl,qoriq-pcie";
  50         device_type = "pci";
  51         #size-cells = <2>;
  52         #address-cells = <3>;
  53         bus-range = <0x0 0xff>;
  54         interrupts = <20 2 0 0>;
  55         fsl,iommu-parent = <&pamu0>;
  56         pcie@0 {
  57                 reg = <0 0 0 0 0>;
  58                 #interrupt-cells = <1>;
  59                 #size-cells = <2>;
  60                 #address-cells = <3>;
  61                 device_type = "pci";
  62                 interrupts = <20 2 0 0>;
  63                 interrupt-map-mask = <0xf800 0 0 7>;
  64                 interrupt-map = <
  65                         /* IDSEL 0x0 */
  66                         0000 0 0 1 &mpic 40 1 0 0
  67                         0000 0 0 2 &mpic 1 1 0 0
  68                         0000 0 0 3 &mpic 2 1 0 0
  69                         0000 0 0 4 &mpic 3 1 0 0
  70                 >;
  71         };
  72 };
  73
  74 /* controller at 0x250000 */
  75 &pci1 {
  76         compatible = "fsl,t2080-pcie", "fsl,qoriq-pcie-v3.0", "fsl,qoriq-pcie";
  77         device_type = "pci";
  78         #size-cells = <2>;
  79         #address-cells = <3>;
  80         bus-range = <0 0xff>;
  81         interrupts = <21 2 0 0>;
  82         fsl,iommu-parent = <&pamu0>;
  83         pcie@0 {
  84                 reg = <0 0 0 0 0>;
  85                 #interrupt-cells = <1>;
  86                 #size-cells = <2>;
  87                 #address-cells = <3>;
  88                 device_type = "pci";
  89                 interrupts = <21 2 0 0>;
  90                 interrupt-map-mask = <0xf800 0 0 7>;
  91                 interrupt-map = <
  92                         /* IDSEL 0x0 */
  93                         0000 0 0 1 &mpic 41 1 0 0
  94                         0000 0 0 2 &mpic 5 1 0 0
  95                         0000 0 0 3 &mpic 6 1 0 0
  96                         0000 0 0 4 &mpic 7 1 0 0
  97                 >;
  98         };
  99 };
 100
 101 /* controller at 0x260000 */
 102 &pci2 {
 103         compatible = "fsl,t2080-pcie", "fsl,qoriq-pcie-v3.0", "fsl,qoriq-pcie";
 104         device_type = "pci";
 105         #size-cells = <2>;
 106         #address-cells = <3>;
 107         bus-range = <0x0 0xff>;
 108         interrupts = <22 2 0 0>;
 109         fsl,iommu-parent = <&pamu0>;
 110         pcie@0 {
 111                 reg = <0 0 0 0 0>;
 112                 #interrupt-cells = <1>;
 113                 #size-cells = <2>;
 114                 #address-cells = <3>;
 115                 device_type = "pci";
 116                 interrupts = <22 2 0 0>;
 117                 interrupt-map-mask = <0xf800 0 0 7>;
 118                 interrupt-map = <
 119                         /* IDSEL 0x0 */
 120                         0000 0 0 1 &mpic 42 1 0 0
 121                         0000 0 0 2 &mpic 9 1 0 0
 122                         0000 0 0 3 &mpic 10 1 0 0
 123                         0000 0 0 4 &mpic 11 1 0 0
 124                 >;
 125         };
 126 };
 127
 128 /* controller at 0x270000 */
 129 &pci3 {
 130         compatible = "fsl,t2080-pcie", "fsl,qoriq-pcie-v3.0", "fsl,qoriq-pcie";
 131         device_type = "pci";
 132         #size-cells = <2>;
 133         #address-cells = <3>;
 134         bus-range = <0x0 0xff>;
 135         interrupts = <23 2 0 0>;
 136         fsl,iommu-parent = <&pamu0>;
 137         pcie@0 {
 138                 reg = <0 0 0 0 0>;
 139                 #interrupt-cells = <1>;
 140                 #size-cells = <2>;
 141                 #address-cells = <3>;
 142                 device_type = "pci";
 143                 interrupts = <23 2 0 0>;
 144                 interrupt-map-mask = <0xf800 0 0 7>;
 145                 interrupt-map = <
 146                         /* IDSEL 0x0 */
 147                         0000 0 0 1 &mpic 43 1 0 0
 148                         0000 0 0 2 &mpic 0 1 0 0
 149                         0000 0 0 3 &mpic 4 1 0 0
 150                         0000 0 0 4 &mpic 8 1 0 0
 151                 >;
 152         };
 153 };
 154
 155 &dcsr {
 156         #address-cells = <1>;
 157         #size-cells = <1>;
 158         compatible = "fsl,dcsr", "simple-bus";
 159
 160         dcsr-epu@0 {
 161                 compatible = "fsl,t2080-dcsr-epu", "fsl,dcsr-epu";
 162                 interrupts = <52 2 0 0
 163                               84 2 0 0
 164                               85 2 0 0
 165                               94 2 0 0
 166                               95 2 0 0>;
 167                 reg = <0x0 0x1000>;
 168         };
 169         dcsr-npc {
 170                 compatible = "fsl,t2080-dcsr-cnpc", "fsl,dcsr-cnpc";
 171                 reg = <0x1000 0x1000 0x1002000 0x10000>;
 172         };
 173         dcsr-nxc@2000 {
 174                 compatible = "fsl,dcsr-nxc";
 175                 reg = <0x2000 0x1000>;
 176         };
 177         dcsr-corenet {
 178                 compatible = "fsl,dcsr-corenet";
 179                 reg = <0x8000 0x1000 0x1A000 0x1000>;
 180         };
 181         dcsr-ocn@11000 {
 182                 compatible = "fsl,t2080-dcsr-ocn", "fsl,dcsr-ocn";
 183                 reg = <0x11000 0x1000>;
 184         };
 185         dcsr-ddr@12000 {
 186                 compatible = "fsl,dcsr-ddr";
 187                 dev-handle = <&ddr1>;
 188                 reg = <0x12000 0x1000>;
 189         };
 190         dcsr-nal@18000 {
 191                 compatible = "fsl,t2080-dcsr-nal", "fsl,dcsr-nal";
 192                 reg = <0x18000 0x1000>;
 193         };
 194         dcsr-rcpm@22000 {
 195                 compatible = "fsl,t2080-dcsr-rcpm", "fsl,dcsr-rcpm";
 196                 reg = <0x22000 0x1000>;
 197         };
 198         dcsr-snpc@30000 {
 199                 compatible = "fsl,t2080-dcsr-snpc", "fsl,dcsr-snpc";
 200                 reg = <0x30000 0x1000 0x1022000 0x10000>;
 201         };
 202         dcsr-snpc@31000 {
 203                 compatible = "fsl,t2080-dcsr-snpc", "fsl,dcsr-snpc";
 204                 reg = <0x31000 0x1000 0x1042000 0x10000>;
 205         };
 206         dcsr-snpc@32000 {
 207                 compatible = "fsl,t2080-dcsr-snpc", "fsl,dcsr-snpc";
 208                 reg = <0x32000 0x1000 0x1062000 0x10000>;
 209         };
 210         dcsr-cpu-sb-proxy@100000 {
 211                 compatible = "fsl,dcsr-e6500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
 212                 cpu-handle = <&cpu0>;
 213                 reg = <0x100000 0x1000 0x101000 0x1000>;
 214         };
 215         dcsr-cpu-sb-proxy@108000 {
 216                 compatible = "fsl,dcsr-e6500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
 217                 cpu-handle = <&cpu1>;
 218                 reg = <0x108000 0x1000 0x109000 0x1000>;
 219         };
 220         dcsr-cpu-sb-proxy@110000 {
 221                 compatible = "fsl,dcsr-e6500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
 222                 cpu-handle = <&cpu2>;
 223                 reg = <0x110000 0x1000 0x111000 0x1000>;
 224         };
 225         dcsr-cpu-sb-proxy@118000 {
 226                 compatible = "fsl,dcsr-e6500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
 227                 cpu-handle = <&cpu3>;
 228                 reg = <0x118000 0x1000 0x119000 0x1000>;
 229         };
 230 };
 231
 232 &bportals {
 233         #address-cells = <0x1>;
 234         #size-cells = <0x1>;
 235         compatible = "simple-bus";
 236
 237         bman-portal@0 {
 238                 compatible = "fsl,bman-portal";
 239                 reg = <0x0 0x4000>, <0x1000000 0x1000>;
 240                 interrupts = <105 2 0 0>;
 241         };
 242         bman-portal@4000 {
 243                 compatible = "fsl,bman-portal";
 244                 reg = <0x4000 0x4000>, <0x1001000 0x1000>;
 245                 interrupts = <107 2 0 0>;
 246         };
 247         bman-portal@8000 {
 248                 compatible = "fsl,bman-portal";
 249                 reg = <0x8000 0x4000>, <0x1002000 0x1000>;
 250                 interrupts = <109 2 0 0>;
 251         };
 252         bman-portal@c000 {
 253                 compatible = "fsl,bman-portal";
 254                 reg = <0xc000 0x4000>, <0x1003000 0x1000>;
 255                 interrupts = <111 2 0 0>;
 256         };
 257         bman-portal@10000 {
 258                 compatible = "fsl,bman-portal";
 259                 reg = <0x10000 0x4000>, <0x1004000 0x1000>;
 260                 interrupts = <113 2 0 0>;
 261         };
 262         bman-portal@14000 {
 263                 compatible = "fsl,bman-portal";
 264                 reg = <0x14000 0x4000>, <0x1005000 0x1000>;
 265                 interrupts = <115 2 0 0>;
 266         };
 267         bman-portal@18000 {
 268                 compatible = "fsl,bman-portal";
 269                 reg = <0x18000 0x4000>, <0x1006000 0x1000>;
 270                 interrupts = <117 2 0 0>;
 271         };
 272         bman-portal@1c000 {
 273                 compatible = "fsl,bman-portal";
 274                 reg = <0x1c000 0x4000>, <0x1007000 0x1000>;
 275                 interrupts = <119 2 0 0>;
 276         };
 277         bman-portal@20000 {
 278                 compatible = "fsl,bman-portal";
 279                 reg = <0x20000 0x4000>, <0x1008000 0x1000>;
 280                 interrupts = <121 2 0 0>;
 281         };
 282         bman-portal@24000 {
 283                 compatible = "fsl,bman-portal";
 284                 reg = <0x24000 0x4000>, <0x1009000 0x1000>;
 285                 interrupts = <123 2 0 0>;
 286         };
 287         bman-portal@28000 {
 288                 compatible = "fsl,bman-portal";
 289                 reg = <0x28000 0x4000>, <0x100a000 0x1000>;
 290                 interrupts = <125 2 0 0>;
 291         };
 292         bman-portal@2c000 {
 293                 compatible = "fsl,bman-portal";
 294                 reg = <0x2c000 0x4000>, <0x100b000 0x1000>;
 295                 interrupts = <127 2 0 0>;
 296         };
 297         bman-portal@30000 {
 298                 compatible = "fsl,bman-portal";
 299                 reg = <0x30000 0x4000>, <0x100c000 0x1000>;
 300                 interrupts = <129 2 0 0>;
 301         };
 302         bman-portal@34000 {
 303                 compatible = "fsl,bman-portal";
 304                 reg = <0x34000 0x4000>, <0x100d000 0x1000>;
 305                 interrupts = <131 2 0 0>;
 306         };
 307         bman-portal@38000 {
 308                 compatible = "fsl,bman-portal";
 309                 reg = <0x38000 0x4000>, <0x100e000 0x1000>;
 310                 interrupts = <133 2 0 0>;
 311         };
 312         bman-portal@3c000 {
 313                 compatible = "fsl,bman-portal";
 314                 reg = <0x3c000 0x4000>, <0x100f000 0x1000>;
 315                 interrupts = <135 2 0 0>;
 316         };
 317         bman-portal@40000 {
 318                 compatible = "fsl,bman-portal";
 319                 reg = <0x40000 0x4000>, <0x1010000 0x1000>;
 320                 interrupts = <137 2 0 0>;
 321         };
 322         bman-portal@44000 {
 323                 compatible = "fsl,bman-portal";
 324                 reg = <0x44000 0x4000>, <0x1011000 0x1000>;
 325                 interrupts = <139 2 0 0>;
 326         };
 327 };
 328
 329 &soc {
 330         #address-cells = <1>;
 331         #size-cells = <1>;
 332         device_type = "soc";
 333         compatible = "simple-bus";
 334
 335         soc-sram-error {
 336                 compatible = "fsl,soc-sram-error";
 337                 interrupts = <16 2 1 29>;
 338         };
 339
 340         corenet-law@0 {
 341                 compatible = "fsl,corenet-law";
 342                 reg = <0x0 0x1000>;
 343                 fsl,num-laws = <32>;
 344         };
 345
 346         ddr1: memory-controller@8000 {
 347                 compatible = "fsl,qoriq-memory-controller-v4.7",
 348                                 "fsl,qoriq-memory-controller";
 349                 reg = <0x8000 0x1000>;
 350                 interrupts = <16 2 1 23>;
 351         };
 352
 353         cpc: l3-cache-controller@10000 {
 354                 compatible = "fsl,t2080-l3-cache-controller", "cache";
 355                 reg = <0x10000 0x1000
 356                        0x11000 0x1000
 357                        0x12000 0x1000>;
 358                 interrupts = <16 2 1 27
 359                               16 2 1 26
 360                               16 2 1 25>;
 361         };
 362
 363         corenet-cf@18000 {
 364                 compatible = "fsl,corenet2-cf", "fsl,corenet-cf";
 365                 reg = <0x18000 0x1000>;
 366                 interrupts = <16 2 1 31>;
 367                 fsl,ccf-num-csdids = <32>;
 368                 fsl,ccf-num-snoopids = <32>;
 369         };
 370
 371         iommu@20000 {
 372                 compatible = "fsl,pamu-v1.0", "fsl,pamu";
 373                 reg = <0x20000 0x3000>;
 374                 fsl,portid-mapping = <0x8000>;
 375                 ranges = <0 0x20000 0x3000>;
 376                 #address-cells = <1>;
 377                 #size-cells = <1>;
 378                 interrupts = <
 379                         24 2 0 0
 380                         16 2 1 30>;
 381
 382                 pamu0: pamu@0 {
 383                         reg = <0 0x1000>;
 384                         fsl,primary-cache-geometry = <32 1>;
 385                         fsl,secondary-cache-geometry = <128 2>;
 386                 };
 387
 388                 pamu1: pamu@1000 {
 389                         reg = <0x1000 0x1000>;
 390                         fsl,primary-cache-geometry = <32 1>;
 391                         fsl,secondary-cache-geometry = <128 2>;
 392                 };
 393
 394                 pamu2: pamu@2000 {
 395                         reg = <0x2000 0x1000>;
 396                         fsl,primary-cache-geometry = <32 1>;
 397                         fsl,secondary-cache-geometry = <128 2>;
 398                 };
 399         };
 400
 401 /include/ "qoriq-mpic4.3.dtsi"
 402
 403         guts: global-utilities@e0000 {
 404                 compatible = "fsl,t2080-device-config", "fsl,qoriq-device-config-2.0";
 405                 reg = <0xe0000 0xe00>;
 406                 fsl,has-rstcr;
 407                 fsl,liodn-bits = <12>;
 408         };
 409
 410 /include/ "qoriq-clockgen2.dtsi"
 411         global-utilities@e1000 {
 412                 compatible = "fsl,t2080-clockgen", "fsl,qoriq-clockgen-2.0";
 413
 414                 mux0: mux0@0 {
 415                         #clock-cells = <0>;
 416                         reg = <0x0 4>;
 417                         compatible = "fsl,qoriq-core-mux-2.0";
 418                         clocks = <&pll0 0>, <&pll0 1>, <&pll0 2>,
 419                                  <&pll1 0>, <&pll1 1>, <&pll1 2>;
 420                         clock-names = "pll0", "pll0-div2", "pll1-div4",
 421                                 "pll1", "pll1-div2", "pll1-div4";
 422                         clock-output-names = "cmux0";
 423                 };
 424
 425                 mux1: mux1@20 {
 426                         #clock-cells = <0>;
 427                         reg = <0x20 4>;
 428                         compatible = "fsl,qoriq-core-mux-2.0";
 429                         clocks = <&pll0 0>, <&pll0 1>, <&pll0 2>,
 430                                  <&pll1 0>, <&pll1 1>, <&pll1 2>;
 431                         clock-names = "pll0", "pll0-div2", "pll1-div4",
 432                                 "pll1", "pll1-div2", "pll1-div4";
 433                         clock-output-names = "cmux1";
 434                 };
 435         };
 436
 437         rcpm: global-utilities@e2000 {
 438                 compatible = "fsl,t2080-rcpm", "fsl,qoriq-rcpm-2.0";
 439                 reg = <0xe2000 0x1000>;
 440         };
 441
 442         sfp: sfp@e8000 {
 443                 compatible = "fsl,t2080-sfp";
 444                 reg = <0xe8000 0x1000>;
 445         };
 446
 447         serdes: serdes@ea000 {
 448                 compatible = "fsl,t2080-serdes";
 449                 reg = <0xea000 0x4000>;
 450         };
 451
 452 /include/ "elo3-dma-0.dtsi"
 453         dma@100300 {
 454                 fsl,iommu-parent = <&pamu0>;
 455                 fsl,liodn-reg = <&guts 0x580>; /* DMA1LIODNR */
 456         };
 457 /include/ "elo3-dma-1.dtsi"
 458         dma@101300 {
 459                 fsl,iommu-parent = <&pamu0>;
 460                 fsl,liodn-reg = <&guts 0x584>; /* DMA2LIODNR */
 461         };
 462 /include/ "elo3-dma-2.dtsi"
 463         dma@102300 {
 464                 fsl,iommu-parent = <&pamu0>;
 465                 fsl,liodn-reg = <&guts 0x588>; /* DMA3LIODNR */
 466         };
 467
 468 /include/ "qoriq-espi-0.dtsi"
 469         spi@110000 {
 470                 fsl,espi-num-chipselects = <4>;
 471         };
 472
 473 /include/ "qoriq-esdhc-0.dtsi"
 474         sdhc@114000 {
 475                 compatible = "fsl,t2080-esdhc", "fsl,esdhc";
 476                 fsl,iommu-parent = <&pamu1>;
 477                 fsl,liodn-reg = <&guts 0x530>; /* SDMMCLIODNR */
 478                 sdhci,auto-cmd12;
 479         };
 480 /include/ "qoriq-i2c-0.dtsi"
 481 /include/ "qoriq-i2c-1.dtsi"
 482 /include/ "qoriq-duart-0.dtsi"
 483 /include/ "qoriq-duart-1.dtsi"
 484 /include/ "qoriq-gpio-0.dtsi"
 485 /include/ "qoriq-gpio-1.dtsi"
 486 /include/ "qoriq-gpio-2.dtsi"
 487 /include/ "qoriq-gpio-3.dtsi"
 488 /include/ "qoriq-usb2-mph-0.dtsi"
 489         usb0: usb@210000 {
 490                 compatible = "fsl-usb2-mph-v2.5", "fsl-usb2-mph";
 491                 fsl,iommu-parent = <&pamu1>;
 492                 fsl,liodn-reg = <&guts 0x520>; /* USB1LIODNR */
 493                 phy_type = "utmi";
 494                 port0;
 495         };
 496 /include/ "qoriq-usb2-dr-0.dtsi"
 497         usb1: usb@211000 {
 498                 compatible = "fsl-usb2-dr-v2.5", "fsl-usb2-dr";
 499                 fsl,iommu-parent = <&pamu1>;
 500                 fsl,liodn-reg = <&guts 0x524>; /* USB1LIODNR */
 501                 dr_mode = "host";
 502                 phy_type = "utmi";
 503         };
 504 /include/ "qoriq-sec5.2-0.dtsi"
 505 /include/ "qoriq-bman1.dtsi"
 506
 507         L2_1: l2-cache-controller@c20000 {
 508                 /* Cluster 0 L2 cache */
 509                 compatible = "fsl,t2080-l2-cache-controller";
 510                 reg = <0xc20000 0x40000>;
 511                 next-level-cache = <&cpc>;
 512         };
 513 };