2 * P4080/P4040 Silicon/SoC Device Tree Source (pre include)
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37 /include/ "e500mc_power_isa.dtsi"
40 compatible = "fsl,P4080";
43 interrupt-parent = <&mpic>;
81 cpu0: PowerPC,e500mc@0 {
85 next-level-cache = <&L2_0>;
86 fsl,portid-mapping = <0x80000000>;
88 next-level-cache = <&cpc>;
91 cpu1: PowerPC,e500mc@1 {
95 next-level-cache = <&L2_1>;
96 fsl,portid-mapping = <0x40000000>;
98 next-level-cache = <&cpc>;
101 cpu2: PowerPC,e500mc@2 {
105 next-level-cache = <&L2_2>;
106 fsl,portid-mapping = <0x20000000>;
108 next-level-cache = <&cpc>;
111 cpu3: PowerPC,e500mc@3 {
115 next-level-cache = <&L2_3>;
116 fsl,portid-mapping = <0x10000000>;
118 next-level-cache = <&cpc>;
121 cpu4: PowerPC,e500mc@4 {
125 next-level-cache = <&L2_4>;
126 fsl,portid-mapping = <0x08000000>;
128 next-level-cache = <&cpc>;
131 cpu5: PowerPC,e500mc@5 {
135 next-level-cache = <&L2_5>;
136 fsl,portid-mapping = <0x04000000>;
138 next-level-cache = <&cpc>;
141 cpu6: PowerPC,e500mc@6 {
145 next-level-cache = <&L2_6>;
146 fsl,portid-mapping = <0x02000000>;
148 next-level-cache = <&cpc>;
151 cpu7: PowerPC,e500mc@7 {
155 next-level-cache = <&L2_7>;
156 fsl,portid-mapping = <0x01000000>;
158 next-level-cache = <&cpc>;