kernel/arch/powerpc/boot/dts/fsl/p2020si-post.dtsi

   1 /*
   2  * P2020/P2010 Silicon/SoC Device Tree Source (post include)
   3  *
   4  * Copyright 2011 Freescale Semiconductor Inc.
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions are met:
   8  *     * Redistributions of source code must retain the above copyright
   9  *       notice, this list of conditions and the following disclaimer.
  10  *     * Redistributions in binary form must reproduce the above copyright
  11  *       notice, this list of conditions and the following disclaimer in the
  12  *       documentation and/or other materials provided with the distribution.
  13  *     * Neither the name of Freescale Semiconductor nor the
  14  *       names of its contributors may be used to endorse or promote products
  15  *       derived from this software without specific prior written permission.
  16  *
  17  *
  18  * ALTERNATIVELY, this software may be distributed under the terms of the
  19  * GNU General Public License ("GPL") as published by the Free Software
  20  * Foundation, either version 2 of that License or (at your option) any
  21  * later version.
  22  *
  23  * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
  24  * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  25  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  26  * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
  27  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  28  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  29  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
  30  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  31  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  32  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  33  */
  34
  35 &lbc {
  36         #address-cells = <2>;
  37         #size-cells = <1>;
  38         compatible = "fsl,p2020-elbc", "fsl,elbc", "simple-bus";
  39         interrupts = <19 2 0 0>;
  40 };
  41
  42 /* controller at 0xa000 */
  43 &pci0 {
  44         compatible = "fsl,mpc8548-pcie";
  45         device_type = "pci";
  46         #size-cells = <2>;
  47         #address-cells = <3>;
  48         bus-range = <0 255>;
  49         clock-frequency = <33333333>;
  50         interrupts = <26 2 0 0>;
  51
  52         pcie@0 {
  53                 reg = <0 0 0 0 0>;
  54                 #interrupt-cells = <1>;
  55                 #size-cells = <2>;
  56                 #address-cells = <3>;
  57                 device_type = "pci";
  58                 interrupts = <26 2 0 0>;
  59                 interrupt-map-mask = <0xf800 0 0 7>;
  60                 interrupt-map = <
  61                         /* IDSEL 0x0 */
  62                         0000 0x0 0x0 0x1 &mpic 0x0 0x1 0x0 0x0
  63                         0000 0x0 0x0 0x2 &mpic 0x1 0x1 0x0 0x0
  64                         0000 0x0 0x0 0x3 &mpic 0x2 0x1 0x0 0x0
  65                         0000 0x0 0x0 0x4 &mpic 0x3 0x1 0x0 0x0
  66                         >;
  67         };
  68 };
  69
  70 /* controller at 0x9000 */
  71 &pci1 {
  72         compatible = "fsl,mpc8548-pcie";
  73         device_type = "pci";
  74         #size-cells = <2>;
  75         #address-cells = <3>;
  76         bus-range = <0 255>;
  77         clock-frequency = <33333333>;
  78         interrupts = <25 2 0 0>;
  79
  80         pcie@0 {
  81                 reg = <0 0 0 0 0>;
  82                 #interrupt-cells = <1>;
  83                 #size-cells = <2>;
  84                 #address-cells = <3>;
  85                 device_type = "pci";
  86                 interrupts = <25 2 0 0>;
  87                 interrupt-map-mask = <0xf800 0 0 7>;
  88
  89                 interrupt-map = <
  90                         /* IDSEL 0x0 */
  91                         0000 0x0 0x0 0x1 &mpic 0x4 0x1 0x0 0x0
  92                         0000 0x0 0x0 0x2 &mpic 0x5 0x1 0x0 0x0
  93                         0000 0x0 0x0 0x3 &mpic 0x6 0x1 0x0 0x0
  94                         0000 0x0 0x0 0x4 &mpic 0x7 0x1 0x0 0x0
  95                         >;
  96         };
  97 };
  98
  99 /* controller at 0x8000 */
 100 &pci2 {
 101         compatible = "fsl,mpc8548-pcie";
 102         device_type = "pci";
 103         #size-cells = <2>;
 104         #address-cells = <3>;
 105         bus-range = <0 255>;
 106         clock-frequency = <33333333>;
 107         interrupts = <24 2 0 0>;
 108
 109         pcie@0 {
 110                 reg = <0 0 0 0 0>;
 111                 #interrupt-cells = <1>;
 112                 #size-cells = <2>;
 113                 #address-cells = <3>;
 114                 device_type = "pci";
 115                 interrupts = <24 2 0 0>;
 116                 interrupt-map-mask = <0xf800 0 0 7>;
 117
 118                 interrupt-map = <
 119                         /* IDSEL 0x0 */
 120                         0000 0x0 0x0 0x1 &mpic 0x8 0x1 0x0 0x0
 121                         0000 0x0 0x0 0x2 &mpic 0x9 0x1 0x0 0x0
 122                         0000 0x0 0x0 0x3 &mpic 0xa 0x1 0x0 0x0
 123                         0000 0x0 0x0 0x4 &mpic 0xb 0x1 0x0 0x0
 124                         >;
 125         };
 126 };
 127
 128 &soc {
 129         #address-cells = <1>;
 130         #size-cells = <1>;
 131         device_type = "soc";
 132         compatible = "fsl,p2020-immr", "simple-bus";
 133         bus-frequency = <0>;            // Filled out by uboot.
 134
 135         ecm-law@0 {
 136                 compatible = "fsl,ecm-law";
 137                 reg = <0x0 0x1000>;
 138                 fsl,num-laws = <12>;
 139         };
 140
 141         ecm@1000 {
 142                 compatible = "fsl,p2020-ecm", "fsl,ecm";
 143                 reg = <0x1000 0x1000>;
 144                 interrupts = <17 2 0 0>;
 145         };
 146
 147         memory-controller@2000 {
 148                 compatible = "fsl,p2020-memory-controller";
 149                 reg = <0x2000 0x1000>;
 150                 interrupts = <18 2 0 0>;
 151         };
 152
 153 /include/ "pq3-i2c-0.dtsi"
 154 /include/ "pq3-i2c-1.dtsi"
 155 /include/ "pq3-duart-0.dtsi"
 156 /include/ "pq3-espi-0.dtsi"
 157         spi0: spi@7000 {
 158                 fsl,espi-num-chipselects = <4>;
 159         };
 160
 161 /include/ "pq3-dma-1.dtsi"
 162 /include/ "pq3-gpio-0.dtsi"
 163
 164         L2: l2-cache-controller@20000 {
 165                 compatible = "fsl,p2020-l2-cache-controller";
 166                 reg = <0x20000 0x1000>;
 167                 cache-line-size = <32>; // 32 bytes
 168                 cache-size = <0x80000>; // L2,512K
 169                 interrupts = <16 2 0 0>;
 170         };
 171
 172 /include/ "pq3-dma-0.dtsi"
 173 /include/ "pq3-usb2-dr-0.dtsi"
 174         usb@22000 {
 175                 compatible = "fsl-usb2-dr-v1.6", "fsl-usb2-dr";
 176         };
 177 /include/ "pq3-etsec1-0.dtsi"
 178 /include/ "pq3-etsec1-timer-0.dtsi"
 179
 180         ptp_clock@24e00 {
 181                 interrupts = <68 2 0 0 69 2 0 0 70 2 0 0>;
 182         };
 183
 184
 185 /include/ "pq3-etsec1-1.dtsi"
 186 /include/ "pq3-etsec1-2.dtsi"
 187 /include/ "pq3-esdhc-0.dtsi"
 188         sdhc@2e000 {
 189                 compatible = "fsl,p2020-esdhc", "fsl,esdhc";
 190         };
 191
 192 /include/ "pq3-sec3.1-0.dtsi"
 193 /include/ "pq3-mpic.dtsi"
 194 /include/ "pq3-mpic-timer-B.dtsi"
 195
 196         global-utilities@e0000 {
 197                 compatible = "fsl,p2020-guts";
 198                 reg = <0xe0000 0x1000>;
 199                 fsl,has-rstcr;
 200         };
 201 };