kernel/arch/mips/mm/c-r4k.c

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * Copyright (C) 1996 David S. Miller (davem@davemloft.net)
   7  * Copyright (C) 1997, 1998, 1999, 2000, 2001, 2002 Ralf Baechle (ralf@gnu.org)
   8  * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
   9  */
  10 #include <linux/cpu_pm.h>
  11 #include <linux/hardirq.h>
  12 #include <linux/init.h>
  13 #include <linux/highmem.h>
  14 #include <linux/kernel.h>
  15 #include <linux/linkage.h>
  16 #include <linux/preempt.h>
  17 #include <linux/sched.h>
  18 #include <linux/smp.h>
  19 #include <linux/mm.h>
  20 #include <linux/module.h>
  21 #include <linux/bitops.h>
  22
  23 #include <asm/bcache.h>
  24 #include <asm/bootinfo.h>
  25 #include <asm/cache.h>
  26 #include <asm/cacheops.h>
  27 #include <asm/cpu.h>
  28 #include <asm/cpu-features.h>
  29 #include <asm/cpu-type.h>
  30 #include <asm/io.h>
  31 #include <asm/page.h>
  32 #include <asm/pgtable.h>
  33 #include <asm/r4kcache.h>
  34 #include <asm/sections.h>
  35 #include <asm/mmu_context.h>
  36 #include <asm/war.h>
  37 #include <asm/cacheflush.h> /* for run_uncached() */
  38 #include <asm/traps.h>
  39 #include <asm/dma-coherence.h>
  40
  41 /*
  42  * Special Variant of smp_call_function for use by cache functions:
  43  *
  44  *  o No return value
  45  *  o collapses to normal function call on UP kernels
  46  *  o collapses to normal function call on systems with a single shared
  47  *    primary cache.
  48  *  o doesn't disable interrupts on the local CPU
  49  */
  50 static inline void r4k_on_each_cpu(void (*func) (void *info), void *info)
  51 {
  52         preempt_disable();
  53
  54 #ifndef CONFIG_MIPS_MT_SMP
  55         smp_call_function(func, info, 1);
  56 #endif
  57         func(info);
  58         preempt_enable();
  59 }
  60
  61 #if defined(CONFIG_MIPS_CMP) || defined(CONFIG_MIPS_CPS)
  62 #define cpu_has_safe_index_cacheops 0
  63 #else
  64 #define cpu_has_safe_index_cacheops 1
  65 #endif
  66
  67 /*
  68  * Must die.
  69  */
  70 static unsigned long icache_size __read_mostly;
  71 static unsigned long dcache_size __read_mostly;
  72 static unsigned long scache_size __read_mostly;
  73
  74 /*
  75  * Dummy cache handling routines for machines without boardcaches
  76  */
  77 static void cache_noop(void) {}
  78
  79 static struct bcache_ops no_sc_ops = {
  80         .bc_enable = (void *)cache_noop,
  81         .bc_disable = (void *)cache_noop,
  82         .bc_wback_inv = (void *)cache_noop,
  83         .bc_inv = (void *)cache_noop
  84 };
  85
  86 struct bcache_ops *bcops = &no_sc_ops;
  87
  88 #define cpu_is_r4600_v1_x()     ((read_c0_prid() & 0xfffffff0) == 0x00002010)
  89 #define cpu_is_r4600_v2_x()     ((read_c0_prid() & 0xfffffff0) == 0x00002020)
  90
  91 #define R4600_HIT_CACHEOP_WAR_IMPL                                      \
  92 do {                                                                    \
  93         if (R4600_V2_HIT_CACHEOP_WAR && cpu_is_r4600_v2_x())            \
  94                 *(volatile unsigned long *)CKSEG1;                      \
  95         if (R4600_V1_HIT_CACHEOP_WAR)                                   \
  96                 __asm__ __volatile__("nop;nop;nop;nop");                \
  97 } while (0)
  98
  99 static void (*r4k_blast_dcache_page)(unsigned long addr);
 100
 101 static inline void r4k_blast_dcache_page_dc32(unsigned long addr)
 102 {
 103         R4600_HIT_CACHEOP_WAR_IMPL;
 104         blast_dcache32_page(addr);
 105 }
 106
 107 static inline void r4k_blast_dcache_page_dc64(unsigned long addr)
 108 {
 109         blast_dcache64_page(addr);
 110 }
 111
 112 static inline void r4k_blast_dcache_page_dc128(unsigned long addr)
 113 {
 114         blast_dcache128_page(addr);
 115 }
 116
 117 static void r4k_blast_dcache_page_setup(void)
 118 {
 119         unsigned long  dc_lsize = cpu_dcache_line_size();
 120
 121         switch (dc_lsize) {
 122         case 0:
 123                 r4k_blast_dcache_page = (void *)cache_noop;
 124                 break;
 125         case 16:
 126                 r4k_blast_dcache_page = blast_dcache16_page;
 127                 break;
 128         case 32:
 129                 r4k_blast_dcache_page = r4k_blast_dcache_page_dc32;
 130                 break;
 131         case 64:
 132                 r4k_blast_dcache_page = r4k_blast_dcache_page_dc64;
 133                 break;
 134         case 128:
 135                 r4k_blast_dcache_page = r4k_blast_dcache_page_dc128;
 136                 break;
 137         default:
 138                 break;
 139         }
 140 }
 141
 142 #ifndef CONFIG_EVA
 143 #define r4k_blast_dcache_user_page  r4k_blast_dcache_page
 144 #else
 145
 146 static void (*r4k_blast_dcache_user_page)(unsigned long addr);
 147
 148 static void r4k_blast_dcache_user_page_setup(void)
 149 {
 150         unsigned long  dc_lsize = cpu_dcache_line_size();
 151
 152         if (dc_lsize == 0)
 153                 r4k_blast_dcache_user_page = (void *)cache_noop;
 154         else if (dc_lsize == 16)
 155                 r4k_blast_dcache_user_page = blast_dcache16_user_page;
 156         else if (dc_lsize == 32)
 157                 r4k_blast_dcache_user_page = blast_dcache32_user_page;
 158         else if (dc_lsize == 64)
 159                 r4k_blast_dcache_user_page = blast_dcache64_user_page;
 160 }
 161
 162 #endif
 163
 164 static void (* r4k_blast_dcache_page_indexed)(unsigned long addr);
 165
 166 static void r4k_blast_dcache_page_indexed_setup(void)
 167 {
 168         unsigned long dc_lsize = cpu_dcache_line_size();
 169
 170         if (dc_lsize == 0)
 171                 r4k_blast_dcache_page_indexed = (void *)cache_noop;
 172         else if (dc_lsize == 16)
 173                 r4k_blast_dcache_page_indexed = blast_dcache16_page_indexed;
 174         else if (dc_lsize == 32)
 175                 r4k_blast_dcache_page_indexed = blast_dcache32_page_indexed;
 176         else if (dc_lsize == 64)
 177                 r4k_blast_dcache_page_indexed = blast_dcache64_page_indexed;
 178         else if (dc_lsize == 128)
 179                 r4k_blast_dcache_page_indexed = blast_dcache128_page_indexed;
 180 }
 181
 182 void (* r4k_blast_dcache)(void);
 183 EXPORT_SYMBOL(r4k_blast_dcache);
 184
 185 static void r4k_blast_dcache_setup(void)
 186 {
 187         unsigned long dc_lsize = cpu_dcache_line_size();
 188
 189         if (dc_lsize == 0)
 190                 r4k_blast_dcache = (void *)cache_noop;
 191         else if (dc_lsize == 16)
 192                 r4k_blast_dcache = blast_dcache16;
 193         else if (dc_lsize == 32)
 194                 r4k_blast_dcache = blast_dcache32;
 195         else if (dc_lsize == 64)
 196                 r4k_blast_dcache = blast_dcache64;
 197         else if (dc_lsize == 128)
 198                 r4k_blast_dcache = blast_dcache128;
 199 }
 200
 201 /* force code alignment (used for TX49XX_ICACHE_INDEX_INV_WAR) */
 202 #define JUMP_TO_ALIGN(order) \
 203         __asm__ __volatile__( \
 204                 "b\t1f\n\t" \
 205                 ".align\t" #order "\n\t" \
 206                 "1:\n\t" \
 207                 )
 208 #define CACHE32_UNROLL32_ALIGN  JUMP_TO_ALIGN(10) /* 32 * 32 = 1024 */
 209 #define CACHE32_UNROLL32_ALIGN2 JUMP_TO_ALIGN(11)
 210
 211 static inline void blast_r4600_v1_icache32(void)
 212 {
 213         unsigned long flags;
 214
 215         local_irq_save(flags);
 216         blast_icache32();
 217         local_irq_restore(flags);
 218 }
 219
 220 static inline void tx49_blast_icache32(void)
 221 {
 222         unsigned long start = INDEX_BASE;
 223         unsigned long end = start + current_cpu_data.icache.waysize;
 224         unsigned long ws_inc = 1UL << current_cpu_data.icache.waybit;
 225         unsigned long ws_end = current_cpu_data.icache.ways <<
 226                                current_cpu_data.icache.waybit;
 227         unsigned long ws, addr;
 228
 229         CACHE32_UNROLL32_ALIGN2;
 230         /* I'm in even chunk.  blast odd chunks */
 231         for (ws = 0; ws < ws_end; ws += ws_inc)
 232                 for (addr = start + 0x400; addr < end; addr += 0x400 * 2)
 233                         cache32_unroll32(addr|ws, Index_Invalidate_I);
 234         CACHE32_UNROLL32_ALIGN;
 235         /* I'm in odd chunk.  blast even chunks */
 236         for (ws = 0; ws < ws_end; ws += ws_inc)
 237                 for (addr = start; addr < end; addr += 0x400 * 2)
 238                         cache32_unroll32(addr|ws, Index_Invalidate_I);
 239 }
 240
 241 static inline void blast_icache32_r4600_v1_page_indexed(unsigned long page)
 242 {
 243         unsigned long flags;
 244
 245         local_irq_save(flags);
 246         blast_icache32_page_indexed(page);
 247         local_irq_restore(flags);
 248 }
 249
 250 static inline void tx49_blast_icache32_page_indexed(unsigned long page)
 251 {
 252         unsigned long indexmask = current_cpu_data.icache.waysize - 1;
 253         unsigned long start = INDEX_BASE + (page & indexmask);
 254         unsigned long end = start + PAGE_SIZE;
 255         unsigned long ws_inc = 1UL << current_cpu_data.icache.waybit;
 256         unsigned long ws_end = current_cpu_data.icache.ways <<
 257                                current_cpu_data.icache.waybit;
 258         unsigned long ws, addr;
 259
 260         CACHE32_UNROLL32_ALIGN2;
 261         /* I'm in even chunk.  blast odd chunks */
 262         for (ws = 0; ws < ws_end; ws += ws_inc)
 263                 for (addr = start + 0x400; addr < end; addr += 0x400 * 2)
 264                         cache32_unroll32(addr|ws, Index_Invalidate_I);
 265         CACHE32_UNROLL32_ALIGN;
 266         /* I'm in odd chunk.  blast even chunks */
 267         for (ws = 0; ws < ws_end; ws += ws_inc)
 268                 for (addr = start; addr < end; addr += 0x400 * 2)
 269                         cache32_unroll32(addr|ws, Index_Invalidate_I);
 270 }
 271
 272 static void (* r4k_blast_icache_page)(unsigned long addr);
 273
 274 static void r4k_blast_icache_page_setup(void)
 275 {
 276         unsigned long ic_lsize = cpu_icache_line_size();
 277
 278         if (ic_lsize == 0)
 279                 r4k_blast_icache_page = (void *)cache_noop;
 280         else if (ic_lsize == 16)
 281                 r4k_blast_icache_page = blast_icache16_page;
 282         else if (ic_lsize == 32 && current_cpu_type() == CPU_LOONGSON2)
 283                 r4k_blast_icache_page = loongson2_blast_icache32_page;
 284         else if (ic_lsize == 32)
 285                 r4k_blast_icache_page = blast_icache32_page;
 286         else if (ic_lsize == 64)
 287                 r4k_blast_icache_page = blast_icache64_page;
 288         else if (ic_lsize == 128)
 289                 r4k_blast_icache_page = blast_icache128_page;
 290 }
 291
 292 #ifndef CONFIG_EVA
 293 #define r4k_blast_icache_user_page  r4k_blast_icache_page
 294 #else
 295
 296 static void (*r4k_blast_icache_user_page)(unsigned long addr);
 297
 298 static void __cpuinit r4k_blast_icache_user_page_setup(void)
 299 {
 300         unsigned long ic_lsize = cpu_icache_line_size();
 301
 302         if (ic_lsize == 0)
 303                 r4k_blast_icache_user_page = (void *)cache_noop;
 304         else if (ic_lsize == 16)
 305                 r4k_blast_icache_user_page = blast_icache16_user_page;
 306         else if (ic_lsize == 32)
 307                 r4k_blast_icache_user_page = blast_icache32_user_page;
 308         else if (ic_lsize == 64)
 309                 r4k_blast_icache_user_page = blast_icache64_user_page;
 310 }
 311
 312 #endif
 313
 314 static void (* r4k_blast_icache_page_indexed)(unsigned long addr);
 315
 316 static void r4k_blast_icache_page_indexed_setup(void)
 317 {
 318         unsigned long ic_lsize = cpu_icache_line_size();
 319
 320         if (ic_lsize == 0)
 321                 r4k_blast_icache_page_indexed = (void *)cache_noop;
 322         else if (ic_lsize == 16)
 323                 r4k_blast_icache_page_indexed = blast_icache16_page_indexed;
 324         else if (ic_lsize == 32) {
 325                 if (R4600_V1_INDEX_ICACHEOP_WAR && cpu_is_r4600_v1_x())
 326                         r4k_blast_icache_page_indexed =
 327                                 blast_icache32_r4600_v1_page_indexed;
 328                 else if (TX49XX_ICACHE_INDEX_INV_WAR)
 329                         r4k_blast_icache_page_indexed =
 330                                 tx49_blast_icache32_page_indexed;
 331                 else if (current_cpu_type() == CPU_LOONGSON2)
 332                         r4k_blast_icache_page_indexed =
 333                                 loongson2_blast_icache32_page_indexed;
 334                 else
 335                         r4k_blast_icache_page_indexed =
 336                                 blast_icache32_page_indexed;
 337         } else if (ic_lsize == 64)
 338                 r4k_blast_icache_page_indexed = blast_icache64_page_indexed;
 339 }
 340
 341 void (* r4k_blast_icache)(void);
 342 EXPORT_SYMBOL(r4k_blast_icache);
 343
 344 static void r4k_blast_icache_setup(void)
 345 {
 346         unsigned long ic_lsize = cpu_icache_line_size();
 347
 348         if (ic_lsize == 0)
 349                 r4k_blast_icache = (void *)cache_noop;
 350         else if (ic_lsize == 16)
 351                 r4k_blast_icache = blast_icache16;
 352         else if (ic_lsize == 32) {
 353                 if (R4600_V1_INDEX_ICACHEOP_WAR && cpu_is_r4600_v1_x())
 354                         r4k_blast_icache = blast_r4600_v1_icache32;
 355                 else if (TX49XX_ICACHE_INDEX_INV_WAR)
 356                         r4k_blast_icache = tx49_blast_icache32;
 357                 else if (current_cpu_type() == CPU_LOONGSON2)
 358                         r4k_blast_icache = loongson2_blast_icache32;
 359                 else
 360                         r4k_blast_icache = blast_icache32;
 361         } else if (ic_lsize == 64)
 362                 r4k_blast_icache = blast_icache64;
 363         else if (ic_lsize == 128)
 364                 r4k_blast_icache = blast_icache128;
 365 }
 366
 367 static void (* r4k_blast_scache_page)(unsigned long addr);
 368
 369 static void r4k_blast_scache_page_setup(void)
 370 {
 371         unsigned long sc_lsize = cpu_scache_line_size();
 372
 373         if (scache_size == 0)
 374                 r4k_blast_scache_page = (void *)cache_noop;
 375         else if (sc_lsize == 16)
 376                 r4k_blast_scache_page = blast_scache16_page;
 377         else if (sc_lsize == 32)
 378                 r4k_blast_scache_page = blast_scache32_page;
 379         else if (sc_lsize == 64)
 380                 r4k_blast_scache_page = blast_scache64_page;
 381         else if (sc_lsize == 128)
 382                 r4k_blast_scache_page = blast_scache128_page;
 383 }
 384
 385 static void (* r4k_blast_scache_page_indexed)(unsigned long addr);
 386
 387 static void r4k_blast_scache_page_indexed_setup(void)
 388 {
 389         unsigned long sc_lsize = cpu_scache_line_size();
 390
 391         if (scache_size == 0)
 392                 r4k_blast_scache_page_indexed = (void *)cache_noop;
 393         else if (sc_lsize == 16)
 394                 r4k_blast_scache_page_indexed = blast_scache16_page_indexed;
 395         else if (sc_lsize == 32)
 396                 r4k_blast_scache_page_indexed = blast_scache32_page_indexed;
 397         else if (sc_lsize == 64)
 398                 r4k_blast_scache_page_indexed = blast_scache64_page_indexed;
 399         else if (sc_lsize == 128)
 400                 r4k_blast_scache_page_indexed = blast_scache128_page_indexed;
 401 }
 402
 403 static void (* r4k_blast_scache)(void);
 404
 405 static void r4k_blast_scache_setup(void)
 406 {
 407         unsigned long sc_lsize = cpu_scache_line_size();
 408
 409         if (scache_size == 0)
 410                 r4k_blast_scache = (void *)cache_noop;
 411         else if (sc_lsize == 16)
 412                 r4k_blast_scache = blast_scache16;
 413         else if (sc_lsize == 32)
 414                 r4k_blast_scache = blast_scache32;
 415         else if (sc_lsize == 64)
 416                 r4k_blast_scache = blast_scache64;
 417         else if (sc_lsize == 128)
 418                 r4k_blast_scache = blast_scache128;
 419 }
 420
 421 static inline void local_r4k___flush_cache_all(void * args)
 422 {
 423         switch (current_cpu_type()) {
 424         case CPU_LOONGSON2:
 425         case CPU_LOONGSON3:
 426         case CPU_R4000SC:
 427         case CPU_R4000MC:
 428         case CPU_R4400SC:
 429         case CPU_R4400MC:
 430         case CPU_R10000:
 431         case CPU_R12000:
 432         case CPU_R14000:
 433         case CPU_R16000:
 434                 /*
 435                  * These caches are inclusive caches, that is, if something
 436                  * is not cached in the S-cache, we know it also won't be
 437                  * in one of the primary caches.
 438                  */
 439                 r4k_blast_scache();
 440                 break;
 441
 442         default:
 443                 r4k_blast_dcache();
 444                 r4k_blast_icache();
 445                 break;
 446         }
 447 }
 448
 449 static void r4k___flush_cache_all(void)
 450 {
 451         r4k_on_each_cpu(local_r4k___flush_cache_all, NULL);
 452 }
 453
 454 static inline int has_valid_asid(const struct mm_struct *mm)
 455 {
 456 #ifdef CONFIG_MIPS_MT_SMP
 457         int i;
 458
 459         for_each_online_cpu(i)
 460                 if (cpu_context(i, mm))
 461                         return 1;
 462
 463         return 0;
 464 #else
 465         return cpu_context(smp_processor_id(), mm);
 466 #endif
 467 }
 468
 469 static void r4k__flush_cache_vmap(void)
 470 {
 471         r4k_blast_dcache();
 472 }
 473
 474 static void r4k__flush_cache_vunmap(void)
 475 {
 476         r4k_blast_dcache();
 477 }
 478
 479 static inline void local_r4k_flush_cache_range(void * args)
 480 {
 481         struct vm_area_struct *vma = args;
 482         int exec = vma->vm_flags & VM_EXEC;
 483
 484         if (!(has_valid_asid(vma->vm_mm)))
 485                 return;
 486
 487         r4k_blast_dcache();
 488         if (exec)
 489                 r4k_blast_icache();
 490 }
 491
 492 static void r4k_flush_cache_range(struct vm_area_struct *vma,
 493         unsigned long start, unsigned long end)
 494 {
 495         int exec = vma->vm_flags & VM_EXEC;
 496
 497         if (cpu_has_dc_aliases || (exec && !cpu_has_ic_fills_f_dc))
 498                 r4k_on_each_cpu(local_r4k_flush_cache_range, vma);
 499 }
 500
 501 static inline void local_r4k_flush_cache_mm(void * args)
 502 {
 503         struct mm_struct *mm = args;
 504
 505         if (!has_valid_asid(mm))
 506                 return;
 507
 508         /*
 509          * Kludge alert.  For obscure reasons R4000SC and R4400SC go nuts if we
 510          * only flush the primary caches but R1x000 behave sane ...
 511          * R4000SC and R4400SC indexed S-cache ops also invalidate primary
 512          * caches, so we can bail out early.
 513          */
 514         if (current_cpu_type() == CPU_R4000SC ||
 515             current_cpu_type() == CPU_R4000MC ||
 516             current_cpu_type() == CPU_R4400SC ||
 517             current_cpu_type() == CPU_R4400MC) {
 518                 r4k_blast_scache();
 519                 return;
 520         }
 521
 522         r4k_blast_dcache();
 523 }
 524
 525 static void r4k_flush_cache_mm(struct mm_struct *mm)
 526 {
 527         if (!cpu_has_dc_aliases)
 528                 return;
 529
 530         r4k_on_each_cpu(local_r4k_flush_cache_mm, mm);
 531 }
 532
 533 struct flush_cache_page_args {
 534         struct vm_area_struct *vma;
 535         unsigned long addr;
 536         unsigned long pfn;
 537 };
 538
 539 static inline void local_r4k_flush_cache_page(void *args)
 540 {
 541         struct flush_cache_page_args *fcp_args = args;
 542         struct vm_area_struct *vma = fcp_args->vma;
 543         unsigned long addr = fcp_args->addr;
 544         struct page *page = pfn_to_page(fcp_args->pfn);
 545         int exec = vma->vm_flags & VM_EXEC;
 546         struct mm_struct *mm = vma->vm_mm;
 547         int map_coherent = 0;
 548         pgd_t *pgdp;
 549         pud_t *pudp;
 550         pmd_t *pmdp;
 551         pte_t *ptep;
 552         void *vaddr;
 553
 554         /*
 555          * If ownes no valid ASID yet, cannot possibly have gotten
 556          * this page into the cache.
 557          */
 558         if (!has_valid_asid(mm))
 559                 return;
 560
 561         addr &= PAGE_MASK;
 562         pgdp = pgd_offset(mm, addr);
 563         pudp = pud_offset(pgdp, addr);
 564         pmdp = pmd_offset(pudp, addr);
 565         ptep = pte_offset(pmdp, addr);
 566
 567         /*
 568          * If the page isn't marked valid, the page cannot possibly be
 569          * in the cache.
 570          */
 571         if (!(pte_present(*ptep)))
 572                 return;
 573
 574         if ((mm == current->active_mm) && (pte_val(*ptep) & _PAGE_VALID))
 575                 vaddr = NULL;
 576         else {
 577                 /*
 578                  * Use kmap_coherent or kmap_atomic to do flushes for
 579                  * another ASID than the current one.
 580                  */
 581                 map_coherent = (cpu_has_dc_aliases &&
 582                                 page_mapped(page) && !Page_dcache_dirty(page));
 583                 if (map_coherent)
 584                         vaddr = kmap_coherent(page, addr);
 585                 else
 586                         vaddr = kmap_atomic(page);
 587                 addr = (unsigned long)vaddr;
 588         }
 589
 590         if (cpu_has_dc_aliases || (exec && !cpu_has_ic_fills_f_dc)) {
 591                 vaddr ? r4k_blast_dcache_page(addr) :
 592                         r4k_blast_dcache_user_page(addr);
 593                 if (exec && !cpu_icache_snoops_remote_store)
 594                         r4k_blast_scache_page(addr);
 595         }
 596         if (exec) {
 597                 if (vaddr && cpu_has_vtag_icache && mm == current->active_mm) {
 598                         int cpu = smp_processor_id();
 599
 600                         if (cpu_context(cpu, mm) != 0)
 601                                 drop_mmu_context(mm, cpu);
 602                 } else
 603                         vaddr ? r4k_blast_icache_page(addr) :
 604                                 r4k_blast_icache_user_page(addr);
 605         }
 606
 607         if (vaddr) {
 608                 if (map_coherent)
 609                         kunmap_coherent();
 610                 else
 611                         kunmap_atomic(vaddr);
 612         }
 613 }
 614
 615 static void r4k_flush_cache_page(struct vm_area_struct *vma,
 616         unsigned long addr, unsigned long pfn)
 617 {
 618         struct flush_cache_page_args args;
 619
 620         args.vma = vma;
 621         args.addr = addr;
 622         args.pfn = pfn;
 623
 624         r4k_on_each_cpu(local_r4k_flush_cache_page, &args);
 625 }
 626
 627 static inline void local_r4k_flush_data_cache_page(void * addr)
 628 {
 629         r4k_blast_dcache_page((unsigned long) addr);
 630 }
 631
 632 static void r4k_flush_data_cache_page(unsigned long addr)
 633 {
 634         if (in_atomic())
 635                 local_r4k_flush_data_cache_page((void *)addr);
 636         else
 637                 r4k_on_each_cpu(local_r4k_flush_data_cache_page, (void *) addr);
 638 }
 639
 640 struct flush_icache_range_args {
 641         unsigned long start;
 642         unsigned long end;
 643 };
 644
 645 static inline void local_r4k_flush_icache_range(unsigned long start, unsigned long end)
 646 {
 647         if (!cpu_has_ic_fills_f_dc) {
 648                 if (end - start >= dcache_size) {
 649                         r4k_blast_dcache();
 650                 } else {
 651                         R4600_HIT_CACHEOP_WAR_IMPL;
 652                         protected_blast_dcache_range(start, end);
 653                 }
 654         }
 655
 656         if (end - start > icache_size)
 657                 r4k_blast_icache();
 658         else {
 659                 switch (boot_cpu_type()) {
 660                 case CPU_LOONGSON2:
 661                         protected_loongson2_blast_icache_range(start, end);
 662                         break;
 663
 664                 default:
 665                         protected_blast_icache_range(start, end);
 666                         break;
 667                 }
 668         }
 669 #ifdef CONFIG_EVA
 670         /*
 671          * Due to all possible segment mappings, there might cache aliases
 672          * caused by the bootloader being in non-EVA mode, and the CPU switching
 673          * to EVA during early kernel init. It's best to flush the scache
 674          * to avoid having secondary cores fetching stale data and lead to
 675          * kernel crashes.
 676          */
 677         bc_wback_inv(start, (end - start));
 678         __sync();
 679 #endif
 680 }
 681
 682 static inline void local_r4k_flush_icache_range_ipi(void *args)
 683 {
 684         struct flush_icache_range_args *fir_args = args;
 685         unsigned long start = fir_args->start;
 686         unsigned long end = fir_args->end;
 687
 688         local_r4k_flush_icache_range(start, end);
 689 }
 690
 691 static void r4k_flush_icache_range(unsigned long start, unsigned long end)
 692 {
 693         struct flush_icache_range_args args;
 694
 695         args.start = start;
 696         args.end = end;
 697
 698         r4k_on_each_cpu(local_r4k_flush_icache_range_ipi, &args);
 699         instruction_hazard();
 700 }
 701
 702 #if defined(CONFIG_DMA_NONCOHERENT) || defined(CONFIG_DMA_MAYBE_COHERENT)
 703
 704 static void r4k_dma_cache_wback_inv(unsigned long addr, unsigned long size)
 705 {
 706         /* Catch bad driver code */
 707         BUG_ON(size == 0);
 708
 709         preempt_disable();
 710         if (cpu_has_inclusive_pcaches) {
 711                 if (size >= scache_size)
 712                         r4k_blast_scache();
 713                 else
 714                         blast_scache_range(addr, addr + size);
 715                 preempt_enable();
 716                 __sync();
 717                 return;
 718         }
 719
 720         /*
 721          * Either no secondary cache or the available caches don't have the
 722          * subset property so we have to flush the primary caches
 723          * explicitly
 724          */
 725         if (cpu_has_safe_index_cacheops && size >= dcache_size) {
 726                 r4k_blast_dcache();
 727         } else {
 728                 R4600_HIT_CACHEOP_WAR_IMPL;
 729                 blast_dcache_range(addr, addr + size);
 730         }
 731         preempt_enable();
 732
 733         bc_wback_inv(addr, size);
 734         __sync();
 735 }
 736
 737 static void r4k_dma_cache_inv(unsigned long addr, unsigned long size)
 738 {
 739         /* Catch bad driver code */
 740         BUG_ON(size == 0);
 741
 742         preempt_disable();
 743         if (cpu_has_inclusive_pcaches) {
 744                 if (size >= scache_size)
 745                         r4k_blast_scache();
 746                 else {
 747                         /*
 748                          * There is no clearly documented alignment requirement
 749                          * for the cache instruction on MIPS processors and
 750                          * some processors, among them the RM5200 and RM7000
 751                          * QED processors will throw an address error for cache
 752                          * hit ops with insufficient alignment.  Solved by
 753                          * aligning the address to cache line size.
 754                          */
 755                         blast_inv_scache_range(addr, addr + size);
 756                 }
 757                 preempt_enable();
 758                 __sync();
 759                 return;
 760         }
 761
 762         if (cpu_has_safe_index_cacheops && size >= dcache_size) {
 763                 r4k_blast_dcache();
 764         } else {
 765                 R4600_HIT_CACHEOP_WAR_IMPL;
 766                 blast_inv_dcache_range(addr, addr + size);
 767         }
 768         preempt_enable();
 769
 770         bc_inv(addr, size);
 771         __sync();
 772 }
 773 #endif /* CONFIG_DMA_NONCOHERENT || CONFIG_DMA_MAYBE_COHERENT */
 774
 775 /*
 776  * While we're protected against bad userland addresses we don't care
 777  * very much about what happens in that case.  Usually a segmentation
 778  * fault will dump the process later on anyway ...
 779  */
 780 static void local_r4k_flush_cache_sigtramp(void * arg)
 781 {
 782         unsigned long ic_lsize = cpu_icache_line_size();
 783         unsigned long dc_lsize = cpu_dcache_line_size();
 784         unsigned long sc_lsize = cpu_scache_line_size();
 785         unsigned long addr = (unsigned long) arg;
 786
 787         R4600_HIT_CACHEOP_WAR_IMPL;
 788         if (dc_lsize)
 789                 protected_writeback_dcache_line(addr & ~(dc_lsize - 1));
 790         if (!cpu_icache_snoops_remote_store && scache_size)
 791                 protected_writeback_scache_line(addr & ~(sc_lsize - 1));
 792         if (ic_lsize)
 793                 protected_flush_icache_line(addr & ~(ic_lsize - 1));
 794         if (MIPS4K_ICACHE_REFILL_WAR) {
 795                 __asm__ __volatile__ (
 796                         ".set push\n\t"
 797                         ".set noat\n\t"
 798                         ".set "MIPS_ISA_LEVEL"\n\t"
 799 #ifdef CONFIG_32BIT
 800                         "la     $at,1f\n\t"
 801 #endif
 802 #ifdef CONFIG_64BIT
 803                         "dla    $at,1f\n\t"
 804 #endif
 805                         "cache  %0,($at)\n\t"
 806                         "nop; nop; nop\n"
 807                         "1:\n\t"
 808                         ".set pop"
 809                         :
 810                         : "i" (Hit_Invalidate_I));
 811         }
 812         if (MIPS_CACHE_SYNC_WAR)
 813                 __asm__ __volatile__ ("sync");
 814 }
 815
 816 static void r4k_flush_cache_sigtramp(unsigned long addr)
 817 {
 818         r4k_on_each_cpu(local_r4k_flush_cache_sigtramp, (void *) addr);
 819 }
 820
 821 static void r4k_flush_icache_all(void)
 822 {
 823         if (cpu_has_vtag_icache)
 824                 r4k_blast_icache();
 825 }
 826
 827 struct flush_kernel_vmap_range_args {
 828         unsigned long   vaddr;
 829         int             size;
 830 };
 831
 832 static inline void local_r4k_flush_kernel_vmap_range(void *args)
 833 {
 834         struct flush_kernel_vmap_range_args *vmra = args;
 835         unsigned long vaddr = vmra->vaddr;
 836         int size = vmra->size;
 837
 838         /*
 839          * Aliases only affect the primary caches so don't bother with
 840          * S-caches or T-caches.
 841          */
 842         if (cpu_has_safe_index_cacheops && size >= dcache_size)
 843                 r4k_blast_dcache();
 844         else {
 845                 R4600_HIT_CACHEOP_WAR_IMPL;
 846                 blast_dcache_range(vaddr, vaddr + size);
 847         }
 848 }
 849
 850 static void r4k_flush_kernel_vmap_range(unsigned long vaddr, int size)
 851 {
 852         struct flush_kernel_vmap_range_args args;
 853
 854         args.vaddr = (unsigned long) vaddr;
 855         args.size = size;
 856
 857         r4k_on_each_cpu(local_r4k_flush_kernel_vmap_range, &args);
 858 }
 859
 860 static inline void rm7k_erratum31(void)
 861 {
 862         const unsigned long ic_lsize = 32;
 863         unsigned long addr;
 864
 865         /* RM7000 erratum #31. The icache is screwed at startup. */
 866         write_c0_taglo(0);
 867         write_c0_taghi(0);
 868
 869         for (addr = INDEX_BASE; addr <= INDEX_BASE + 4096; addr += ic_lsize) {
 870                 __asm__ __volatile__ (
 871                         ".set push\n\t"
 872                         ".set noreorder\n\t"
 873                         ".set mips3\n\t"
 874                         "cache\t%1, 0(%0)\n\t"
 875                         "cache\t%1, 0x1000(%0)\n\t"
 876                         "cache\t%1, 0x2000(%0)\n\t"
 877                         "cache\t%1, 0x3000(%0)\n\t"
 878                         "cache\t%2, 0(%0)\n\t"
 879                         "cache\t%2, 0x1000(%0)\n\t"
 880                         "cache\t%2, 0x2000(%0)\n\t"
 881                         "cache\t%2, 0x3000(%0)\n\t"
 882                         "cache\t%1, 0(%0)\n\t"
 883                         "cache\t%1, 0x1000(%0)\n\t"
 884                         "cache\t%1, 0x2000(%0)\n\t"
 885                         "cache\t%1, 0x3000(%0)\n\t"
 886                         ".set pop\n"
 887                         :
 888                         : "r" (addr), "i" (Index_Store_Tag_I), "i" (Fill));
 889         }
 890 }
 891
 892 static inline int alias_74k_erratum(struct cpuinfo_mips *c)
 893 {
 894         unsigned int imp = c->processor_id & PRID_IMP_MASK;
 895         unsigned int rev = c->processor_id & PRID_REV_MASK;
 896         int present = 0;
 897
 898         /*
 899          * Early versions of the 74K do not update the cache tags on a
 900          * vtag miss/ptag hit which can occur in the case of KSEG0/KUSEG
 901          * aliases.  In this case it is better to treat the cache as always
 902          * having aliases.  Also disable the synonym tag update feature
 903          * where available.  In this case no opportunistic tag update will
 904          * happen where a load causes a virtual address miss but a physical
 905          * address hit during a D-cache look-up.
 906          */
 907         switch (imp) {
 908         case PRID_IMP_74K:
 909                 if (rev <= PRID_REV_ENCODE_332(2, 4, 0))
 910                         present = 1;
 911                 if (rev == PRID_REV_ENCODE_332(2, 4, 0))
 912                         write_c0_config6(read_c0_config6() | MIPS_CONF6_SYND);
 913                 break;
 914         case PRID_IMP_1074K:
 915                 if (rev <= PRID_REV_ENCODE_332(1, 1, 0)) {
 916                         present = 1;
 917                         write_c0_config6(read_c0_config6() | MIPS_CONF6_SYND);
 918                 }
 919                 break;
 920         default:
 921                 BUG();
 922         }
 923
 924         return present;
 925 }
 926
 927 static void b5k_instruction_hazard(void)
 928 {
 929         __sync();
 930         __sync();
 931         __asm__ __volatile__(
 932         "       nop; nop; nop; nop; nop; nop; nop; nop\n"
 933         "       nop; nop; nop; nop; nop; nop; nop; nop\n"
 934         "       nop; nop; nop; nop; nop; nop; nop; nop\n"
 935         "       nop; nop; nop; nop; nop; nop; nop; nop\n"
 936         : : : "memory");
 937 }
 938
 939 static char *way_string[] = { NULL, "direct mapped", "2-way",
 940         "3-way", "4-way", "5-way", "6-way", "7-way", "8-way"
 941 };
 942
 943 static void probe_pcache(void)
 944 {
 945         struct cpuinfo_mips *c = &current_cpu_data;
 946         unsigned int config = read_c0_config();
 947         unsigned int prid = read_c0_prid();
 948         int has_74k_erratum = 0;
 949         unsigned long config1;
 950         unsigned int lsize;
 951
 952         switch (current_cpu_type()) {
 953         case CPU_R4600:                 /* QED style two way caches? */
 954         case CPU_R4700:
 955         case CPU_R5000:
 956         case CPU_NEVADA:
 957                 icache_size = 1 << (12 + ((config & CONF_IC) >> 9));
 958                 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
 959                 c->icache.ways = 2;
 960                 c->icache.waybit = __ffs(icache_size/2);
 961
 962                 dcache_size = 1 << (12 + ((config & CONF_DC) >> 6));
 963                 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
 964                 c->dcache.ways = 2;
 965                 c->dcache.waybit= __ffs(dcache_size/2);
 966
 967                 c->options |= MIPS_CPU_CACHE_CDEX_P;
 968                 break;
 969
 970         case CPU_R5432:
 971         case CPU_R5500:
 972                 icache_size = 1 << (12 + ((config & CONF_IC) >> 9));
 973                 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
 974                 c->icache.ways = 2;
 975                 c->icache.waybit= 0;
 976
 977                 dcache_size = 1 << (12 + ((config & CONF_DC) >> 6));
 978                 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
 979                 c->dcache.ways = 2;
 980                 c->dcache.waybit = 0;
 981
 982                 c->options |= MIPS_CPU_CACHE_CDEX_P | MIPS_CPU_PREFETCH;
 983                 break;
 984
 985         case CPU_TX49XX:
 986                 icache_size = 1 << (12 + ((config & CONF_IC) >> 9));
 987                 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
 988                 c->icache.ways = 4;
 989                 c->icache.waybit= 0;
 990
 991                 dcache_size = 1 << (12 + ((config & CONF_DC) >> 6));
 992                 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
 993                 c->dcache.ways = 4;
 994                 c->dcache.waybit = 0;
 995
 996                 c->options |= MIPS_CPU_CACHE_CDEX_P;
 997                 c->options |= MIPS_CPU_PREFETCH;
 998                 break;
 999
1000         case CPU_R4000PC:
1001         case CPU_R4000SC:
1002         case CPU_R4000MC:
1003         case CPU_R4400PC:
1004         case CPU_R4400SC:
1005         case CPU_R4400MC:
1006         case CPU_R4300:
1007                 icache_size = 1 << (12 + ((config & CONF_IC) >> 9));
1008                 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
1009                 c->icache.ways = 1;
1010                 c->icache.waybit = 0;   /* doesn't matter */
1011
1012                 dcache_size = 1 << (12 + ((config & CONF_DC) >> 6));
1013                 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
1014                 c->dcache.ways = 1;
1015                 c->dcache.waybit = 0;   /* does not matter */
1016
1017                 c->options |= MIPS_CPU_CACHE_CDEX_P;
1018                 break;
1019
1020         case CPU_R10000:
1021         case CPU_R12000:
1022         case CPU_R14000:
1023         case CPU_R16000:
1024                 icache_size = 1 << (12 + ((config & R10K_CONF_IC) >> 29));
1025                 c->icache.linesz = 64;
1026                 c->icache.ways = 2;
1027                 c->icache.waybit = 0;
1028
1029                 dcache_size = 1 << (12 + ((config & R10K_CONF_DC) >> 26));
1030                 c->dcache.linesz = 32;
1031                 c->dcache.ways = 2;
1032                 c->dcache.waybit = 0;
1033
1034                 c->options |= MIPS_CPU_PREFETCH;
1035                 break;
1036
1037         case CPU_VR4133:
1038                 write_c0_config(config & ~VR41_CONF_P4K);
1039         case CPU_VR4131:
1040                 /* Workaround for cache instruction bug of VR4131 */
1041                 if (c->processor_id == 0x0c80U || c->processor_id == 0x0c81U ||
1042                     c->processor_id == 0x0c82U) {
1043                         config |= 0x00400000U;
1044                         if (c->processor_id == 0x0c80U)
1045                                 config |= VR41_CONF_BP;
1046                         write_c0_config(config);
1047                 } else
1048                         c->options |= MIPS_CPU_CACHE_CDEX_P;
1049
1050                 icache_size = 1 << (10 + ((config & CONF_IC) >> 9));
1051                 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
1052                 c->icache.ways = 2;
1053                 c->icache.waybit = __ffs(icache_size/2);
1054
1055                 dcache_size = 1 << (10 + ((config & CONF_DC) >> 6));
1056                 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
1057                 c->dcache.ways = 2;
1058                 c->dcache.waybit = __ffs(dcache_size/2);
1059                 break;
1060
1061         case CPU_VR41XX:
1062         case CPU_VR4111:
1063         case CPU_VR4121:
1064         case CPU_VR4122:
1065         case CPU_VR4181:
1066         case CPU_VR4181A:
1067                 icache_size = 1 << (10 + ((config & CONF_IC) >> 9));
1068                 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
1069                 c->icache.ways = 1;
1070                 c->icache.waybit = 0;   /* doesn't matter */
1071
1072                 dcache_size = 1 << (10 + ((config & CONF_DC) >> 6));
1073                 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
1074                 c->dcache.ways = 1;
1075                 c->dcache.waybit = 0;   /* does not matter */
1076
1077                 c->options |= MIPS_CPU_CACHE_CDEX_P;
1078                 break;
1079
1080         case CPU_RM7000:
1081                 rm7k_erratum31();
1082
1083                 icache_size = 1 << (12 + ((config & CONF_IC) >> 9));
1084                 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
1085                 c->icache.ways = 4;
1086                 c->icache.waybit = __ffs(icache_size / c->icache.ways);
1087
1088                 dcache_size = 1 << (12 + ((config & CONF_DC) >> 6));
1089                 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
1090                 c->dcache.ways = 4;
1091                 c->dcache.waybit = __ffs(dcache_size / c->dcache.ways);
1092
1093                 c->options |= MIPS_CPU_CACHE_CDEX_P;
1094                 c->options |= MIPS_CPU_PREFETCH;
1095                 break;
1096
1097         case CPU_LOONGSON2:
1098                 icache_size = 1 << (12 + ((config & CONF_IC) >> 9));
1099                 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
1100                 if (prid & 0x3)
1101                         c->icache.ways = 4;
1102                 else
1103                         c->icache.ways = 2;
1104                 c->icache.waybit = 0;
1105
1106                 dcache_size = 1 << (12 + ((config & CONF_DC) >> 6));
1107                 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
1108                 if (prid & 0x3)
1109                         c->dcache.ways = 4;
1110                 else
1111                         c->dcache.ways = 2;
1112                 c->dcache.waybit = 0;
1113                 break;
1114
1115         case CPU_LOONGSON3:
1116                 config1 = read_c0_config1();
1117                 lsize = (config1 >> 19) & 7;
1118                 if (lsize)
1119                         c->icache.linesz = 2 << lsize;
1120                 else
1121                         c->icache.linesz = 0;
1122                 c->icache.sets = 64 << ((config1 >> 22) & 7);
1123                 c->icache.ways = 1 + ((config1 >> 16) & 7);
1124                 icache_size = c->icache.sets *
1125                                           c->icache.ways *
1126                                           c->icache.linesz;
1127                 c->icache.waybit = 0;
1128
1129                 lsize = (config1 >> 10) & 7;
1130                 if (lsize)
1131                         c->dcache.linesz = 2 << lsize;
1132                 else
1133                         c->dcache.linesz = 0;
1134                 c->dcache.sets = 64 << ((config1 >> 13) & 7);
1135                 c->dcache.ways = 1 + ((config1 >> 7) & 7);
1136                 dcache_size = c->dcache.sets *
1137                                           c->dcache.ways *
1138                                           c->dcache.linesz;
1139                 c->dcache.waybit = 0;
1140                 break;
1141
1142         case CPU_CAVIUM_OCTEON3:
1143                 /* For now lie about the number of ways. */
1144                 c->icache.linesz = 128;
1145                 c->icache.sets = 16;
1146                 c->icache.ways = 8;
1147                 c->icache.flags |= MIPS_CACHE_VTAG;
1148                 icache_size = c->icache.sets * c->icache.ways * c->icache.linesz;
1149
1150                 c->dcache.linesz = 128;
1151                 c->dcache.ways = 8;
1152                 c->dcache.sets = 8;
1153                 dcache_size = c->dcache.sets * c->dcache.ways * c->dcache.linesz;
1154                 c->options |= MIPS_CPU_PREFETCH;
1155                 break;
1156
1157         default:
1158                 if (!(config & MIPS_CONF_M))
1159                         panic("Don't know how to probe P-caches on this cpu.");
1160
1161                 /*
1162                  * So we seem to be a MIPS32 or MIPS64 CPU
1163                  * So let's probe the I-cache ...
1164                  */
1165                 config1 = read_c0_config1();
1166
1167                 lsize = (config1 >> 19) & 7;
1168
1169                 /* IL == 7 is reserved */
1170                 if (lsize == 7)
1171                         panic("Invalid icache line size");
1172
1173                 c->icache.linesz = lsize ? 2 << lsize : 0;
1174
1175                 c->icache.sets = 32 << (((config1 >> 22) + 1) & 7);
1176                 c->icache.ways = 1 + ((config1 >> 16) & 7);
1177
1178                 icache_size = c->icache.sets *
1179                               c->icache.ways *
1180                               c->icache.linesz;
1181                 c->icache.waybit = __ffs(icache_size/c->icache.ways);
1182
1183                 if (config & 0x8)               /* VI bit */
1184                         c->icache.flags |= MIPS_CACHE_VTAG;
1185
1186                 /*
1187                  * Now probe the MIPS32 / MIPS64 data cache.
1188                  */
1189                 c->dcache.flags = 0;
1190
1191                 lsize = (config1 >> 10) & 7;
1192
1193                 /* DL == 7 is reserved */
1194                 if (lsize == 7)
1195                         panic("Invalid dcache line size");
1196
1197                 c->dcache.linesz = lsize ? 2 << lsize : 0;
1198
1199                 c->dcache.sets = 32 << (((config1 >> 13) + 1) & 7);
1200                 c->dcache.ways = 1 + ((config1 >> 7) & 7);
1201
1202                 dcache_size = c->dcache.sets *
1203                               c->dcache.ways *
1204                               c->dcache.linesz;
1205                 c->dcache.waybit = __ffs(dcache_size/c->dcache.ways);
1206
1207                 c->options |= MIPS_CPU_PREFETCH;
1208                 break;
1209         }
1210
1211         /*
1212          * Processor configuration sanity check for the R4000SC erratum
1213          * #5.  With page sizes larger than 32kB there is no possibility
1214          * to get a VCE exception anymore so we don't care about this
1215          * misconfiguration.  The case is rather theoretical anyway;
1216          * presumably no vendor is shipping his hardware in the "bad"
1217          * configuration.
1218          */
1219         if ((prid & PRID_IMP_MASK) == PRID_IMP_R4000 &&
1220             (prid & PRID_REV_MASK) < PRID_REV_R4400 &&
1221             !(config & CONF_SC) && c->icache.linesz != 16 &&
1222             PAGE_SIZE <= 0x8000)
1223                 panic("Improper R4000SC processor configuration detected");
1224
1225         /* compute a couple of other cache variables */
1226         c->icache.waysize = icache_size / c->icache.ways;
1227         c->dcache.waysize = dcache_size / c->dcache.ways;
1228
1229         c->icache.sets = c->icache.linesz ?
1230                 icache_size / (c->icache.linesz * c->icache.ways) : 0;
1231         c->dcache.sets = c->dcache.linesz ?
1232                 dcache_size / (c->dcache.linesz * c->dcache.ways) : 0;
1233
1234         /*
1235          * R1x000 P-caches are odd in a positive way.  They're 32kB 2-way
1236          * virtually indexed so normally would suffer from aliases.  So
1237          * normally they'd suffer from aliases but magic in the hardware deals
1238          * with that for us so we don't need to take care ourselves.
1239          */
1240         switch (current_cpu_type()) {
1241         case CPU_20KC:
1242         case CPU_25KF:
1243         case CPU_SB1:
1244         case CPU_SB1A:
1245         case CPU_XLR:
1246                 c->dcache.flags |= MIPS_CACHE_PINDEX;
1247                 break;
1248
1249         case CPU_R10000:
1250         case CPU_R12000:
1251         case CPU_R14000:
1252         case CPU_R16000:
1253                 break;
1254
1255         case CPU_74K:
1256         case CPU_1074K:
1257                 has_74k_erratum = alias_74k_erratum(c);
1258                 /* Fall through. */
1259         case CPU_M14KC:
1260         case CPU_M14KEC:
1261         case CPU_24K:
1262         case CPU_34K:
1263         case CPU_1004K:
1264         case CPU_INTERAPTIV:
1265         case CPU_P5600:
1266         case CPU_PROAPTIV:
1267         case CPU_M5150:
1268         case CPU_QEMU_GENERIC:
1269                 if (!(read_c0_config7() & MIPS_CONF7_IAR) &&
1270                     (c->icache.waysize > PAGE_SIZE))
1271                         c->icache.flags |= MIPS_CACHE_ALIASES;
1272                 if (!has_74k_erratum && (read_c0_config7() & MIPS_CONF7_AR)) {
1273                         /*
1274                          * Effectively physically indexed dcache,
1275                          * thus no virtual aliases.
1276                         */
1277                         c->dcache.flags |= MIPS_CACHE_PINDEX;
1278                         break;
1279                 }
1280         default:
1281                 if (has_74k_erratum || c->dcache.waysize > PAGE_SIZE)
1282                         c->dcache.flags |= MIPS_CACHE_ALIASES;
1283         }
1284
1285         switch (current_cpu_type()) {
1286         case CPU_20KC:
1287                 /*
1288                  * Some older 20Kc chips doesn't have the 'VI' bit in
1289                  * the config register.
1290                  */
1291                 c->icache.flags |= MIPS_CACHE_VTAG;
1292                 break;
1293
1294         case CPU_ALCHEMY:
1295                 c->icache.flags |= MIPS_CACHE_IC_F_DC;
1296                 break;
1297
1298         case CPU_LOONGSON2:
1299                 /*
1300                  * LOONGSON2 has 4 way icache, but when using indexed cache op,
1301                  * one op will act on all 4 ways
1302                  */
1303                 c->icache.ways = 1;
1304         }
1305
1306         printk("Primary instruction cache %ldkB, %s, %s, linesize %d bytes.\n",
1307                icache_size >> 10,
1308                c->icache.flags & MIPS_CACHE_VTAG ? "VIVT" : "VIPT",
1309                way_string[c->icache.ways], c->icache.linesz);
1310
1311         printk("Primary data cache %ldkB, %s, %s, %s, linesize %d bytes\n",
1312                dcache_size >> 10, way_string[c->dcache.ways],
1313                (c->dcache.flags & MIPS_CACHE_PINDEX) ? "PIPT" : "VIPT",
1314                (c->dcache.flags & MIPS_CACHE_ALIASES) ?
1315                         "cache aliases" : "no aliases",
1316                c->dcache.linesz);
1317 }
1318
1319 /*
1320  * If you even _breathe_ on this function, look at the gcc output and make sure
1321  * it does not pop things on and off the stack for the cache sizing loop that
1322  * executes in KSEG1 space or else you will crash and burn badly.  You have
1323  * been warned.
1324  */
1325 static int probe_scache(void)
1326 {
1327         unsigned long flags, addr, begin, end, pow2;
1328         unsigned int config = read_c0_config();
1329         struct cpuinfo_mips *c = &current_cpu_data;
1330
1331         if (config & CONF_SC)
1332                 return 0;
1333
1334         begin = (unsigned long) &_stext;
1335         begin &= ~((4 * 1024 * 1024) - 1);
1336         end = begin + (4 * 1024 * 1024);
1337
1338         /*
1339          * This is such a bitch, you'd think they would make it easy to do
1340          * this.  Away you daemons of stupidity!
1341          */
1342         local_irq_save(flags);
1343
1344         /* Fill each size-multiple cache line with a valid tag. */
1345         pow2 = (64 * 1024);
1346         for (addr = begin; addr < end; addr = (begin + pow2)) {
1347                 unsigned long *p = (unsigned long *) addr;
1348                 __asm__ __volatile__("nop" : : "r" (*p)); /* whee... */
1349                 pow2 <<= 1;
1350         }
1351
1352         /* Load first line with zero (therefore invalid) tag. */
1353         write_c0_taglo(0);
1354         write_c0_taghi(0);
1355         __asm__ __volatile__("nop; nop; nop; nop;"); /* avoid the hazard */
1356         cache_op(Index_Store_Tag_I, begin);
1357         cache_op(Index_Store_Tag_D, begin);
1358         cache_op(Index_Store_Tag_SD, begin);
1359
1360         /* Now search for the wrap around point. */
1361         pow2 = (128 * 1024);
1362         for (addr = begin + (128 * 1024); addr < end; addr = begin + pow2) {
1363                 cache_op(Index_Load_Tag_SD, addr);
1364                 __asm__ __volatile__("nop; nop; nop; nop;"); /* hazard... */
1365                 if (!read_c0_taglo())
1366                         break;
1367                 pow2 <<= 1;
1368         }
1369         local_irq_restore(flags);
1370         addr -= begin;
1371
1372         scache_size = addr;
1373         c->scache.linesz = 16 << ((config & R4K_CONF_SB) >> 22);
1374         c->scache.ways = 1;
1375         c->scache.waybit = 0;           /* does not matter */
1376
1377         return 1;
1378 }
1379
1380 static void __init loongson2_sc_init(void)
1381 {
1382         struct cpuinfo_mips *c = &current_cpu_data;
1383
1384         scache_size = 512*1024;
1385         c->scache.linesz = 32;
1386         c->scache.ways = 4;
1387         c->scache.waybit = 0;
1388         c->scache.waysize = scache_size / (c->scache.ways);
1389         c->scache.sets = scache_size / (c->scache.linesz * c->scache.ways);
1390         pr_info("Unified secondary cache %ldkB %s, linesize %d bytes.\n",
1391                scache_size >> 10, way_string[c->scache.ways], c->scache.linesz);
1392
1393         c->options |= MIPS_CPU_INCLUSIVE_CACHES;
1394 }
1395
1396 static void __init loongson3_sc_init(void)
1397 {
1398         struct cpuinfo_mips *c = &current_cpu_data;
1399         unsigned int config2, lsize;
1400
1401         config2 = read_c0_config2();
1402         lsize = (config2 >> 4) & 15;
1403         if (lsize)
1404                 c->scache.linesz = 2 << lsize;
1405         else
1406                 c->scache.linesz = 0;
1407         c->scache.sets = 64 << ((config2 >> 8) & 15);
1408         c->scache.ways = 1 + (config2 & 15);
1409
1410         scache_size = c->scache.sets *
1411                                   c->scache.ways *
1412                                   c->scache.linesz;
1413         /* Loongson-3 has 4 cores, 1MB scache for each. scaches are shared */
1414         scache_size *= 4;
1415         c->scache.waybit = 0;
1416         pr_info("Unified secondary cache %ldkB %s, linesize %d bytes.\n",
1417                scache_size >> 10, way_string[c->scache.ways], c->scache.linesz);
1418         if (scache_size)
1419                 c->options |= MIPS_CPU_INCLUSIVE_CACHES;
1420         return;
1421 }
1422
1423 extern int r5k_sc_init(void);
1424 extern int rm7k_sc_init(void);
1425 extern int mips_sc_init(void);
1426
1427 static void setup_scache(void)
1428 {
1429         struct cpuinfo_mips *c = &current_cpu_data;
1430         unsigned int config = read_c0_config();
1431         int sc_present = 0;
1432
1433         /*
1434          * Do the probing thing on R4000SC and R4400SC processors.  Other
1435          * processors don't have a S-cache that would be relevant to the
1436          * Linux memory management.
1437          */
1438         switch (current_cpu_type()) {
1439         case CPU_R4000SC:
1440         case CPU_R4000MC:
1441         case CPU_R4400SC:
1442         case CPU_R4400MC:
1443                 sc_present = run_uncached(probe_scache);
1444                 if (sc_present)
1445                         c->options |= MIPS_CPU_CACHE_CDEX_S;
1446                 break;
1447
1448         case CPU_R10000:
1449         case CPU_R12000:
1450         case CPU_R14000:
1451         case CPU_R16000:
1452                 scache_size = 0x80000 << ((config & R10K_CONF_SS) >> 16);
1453                 c->scache.linesz = 64 << ((config >> 13) & 1);
1454                 c->scache.ways = 2;
1455                 c->scache.waybit= 0;
1456                 sc_present = 1;
1457                 break;
1458
1459         case CPU_R5000:
1460         case CPU_NEVADA:
1461 #ifdef CONFIG_R5000_CPU_SCACHE
1462                 r5k_sc_init();
1463 #endif
1464                 return;
1465
1466         case CPU_RM7000:
1467 #ifdef CONFIG_RM7000_CPU_SCACHE
1468                 rm7k_sc_init();
1469 #endif
1470                 return;
1471
1472         case CPU_LOONGSON2:
1473                 loongson2_sc_init();
1474                 return;
1475
1476         case CPU_LOONGSON3:
1477                 loongson3_sc_init();
1478                 return;
1479
1480         case CPU_CAVIUM_OCTEON3:
1481         case CPU_XLP:
1482                 /* don't need to worry about L2, fully coherent */
1483                 return;
1484
1485         default:
1486                 if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M32R2 |
1487                                     MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R1 |
1488                                     MIPS_CPU_ISA_M64R2 | MIPS_CPU_ISA_M64R6)) {
1489 #ifdef CONFIG_MIPS_CPU_SCACHE
1490                         if (mips_sc_init ()) {
1491                                 scache_size = c->scache.ways * c->scache.sets * c->scache.linesz;
1492                                 printk("MIPS secondary cache %ldkB, %s, linesize %d bytes.\n",
1493                                        scache_size >> 10,
1494                                        way_string[c->scache.ways], c->scache.linesz);
1495                         }
1496 #else
1497                         if (!(c->scache.flags & MIPS_CACHE_NOT_PRESENT))
1498                                 panic("Dunno how to handle MIPS32 / MIPS64 second level cache");
1499 #endif
1500                         return;
1501                 }
1502                 sc_present = 0;
1503         }
1504
1505         if (!sc_present)
1506                 return;
1507
1508         /* compute a couple of other cache variables */
1509         c->scache.waysize = scache_size / c->scache.ways;
1510
1511         c->scache.sets = scache_size / (c->scache.linesz * c->scache.ways);
1512
1513         printk("Unified secondary cache %ldkB %s, linesize %d bytes.\n",
1514                scache_size >> 10, way_string[c->scache.ways], c->scache.linesz);
1515
1516         c->options |= MIPS_CPU_INCLUSIVE_CACHES;
1517 }
1518
1519 void au1x00_fixup_config_od(void)
1520 {
1521         /*
1522          * c0_config.od (bit 19) was write only (and read as 0)
1523          * on the early revisions of Alchemy SOCs.  It disables the bus
1524          * transaction overlapping and needs to be set to fix various errata.
1525          */
1526         switch (read_c0_prid()) {
1527         case 0x00030100: /* Au1000 DA */
1528         case 0x00030201: /* Au1000 HA */
1529         case 0x00030202: /* Au1000 HB */
1530         case 0x01030200: /* Au1500 AB */
1531         /*
1532          * Au1100 errata actually keeps silence about this bit, so we set it
1533          * just in case for those revisions that require it to be set according
1534          * to the (now gone) cpu table.
1535          */
1536         case 0x02030200: /* Au1100 AB */
1537         case 0x02030201: /* Au1100 BA */
1538         case 0x02030202: /* Au1100 BC */
1539                 set_c0_config(1 << 19);
1540                 break;
1541         }
1542 }
1543
1544 /* CP0 hazard avoidance. */
1545 #define NXP_BARRIER()                                                   \
1546          __asm__ __volatile__(                                          \
1547         ".set noreorder\n\t"                                            \
1548         "nop; nop; nop; nop; nop; nop;\n\t"                             \
1549         ".set reorder\n\t")
1550
1551 static void nxp_pr4450_fixup_config(void)
1552 {
1553         unsigned long config0;
1554
1555         config0 = read_c0_config();
1556
1557         /* clear all three cache coherency fields */
1558         config0 &= ~(0x7 | (7 << 25) | (7 << 28));
1559         config0 |= (((_page_cachable_default >> _CACHE_SHIFT) <<  0) |
1560                     ((_page_cachable_default >> _CACHE_SHIFT) << 25) |
1561                     ((_page_cachable_default >> _CACHE_SHIFT) << 28));
1562         write_c0_config(config0);
1563         NXP_BARRIER();
1564 }
1565
1566 static int cca = -1;
1567
1568 static int __init cca_setup(char *str)
1569 {
1570         get_option(&str, &cca);
1571
1572         return 0;
1573 }
1574
1575 early_param("cca", cca_setup);
1576
1577 static void coherency_setup(void)
1578 {
1579         if (cca < 0 || cca > 7)
1580                 cca = read_c0_config() & CONF_CM_CMASK;
1581         _page_cachable_default = cca << _CACHE_SHIFT;
1582
1583         pr_debug("Using cache attribute %d\n", cca);
1584         change_c0_config(CONF_CM_CMASK, cca);
1585
1586         /*
1587          * c0_status.cu=0 specifies that updates by the sc instruction use
1588          * the coherency mode specified by the TLB; 1 means cachable
1589          * coherent update on write will be used.  Not all processors have
1590          * this bit and; some wire it to zero, others like Toshiba had the
1591          * silly idea of putting something else there ...
1592          */
1593         switch (current_cpu_type()) {
1594         case CPU_R4000PC:
1595         case CPU_R4000SC:
1596         case CPU_R4000MC:
1597         case CPU_R4400PC:
1598         case CPU_R4400SC:
1599         case CPU_R4400MC:
1600                 clear_c0_config(CONF_CU);
1601                 break;
1602         /*
1603          * We need to catch the early Alchemy SOCs with
1604          * the write-only co_config.od bit and set it back to one on:
1605          * Au1000 rev DA, HA, HB;  Au1100 AB, BA, BC, Au1500 AB
1606          */
1607         case CPU_ALCHEMY:
1608                 au1x00_fixup_config_od();
1609                 break;
1610
1611         case PRID_IMP_PR4450:
1612                 nxp_pr4450_fixup_config();
1613                 break;
1614         }
1615 }
1616
1617 static void r4k_cache_error_setup(void)
1618 {
1619         extern char __weak except_vec2_generic;
1620         extern char __weak except_vec2_sb1;
1621
1622         switch (current_cpu_type()) {
1623         case CPU_SB1:
1624         case CPU_SB1A:
1625                 set_uncached_handler(0x100, &except_vec2_sb1, 0x80);
1626                 break;
1627
1628         default:
1629                 set_uncached_handler(0x100, &except_vec2_generic, 0x80);
1630                 break;
1631         }
1632 }
1633
1634 void r4k_cache_init(void)
1635 {
1636         extern void build_clear_page(void);
1637         extern void build_copy_page(void);
1638         struct cpuinfo_mips *c = &current_cpu_data;
1639
1640         probe_pcache();
1641         setup_scache();
1642
1643         r4k_blast_dcache_page_setup();
1644         r4k_blast_dcache_page_indexed_setup();
1645         r4k_blast_dcache_setup();
1646         r4k_blast_icache_page_setup();
1647         r4k_blast_icache_page_indexed_setup();
1648         r4k_blast_icache_setup();
1649         r4k_blast_scache_page_setup();
1650         r4k_blast_scache_page_indexed_setup();
1651         r4k_blast_scache_setup();
1652 #ifdef CONFIG_EVA
1653         r4k_blast_dcache_user_page_setup();
1654         r4k_blast_icache_user_page_setup();
1655 #endif
1656
1657         /*
1658          * Some MIPS32 and MIPS64 processors have physically indexed caches.
1659          * This code supports virtually indexed processors and will be
1660          * unnecessarily inefficient on physically indexed processors.
1661          */
1662         if (c->dcache.linesz)
1663                 shm_align_mask = max_t( unsigned long,
1664                                         c->dcache.sets * c->dcache.linesz - 1,
1665                                         PAGE_SIZE - 1);
1666         else
1667                 shm_align_mask = PAGE_SIZE-1;
1668
1669         __flush_cache_vmap      = r4k__flush_cache_vmap;
1670         __flush_cache_vunmap    = r4k__flush_cache_vunmap;
1671
1672         flush_cache_all         = cache_noop;
1673         __flush_cache_all       = r4k___flush_cache_all;
1674         flush_cache_mm          = r4k_flush_cache_mm;
1675         flush_cache_page        = r4k_flush_cache_page;
1676         flush_cache_range       = r4k_flush_cache_range;
1677
1678         __flush_kernel_vmap_range = r4k_flush_kernel_vmap_range;
1679
1680         flush_cache_sigtramp    = r4k_flush_cache_sigtramp;
1681         flush_icache_all        = r4k_flush_icache_all;
1682         local_flush_data_cache_page     = local_r4k_flush_data_cache_page;
1683         flush_data_cache_page   = r4k_flush_data_cache_page;
1684         flush_icache_range      = r4k_flush_icache_range;
1685         local_flush_icache_range        = local_r4k_flush_icache_range;
1686
1687 #if defined(CONFIG_DMA_NONCOHERENT) || defined(CONFIG_DMA_MAYBE_COHERENT)
1688         if (coherentio) {
1689                 _dma_cache_wback_inv    = (void *)cache_noop;
1690                 _dma_cache_wback        = (void *)cache_noop;
1691                 _dma_cache_inv          = (void *)cache_noop;
1692         } else {
1693                 _dma_cache_wback_inv    = r4k_dma_cache_wback_inv;
1694                 _dma_cache_wback        = r4k_dma_cache_wback_inv;
1695                 _dma_cache_inv          = r4k_dma_cache_inv;
1696         }
1697 #endif
1698
1699         build_clear_page();
1700         build_copy_page();
1701
1702         /*
1703          * We want to run CMP kernels on core with and without coherent
1704          * caches. Therefore, do not use CONFIG_MIPS_CMP to decide whether
1705          * or not to flush caches.
1706          */
1707         local_r4k___flush_cache_all(NULL);
1708
1709         coherency_setup();
1710         board_cache_error_setup = r4k_cache_error_setup;
1711
1712         /*
1713          * Per-CPU overrides
1714          */
1715         switch (current_cpu_type()) {
1716         case CPU_BMIPS4350:
1717         case CPU_BMIPS4380:
1718                 /* No IPI is needed because all CPUs share the same D$ */
1719                 flush_data_cache_page = r4k_blast_dcache_page;
1720                 break;
1721         case CPU_BMIPS5000:
1722                 /* We lose our superpowers if L2 is disabled */
1723                 if (c->scache.flags & MIPS_CACHE_NOT_PRESENT)
1724                         break;
1725
1726                 /* I$ fills from D$ just by emptying the write buffers */
1727                 flush_cache_page = (void *)b5k_instruction_hazard;
1728                 flush_cache_range = (void *)b5k_instruction_hazard;
1729                 flush_cache_sigtramp = (void *)b5k_instruction_hazard;
1730                 local_flush_data_cache_page = (void *)b5k_instruction_hazard;
1731                 flush_data_cache_page = (void *)b5k_instruction_hazard;
1732                 flush_icache_range = (void *)b5k_instruction_hazard;
1733                 local_flush_icache_range = (void *)b5k_instruction_hazard;
1734
1735                 /* Cache aliases are handled in hardware; allow HIGHMEM */
1736                 current_cpu_data.dcache.flags &= ~MIPS_CACHE_ALIASES;
1737
1738                 /* Optimization: an L2 flush implicitly flushes the L1 */
1739                 current_cpu_data.options |= MIPS_CPU_INCLUSIVE_CACHES;
1740                 break;
1741         }
1742 }
1743
1744 static int r4k_cache_pm_notifier(struct notifier_block *self, unsigned long cmd,
1745                                void *v)
1746 {
1747         switch (cmd) {
1748         case CPU_PM_ENTER_FAILED:
1749         case CPU_PM_EXIT:
1750                 coherency_setup();
1751                 break;
1752         }
1753
1754         return NOTIFY_OK;
1755 }
1756
1757 static struct notifier_block r4k_cache_pm_notifier_block = {
1758         .notifier_call = r4k_cache_pm_notifier,
1759 };
1760
1761 int __init r4k_cache_init_pm(void)
1762 {
1763         return cpu_pm_register_notifier(&r4k_cache_pm_notifier_block);
1764 }
1765 arch_initcall(r4k_cache_init_pm);