kernel/arch/mips/kernel/cpu-probe.c

   1 /*
   2  * Processor capabilities determination functions.
   3  *
   4  * Copyright (C) xxxx  the Anonymous
   5  * Copyright (C) 1994 - 2006 Ralf Baechle
   6  * Copyright (C) 2003, 2004  Maciej W. Rozycki
   7  * Copyright (C) 2001, 2004, 2011, 2012  MIPS Technologies, Inc.
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License
  11  * as published by the Free Software Foundation; either version
  12  * 2 of the License, or (at your option) any later version.
  13  */
  14 #include <linux/init.h>
  15 #include <linux/kernel.h>
  16 #include <linux/ptrace.h>
  17 #include <linux/smp.h>
  18 #include <linux/stddef.h>
  19 #include <linux/export.h>
  20
  21 #include <asm/bugs.h>
  22 #include <asm/cpu.h>
  23 #include <asm/cpu-features.h>
  24 #include <asm/cpu-type.h>
  25 #include <asm/fpu.h>
  26 #include <asm/mipsregs.h>
  27 #include <asm/mipsmtregs.h>
  28 #include <asm/msa.h>
  29 #include <asm/watch.h>
  30 #include <asm/elf.h>
  31 #include <asm/pgtable-bits.h>
  32 #include <asm/spram.h>
  33 #include <asm/uaccess.h>
  34
  35 /*
  36  * Get the FPU Implementation/Revision.
  37  */
  38 static inline unsigned long cpu_get_fpu_id(void)
  39 {
  40         unsigned long tmp, fpu_id;
  41
  42         tmp = read_c0_status();
  43         __enable_fpu(FPU_AS_IS);
  44         fpu_id = read_32bit_cp1_register(CP1_REVISION);
  45         write_c0_status(tmp);
  46         return fpu_id;
  47 }
  48
  49 /*
  50  * Check if the CPU has an external FPU.
  51  */
  52 static inline int __cpu_has_fpu(void)
  53 {
  54         return (cpu_get_fpu_id() & FPIR_IMP_MASK) != FPIR_IMP_NONE;
  55 }
  56
  57 static inline unsigned long cpu_get_msa_id(void)
  58 {
  59         unsigned long status, msa_id;
  60
  61         status = read_c0_status();
  62         __enable_fpu(FPU_64BIT);
  63         enable_msa();
  64         msa_id = read_msa_ir();
  65         disable_msa();
  66         write_c0_status(status);
  67         return msa_id;
  68 }
  69
  70 /*
  71  * Determine the FCSR mask for FPU hardware.
  72  */
  73 static inline void cpu_set_fpu_fcsr_mask(struct cpuinfo_mips *c)
  74 {
  75         unsigned long sr, mask, fcsr, fcsr0, fcsr1;
  76
  77         fcsr = c->fpu_csr31;
  78         mask = FPU_CSR_ALL_X | FPU_CSR_ALL_E | FPU_CSR_ALL_S | FPU_CSR_RM;
  79
  80         sr = read_c0_status();
  81         __enable_fpu(FPU_AS_IS);
  82
  83         fcsr0 = fcsr & mask;
  84         write_32bit_cp1_register(CP1_STATUS, fcsr0);
  85         fcsr0 = read_32bit_cp1_register(CP1_STATUS);
  86
  87         fcsr1 = fcsr | ~mask;
  88         write_32bit_cp1_register(CP1_STATUS, fcsr1);
  89         fcsr1 = read_32bit_cp1_register(CP1_STATUS);
  90
  91         write_32bit_cp1_register(CP1_STATUS, fcsr);
  92
  93         write_c0_status(sr);
  94
  95         c->fpu_msk31 = ~(fcsr0 ^ fcsr1) & ~mask;
  96 }
  97
  98 /*
  99  * Set the FIR feature flags for the FPU emulator.
 100  */
 101 static void cpu_set_nofpu_id(struct cpuinfo_mips *c)
 102 {
 103         u32 value;
 104
 105         value = 0;
 106         if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1 |
 107                             MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 |
 108                             MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6))
 109                 value |= MIPS_FPIR_D | MIPS_FPIR_S;
 110         if (c->isa_level & (MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 |
 111                             MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6))
 112                 value |= MIPS_FPIR_F64 | MIPS_FPIR_L | MIPS_FPIR_W;
 113         c->fpu_id = value;
 114 }
 115
 116 /* Determined FPU emulator mask to use for the boot CPU with "nofpu".  */
 117 static unsigned int mips_nofpu_msk31;
 118
 119 /*
 120  * Set options for FPU hardware.
 121  */
 122 static void cpu_set_fpu_opts(struct cpuinfo_mips *c)
 123 {
 124         c->fpu_id = cpu_get_fpu_id();
 125         mips_nofpu_msk31 = c->fpu_msk31;
 126
 127         if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1 |
 128                             MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 |
 129                             MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6)) {
 130                 if (c->fpu_id & MIPS_FPIR_3D)
 131                         c->ases |= MIPS_ASE_MIPS3D;
 132                 if (c->fpu_id & MIPS_FPIR_FREP)
 133                         c->options |= MIPS_CPU_FRE;
 134         }
 135
 136         cpu_set_fpu_fcsr_mask(c);
 137 }
 138
 139 /*
 140  * Set options for the FPU emulator.
 141  */
 142 static void cpu_set_nofpu_opts(struct cpuinfo_mips *c)
 143 {
 144         c->options &= ~MIPS_CPU_FPU;
 145         c->fpu_msk31 = mips_nofpu_msk31;
 146
 147         cpu_set_nofpu_id(c);
 148 }
 149
 150 static int mips_fpu_disabled;
 151
 152 static int __init fpu_disable(char *s)
 153 {
 154         cpu_set_nofpu_opts(&boot_cpu_data);
 155         mips_fpu_disabled = 1;
 156
 157         return 1;
 158 }
 159
 160 __setup("nofpu", fpu_disable);
 161
 162 int mips_dsp_disabled;
 163
 164 static int __init dsp_disable(char *s)
 165 {
 166         cpu_data[0].ases &= ~(MIPS_ASE_DSP | MIPS_ASE_DSP2P);
 167         mips_dsp_disabled = 1;
 168
 169         return 1;
 170 }
 171
 172 __setup("nodsp", dsp_disable);
 173
 174 static int mips_htw_disabled;
 175
 176 static int __init htw_disable(char *s)
 177 {
 178         mips_htw_disabled = 1;
 179         cpu_data[0].options &= ~MIPS_CPU_HTW;
 180         write_c0_pwctl(read_c0_pwctl() &
 181                        ~(1 << MIPS_PWCTL_PWEN_SHIFT));
 182
 183         return 1;
 184 }
 185
 186 __setup("nohtw", htw_disable);
 187
 188 static int mips_ftlb_disabled;
 189 static int mips_has_ftlb_configured;
 190
 191 static void set_ftlb_enable(struct cpuinfo_mips *c, int enable);
 192
 193 static int __init ftlb_disable(char *s)
 194 {
 195         unsigned int config4, mmuextdef;
 196
 197         /*
 198          * If the core hasn't done any FTLB configuration, there is nothing
 199          * for us to do here.
 200          */
 201         if (!mips_has_ftlb_configured)
 202                 return 1;
 203
 204         /* Disable it in the boot cpu */
 205         set_ftlb_enable(&cpu_data[0], 0);
 206
 207         back_to_back_c0_hazard();
 208
 209         config4 = read_c0_config4();
 210
 211         /* Check that FTLB has been disabled */
 212         mmuextdef = config4 & MIPS_CONF4_MMUEXTDEF;
 213         /* MMUSIZEEXT == VTLB ON, FTLB OFF */
 214         if (mmuextdef == MIPS_CONF4_MMUEXTDEF_FTLBSIZEEXT) {
 215                 /* This should never happen */
 216                 pr_warn("FTLB could not be disabled!\n");
 217                 return 1;
 218         }
 219
 220         mips_ftlb_disabled = 1;
 221         mips_has_ftlb_configured = 0;
 222
 223         /*
 224          * noftlb is mainly used for debug purposes so print
 225          * an informative message instead of using pr_debug()
 226          */
 227         pr_info("FTLB has been disabled\n");
 228
 229         /*
 230          * Some of these bits are duplicated in the decode_config4.
 231          * MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT is the only possible case
 232          * once FTLB has been disabled so undo what decode_config4 did.
 233          */
 234         cpu_data[0].tlbsize -= cpu_data[0].tlbsizeftlbways *
 235                                cpu_data[0].tlbsizeftlbsets;
 236         cpu_data[0].tlbsizeftlbsets = 0;
 237         cpu_data[0].tlbsizeftlbways = 0;
 238
 239         return 1;
 240 }
 241
 242 __setup("noftlb", ftlb_disable);
 243
 244
 245 static inline void check_errata(void)
 246 {
 247         struct cpuinfo_mips *c = &current_cpu_data;
 248
 249         switch (current_cpu_type()) {
 250         case CPU_34K:
 251                 /*
 252                  * Erratum "RPS May Cause Incorrect Instruction Execution"
 253                  * This code only handles VPE0, any SMP/RTOS code
 254                  * making use of VPE1 will be responsable for that VPE.
 255                  */
 256                 if ((c->processor_id & PRID_REV_MASK) <= PRID_REV_34K_V1_0_2)
 257                         write_c0_config7(read_c0_config7() | MIPS_CONF7_RPS);
 258                 break;
 259         default:
 260                 break;
 261         }
 262 }
 263
 264 void __init check_bugs32(void)
 265 {
 266         check_errata();
 267 }
 268
 269 /*
 270  * Probe whether cpu has config register by trying to play with
 271  * alternate cache bit and see whether it matters.
 272  * It's used by cpu_probe to distinguish between R3000A and R3081.
 273  */
 274 static inline int cpu_has_confreg(void)
 275 {
 276 #ifdef CONFIG_CPU_R3000
 277         extern unsigned long r3k_cache_size(unsigned long);
 278         unsigned long size1, size2;
 279         unsigned long cfg = read_c0_conf();
 280
 281         size1 = r3k_cache_size(ST0_ISC);
 282         write_c0_conf(cfg ^ R30XX_CONF_AC);
 283         size2 = r3k_cache_size(ST0_ISC);
 284         write_c0_conf(cfg);
 285         return size1 != size2;
 286 #else
 287         return 0;
 288 #endif
 289 }
 290
 291 static inline void set_elf_platform(int cpu, const char *plat)
 292 {
 293         if (cpu == 0)
 294                 __elf_platform = plat;
 295 }
 296
 297 static inline void cpu_probe_vmbits(struct cpuinfo_mips *c)
 298 {
 299 #ifdef __NEED_VMBITS_PROBE
 300         write_c0_entryhi(0x3fffffffffffe000ULL);
 301         back_to_back_c0_hazard();
 302         c->vmbits = fls64(read_c0_entryhi() & 0x3fffffffffffe000ULL);
 303 #endif
 304 }
 305
 306 static void set_isa(struct cpuinfo_mips *c, unsigned int isa)
 307 {
 308         switch (isa) {
 309         case MIPS_CPU_ISA_M64R2:
 310                 c->isa_level |= MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2;
 311         case MIPS_CPU_ISA_M64R1:
 312                 c->isa_level |= MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1;
 313         case MIPS_CPU_ISA_V:
 314                 c->isa_level |= MIPS_CPU_ISA_V;
 315         case MIPS_CPU_ISA_IV:
 316                 c->isa_level |= MIPS_CPU_ISA_IV;
 317         case MIPS_CPU_ISA_III:
 318                 c->isa_level |= MIPS_CPU_ISA_II | MIPS_CPU_ISA_III;
 319                 break;
 320
 321         /* R6 incompatible with everything else */
 322         case MIPS_CPU_ISA_M64R6:
 323                 c->isa_level |= MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6;
 324         case MIPS_CPU_ISA_M32R6:
 325                 c->isa_level |= MIPS_CPU_ISA_M32R6;
 326                 /* Break here so we don't add incompatible ISAs */
 327                 break;
 328         case MIPS_CPU_ISA_M32R2:
 329                 c->isa_level |= MIPS_CPU_ISA_M32R2;
 330         case MIPS_CPU_ISA_M32R1:
 331                 c->isa_level |= MIPS_CPU_ISA_M32R1;
 332         case MIPS_CPU_ISA_II:
 333                 c->isa_level |= MIPS_CPU_ISA_II;
 334                 break;
 335         }
 336 }
 337
 338 static char unknown_isa[] = KERN_ERR \
 339         "Unsupported ISA type, c0.config0: %d.";
 340
 341 static unsigned int calculate_ftlb_probability(struct cpuinfo_mips *c)
 342 {
 343
 344         unsigned int probability = c->tlbsize / c->tlbsizevtlb;
 345
 346         /*
 347          * 0 = All TLBWR instructions go to FTLB
 348          * 1 = 15:1: For every 16 TBLWR instructions, 15 go to the
 349          * FTLB and 1 goes to the VTLB.
 350          * 2 = 7:1: As above with 7:1 ratio.
 351          * 3 = 3:1: As above with 3:1 ratio.
 352          *
 353          * Use the linear midpoint as the probability threshold.
 354          */
 355         if (probability >= 12)
 356                 return 1;
 357         else if (probability >= 6)
 358                 return 2;
 359         else
 360                 /*
 361                  * So FTLB is less than 4 times bigger than VTLB.
 362                  * A 3:1 ratio can still be useful though.
 363                  */
 364                 return 3;
 365 }
 366
 367 static void set_ftlb_enable(struct cpuinfo_mips *c, int enable)
 368 {
 369         unsigned int config6;
 370
 371         /* It's implementation dependent how the FTLB can be enabled */
 372         switch (c->cputype) {
 373         case CPU_PROAPTIV:
 374         case CPU_P5600:
 375                 /* proAptiv & related cores use Config6 to enable the FTLB */
 376                 config6 = read_c0_config6();
 377                 /* Clear the old probability value */
 378                 config6 &= ~(3 << MIPS_CONF6_FTLBP_SHIFT);
 379                 if (enable)
 380                         /* Enable FTLB */
 381                         write_c0_config6(config6 |
 382                                          (calculate_ftlb_probability(c)
 383                                           << MIPS_CONF6_FTLBP_SHIFT)
 384                                          | MIPS_CONF6_FTLBEN);
 385                 else
 386                         /* Disable FTLB */
 387                         write_c0_config6(config6 &  ~MIPS_CONF6_FTLBEN);
 388                 back_to_back_c0_hazard();
 389                 break;
 390         }
 391 }
 392
 393 static inline unsigned int decode_config0(struct cpuinfo_mips *c)
 394 {
 395         unsigned int config0;
 396         int isa;
 397
 398         config0 = read_c0_config();
 399
 400         /*
 401          * Look for Standard TLB or Dual VTLB and FTLB
 402          */
 403         if ((((config0 & MIPS_CONF_MT) >> 7) == 1) ||
 404             (((config0 & MIPS_CONF_MT) >> 7) == 4))
 405                 c->options |= MIPS_CPU_TLB;
 406
 407         isa = (config0 & MIPS_CONF_AT) >> 13;
 408         switch (isa) {
 409         case 0:
 410                 switch ((config0 & MIPS_CONF_AR) >> 10) {
 411                 case 0:
 412                         set_isa(c, MIPS_CPU_ISA_M32R1);
 413                         break;
 414                 case 1:
 415                         set_isa(c, MIPS_CPU_ISA_M32R2);
 416                         break;
 417                 case 2:
 418                         set_isa(c, MIPS_CPU_ISA_M32R6);
 419                         break;
 420                 default:
 421                         goto unknown;
 422                 }
 423                 break;
 424         case 2:
 425                 switch ((config0 & MIPS_CONF_AR) >> 10) {
 426                 case 0:
 427                         set_isa(c, MIPS_CPU_ISA_M64R1);
 428                         break;
 429                 case 1:
 430                         set_isa(c, MIPS_CPU_ISA_M64R2);
 431                         break;
 432                 case 2:
 433                         set_isa(c, MIPS_CPU_ISA_M64R6);
 434                         break;
 435                 default:
 436                         goto unknown;
 437                 }
 438                 break;
 439         default:
 440                 goto unknown;
 441         }
 442
 443         return config0 & MIPS_CONF_M;
 444
 445 unknown:
 446         panic(unknown_isa, config0);
 447 }
 448
 449 static inline unsigned int decode_config1(struct cpuinfo_mips *c)
 450 {
 451         unsigned int config1;
 452
 453         config1 = read_c0_config1();
 454
 455         if (config1 & MIPS_CONF1_MD)
 456                 c->ases |= MIPS_ASE_MDMX;
 457         if (config1 & MIPS_CONF1_WR)
 458                 c->options |= MIPS_CPU_WATCH;
 459         if (config1 & MIPS_CONF1_CA)
 460                 c->ases |= MIPS_ASE_MIPS16;
 461         if (config1 & MIPS_CONF1_EP)
 462                 c->options |= MIPS_CPU_EJTAG;
 463         if (config1 & MIPS_CONF1_FP) {
 464                 c->options |= MIPS_CPU_FPU;
 465                 c->options |= MIPS_CPU_32FPR;
 466         }
 467         if (cpu_has_tlb) {
 468                 c->tlbsize = ((config1 & MIPS_CONF1_TLBS) >> 25) + 1;
 469                 c->tlbsizevtlb = c->tlbsize;
 470                 c->tlbsizeftlbsets = 0;
 471         }
 472
 473         return config1 & MIPS_CONF_M;
 474 }
 475
 476 static inline unsigned int decode_config2(struct cpuinfo_mips *c)
 477 {
 478         unsigned int config2;
 479
 480         config2 = read_c0_config2();
 481
 482         if (config2 & MIPS_CONF2_SL)
 483                 c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT;
 484
 485         return config2 & MIPS_CONF_M;
 486 }
 487
 488 static inline unsigned int decode_config3(struct cpuinfo_mips *c)
 489 {
 490         unsigned int config3;
 491
 492         config3 = read_c0_config3();
 493
 494         if (config3 & MIPS_CONF3_SM) {
 495                 c->ases |= MIPS_ASE_SMARTMIPS;
 496                 c->options |= MIPS_CPU_RIXI;
 497         }
 498         if (config3 & MIPS_CONF3_RXI)
 499                 c->options |= MIPS_CPU_RIXI;
 500         if (config3 & MIPS_CONF3_DSP)
 501                 c->ases |= MIPS_ASE_DSP;
 502         if (config3 & MIPS_CONF3_DSP2P)
 503                 c->ases |= MIPS_ASE_DSP2P;
 504         if (config3 & MIPS_CONF3_VINT)
 505                 c->options |= MIPS_CPU_VINT;
 506         if (config3 & MIPS_CONF3_VEIC)
 507                 c->options |= MIPS_CPU_VEIC;
 508         if (config3 & MIPS_CONF3_MT)
 509                 c->ases |= MIPS_ASE_MIPSMT;
 510         if (config3 & MIPS_CONF3_ULRI)
 511                 c->options |= MIPS_CPU_ULRI;
 512         if (config3 & MIPS_CONF3_ISA)
 513                 c->options |= MIPS_CPU_MICROMIPS;
 514         if (config3 & MIPS_CONF3_VZ)
 515                 c->ases |= MIPS_ASE_VZ;
 516         if (config3 & MIPS_CONF3_SC)
 517                 c->options |= MIPS_CPU_SEGMENTS;
 518         if (config3 & MIPS_CONF3_MSA)
 519                 c->ases |= MIPS_ASE_MSA;
 520         /* Only tested on 32-bit cores */
 521         if ((config3 & MIPS_CONF3_PW) && config_enabled(CONFIG_32BIT)) {
 522                 c->htw_seq = 0;
 523                 c->options |= MIPS_CPU_HTW;
 524         }
 525         if (config3 & MIPS_CONF3_CDMM)
 526                 c->options |= MIPS_CPU_CDMM;
 527
 528         return config3 & MIPS_CONF_M;
 529 }
 530
 531 static inline unsigned int decode_config4(struct cpuinfo_mips *c)
 532 {
 533         unsigned int config4;
 534         unsigned int newcf4;
 535         unsigned int mmuextdef;
 536         unsigned int ftlb_page = MIPS_CONF4_FTLBPAGESIZE;
 537
 538         config4 = read_c0_config4();
 539
 540         if (cpu_has_tlb) {
 541                 if (((config4 & MIPS_CONF4_IE) >> 29) == 2)
 542                         c->options |= MIPS_CPU_TLBINV;
 543                 mmuextdef = config4 & MIPS_CONF4_MMUEXTDEF;
 544                 switch (mmuextdef) {
 545                 case MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT:
 546                         c->tlbsize += (config4 & MIPS_CONF4_MMUSIZEEXT) * 0x40;
 547                         c->tlbsizevtlb = c->tlbsize;
 548                         break;
 549                 case MIPS_CONF4_MMUEXTDEF_VTLBSIZEEXT:
 550                         c->tlbsizevtlb +=
 551                                 ((config4 & MIPS_CONF4_VTLBSIZEEXT) >>
 552                                   MIPS_CONF4_VTLBSIZEEXT_SHIFT) * 0x40;
 553                         c->tlbsize = c->tlbsizevtlb;
 554                         ftlb_page = MIPS_CONF4_VFTLBPAGESIZE;
 555                         /* fall through */
 556                 case MIPS_CONF4_MMUEXTDEF_FTLBSIZEEXT:
 557                         if (mips_ftlb_disabled)
 558                                 break;
 559                         newcf4 = (config4 & ~ftlb_page) |
 560                                 (page_size_ftlb(mmuextdef) <<
 561                                  MIPS_CONF4_FTLBPAGESIZE_SHIFT);
 562                         write_c0_config4(newcf4);
 563                         back_to_back_c0_hazard();
 564                         config4 = read_c0_config4();
 565                         if (config4 != newcf4) {
 566                                 pr_err("PAGE_SIZE 0x%lx is not supported by FTLB (config4=0x%x)\n",
 567                                        PAGE_SIZE, config4);
 568                                 /* Switch FTLB off */
 569                                 set_ftlb_enable(c, 0);
 570                                 break;
 571                         }
 572                         c->tlbsizeftlbsets = 1 <<
 573                                 ((config4 & MIPS_CONF4_FTLBSETS) >>
 574                                  MIPS_CONF4_FTLBSETS_SHIFT);
 575                         c->tlbsizeftlbways = ((config4 & MIPS_CONF4_FTLBWAYS) >>
 576                                               MIPS_CONF4_FTLBWAYS_SHIFT) + 2;
 577                         c->tlbsize += c->tlbsizeftlbways * c->tlbsizeftlbsets;
 578                         mips_has_ftlb_configured = 1;
 579                         break;
 580                 }
 581         }
 582
 583         c->kscratch_mask = (config4 >> 16) & 0xff;
 584
 585         return config4 & MIPS_CONF_M;
 586 }
 587
 588 static inline unsigned int decode_config5(struct cpuinfo_mips *c)
 589 {
 590         unsigned int config5;
 591
 592         config5 = read_c0_config5();
 593         config5 &= ~(MIPS_CONF5_UFR | MIPS_CONF5_UFE);
 594         write_c0_config5(config5);
 595
 596         if (config5 & MIPS_CONF5_EVA)
 597                 c->options |= MIPS_CPU_EVA;
 598         if (config5 & MIPS_CONF5_MRP)
 599                 c->options |= MIPS_CPU_MAAR;
 600         if (config5 & MIPS_CONF5_LLB)
 601                 c->options |= MIPS_CPU_RW_LLB;
 602 #ifdef CONFIG_XPA
 603         if (config5 & MIPS_CONF5_MVH)
 604                 c->options |= MIPS_CPU_XPA;
 605 #endif
 606
 607         return config5 & MIPS_CONF_M;
 608 }
 609
 610 static void decode_configs(struct cpuinfo_mips *c)
 611 {
 612         int ok;
 613
 614         /* MIPS32 or MIPS64 compliant CPU.  */
 615         c->options = MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE | MIPS_CPU_COUNTER |
 616                      MIPS_CPU_DIVEC | MIPS_CPU_LLSC | MIPS_CPU_MCHECK;
 617
 618         c->scache.flags = MIPS_CACHE_NOT_PRESENT;
 619
 620         /* Enable FTLB if present and not disabled */
 621         set_ftlb_enable(c, !mips_ftlb_disabled);
 622
 623         ok = decode_config0(c);                 /* Read Config registers.  */
 624         BUG_ON(!ok);                            /* Arch spec violation!  */
 625         if (ok)
 626                 ok = decode_config1(c);
 627         if (ok)
 628                 ok = decode_config2(c);
 629         if (ok)
 630                 ok = decode_config3(c);
 631         if (ok)
 632                 ok = decode_config4(c);
 633         if (ok)
 634                 ok = decode_config5(c);
 635
 636         mips_probe_watch_registers(c);
 637
 638         if (cpu_has_rixi) {
 639                 /* Enable the RIXI exceptions */
 640                 set_c0_pagegrain(PG_IEC);
 641                 back_to_back_c0_hazard();
 642                 /* Verify the IEC bit is set */
 643                 if (read_c0_pagegrain() & PG_IEC)
 644                         c->options |= MIPS_CPU_RIXIEX;
 645         }
 646
 647 #ifndef CONFIG_MIPS_CPS
 648         if (cpu_has_mips_r2_r6) {
 649                 c->core = get_ebase_cpunum();
 650                 if (cpu_has_mipsmt)
 651                         c->core >>= fls(core_nvpes()) - 1;
 652         }
 653 #endif
 654 }
 655
 656 #define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE \
 657                 | MIPS_CPU_COUNTER)
 658
 659 static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
 660 {
 661         switch (c->processor_id & PRID_IMP_MASK) {
 662         case PRID_IMP_R2000:
 663                 c->cputype = CPU_R2000;
 664                 __cpu_name[cpu] = "R2000";
 665                 c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS;
 666                 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
 667                              MIPS_CPU_NOFPUEX;
 668                 if (__cpu_has_fpu())
 669                         c->options |= MIPS_CPU_FPU;
 670                 c->tlbsize = 64;
 671                 break;
 672         case PRID_IMP_R3000:
 673                 if ((c->processor_id & PRID_REV_MASK) == PRID_REV_R3000A) {
 674                         if (cpu_has_confreg()) {
 675                                 c->cputype = CPU_R3081E;
 676                                 __cpu_name[cpu] = "R3081";
 677                         } else {
 678                                 c->cputype = CPU_R3000A;
 679                                 __cpu_name[cpu] = "R3000A";
 680                         }
 681                 } else {
 682                         c->cputype = CPU_R3000;
 683                         __cpu_name[cpu] = "R3000";
 684                 }
 685                 c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS;
 686                 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
 687                              MIPS_CPU_NOFPUEX;
 688                 if (__cpu_has_fpu())
 689                         c->options |= MIPS_CPU_FPU;
 690                 c->tlbsize = 64;
 691                 break;
 692         case PRID_IMP_R4000:
 693                 if (read_c0_config() & CONF_SC) {
 694                         if ((c->processor_id & PRID_REV_MASK) >=
 695                             PRID_REV_R4400) {
 696                                 c->cputype = CPU_R4400PC;
 697                                 __cpu_name[cpu] = "R4400PC";
 698                         } else {
 699                                 c->cputype = CPU_R4000PC;
 700                                 __cpu_name[cpu] = "R4000PC";
 701                         }
 702                 } else {
 703                         int cca = read_c0_config() & CONF_CM_CMASK;
 704                         int mc;
 705
 706                         /*
 707                          * SC and MC versions can't be reliably told apart,
 708                          * but only the latter support coherent caching
 709                          * modes so assume the firmware has set the KSEG0
 710                          * coherency attribute reasonably (if uncached, we
 711                          * assume SC).
 712                          */
 713                         switch (cca) {
 714                         case CONF_CM_CACHABLE_CE:
 715                         case CONF_CM_CACHABLE_COW:
 716                         case CONF_CM_CACHABLE_CUW:
 717                                 mc = 1;
 718                                 break;
 719                         default:
 720                                 mc = 0;
 721                                 break;
 722                         }
 723                         if ((c->processor_id & PRID_REV_MASK) >=
 724                             PRID_REV_R4400) {
 725                                 c->cputype = mc ? CPU_R4400MC : CPU_R4400SC;
 726                                 __cpu_name[cpu] = mc ? "R4400MC" : "R4400SC";
 727                         } else {
 728                                 c->cputype = mc ? CPU_R4000MC : CPU_R4000SC;
 729                                 __cpu_name[cpu] = mc ? "R4000MC" : "R4000SC";
 730                         }
 731                 }
 732
 733                 set_isa(c, MIPS_CPU_ISA_III);
 734                 c->fpu_msk31 |= FPU_CSR_CONDX;
 735                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 736                              MIPS_CPU_WATCH | MIPS_CPU_VCE |
 737                              MIPS_CPU_LLSC;
 738                 c->tlbsize = 48;
 739                 break;
 740         case PRID_IMP_VR41XX:
 741                 set_isa(c, MIPS_CPU_ISA_III);
 742                 c->fpu_msk31 |= FPU_CSR_CONDX;
 743                 c->options = R4K_OPTS;
 744                 c->tlbsize = 32;
 745                 switch (c->processor_id & 0xf0) {
 746                 case PRID_REV_VR4111:
 747                         c->cputype = CPU_VR4111;
 748                         __cpu_name[cpu] = "NEC VR4111";
 749                         break;
 750                 case PRID_REV_VR4121:
 751                         c->cputype = CPU_VR4121;
 752                         __cpu_name[cpu] = "NEC VR4121";
 753                         break;
 754                 case PRID_REV_VR4122:
 755                         if ((c->processor_id & 0xf) < 0x3) {
 756                                 c->cputype = CPU_VR4122;
 757                                 __cpu_name[cpu] = "NEC VR4122";
 758                         } else {
 759                                 c->cputype = CPU_VR4181A;
 760                                 __cpu_name[cpu] = "NEC VR4181A";
 761                         }
 762                         break;
 763                 case PRID_REV_VR4130:
 764                         if ((c->processor_id & 0xf) < 0x4) {
 765                                 c->cputype = CPU_VR4131;
 766                                 __cpu_name[cpu] = "NEC VR4131";
 767                         } else {
 768                                 c->cputype = CPU_VR4133;
 769                                 c->options |= MIPS_CPU_LLSC;
 770                                 __cpu_name[cpu] = "NEC VR4133";
 771                         }
 772                         break;
 773                 default:
 774                         printk(KERN_INFO "Unexpected CPU of NEC VR4100 series\n");
 775                         c->cputype = CPU_VR41XX;
 776                         __cpu_name[cpu] = "NEC Vr41xx";
 777                         break;
 778                 }
 779                 break;
 780         case PRID_IMP_R4300:
 781                 c->cputype = CPU_R4300;
 782                 __cpu_name[cpu] = "R4300";
 783                 set_isa(c, MIPS_CPU_ISA_III);
 784                 c->fpu_msk31 |= FPU_CSR_CONDX;
 785                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 786                              MIPS_CPU_LLSC;
 787                 c->tlbsize = 32;
 788                 break;
 789         case PRID_IMP_R4600:
 790                 c->cputype = CPU_R4600;
 791                 __cpu_name[cpu] = "R4600";
 792                 set_isa(c, MIPS_CPU_ISA_III);
 793                 c->fpu_msk31 |= FPU_CSR_CONDX;
 794                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 795                              MIPS_CPU_LLSC;
 796                 c->tlbsize = 48;
 797                 break;
 798         #if 0
 799         case PRID_IMP_R4650:
 800                 /*
 801                  * This processor doesn't have an MMU, so it's not
 802                  * "real easy" to run Linux on it. It is left purely
 803                  * for documentation.  Commented out because it shares
 804                  * it's c0_prid id number with the TX3900.
 805                  */
 806                 c->cputype = CPU_R4650;
 807                 __cpu_name[cpu] = "R4650";
 808                 set_isa(c, MIPS_CPU_ISA_III);
 809                 c->fpu_msk31 |= FPU_CSR_CONDX;
 810                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_LLSC;
 811                 c->tlbsize = 48;
 812                 break;
 813         #endif
 814         case PRID_IMP_TX39:
 815                 c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS;
 816                 c->options = MIPS_CPU_TLB | MIPS_CPU_TX39_CACHE;
 817
 818                 if ((c->processor_id & 0xf0) == (PRID_REV_TX3927 & 0xf0)) {
 819                         c->cputype = CPU_TX3927;
 820                         __cpu_name[cpu] = "TX3927";
 821                         c->tlbsize = 64;
 822                 } else {
 823                         switch (c->processor_id & PRID_REV_MASK) {
 824                         case PRID_REV_TX3912:
 825                                 c->cputype = CPU_TX3912;
 826                                 __cpu_name[cpu] = "TX3912";
 827                                 c->tlbsize = 32;
 828                                 break;
 829                         case PRID_REV_TX3922:
 830                                 c->cputype = CPU_TX3922;
 831                                 __cpu_name[cpu] = "TX3922";
 832                                 c->tlbsize = 64;
 833                                 break;
 834                         }
 835                 }
 836                 break;
 837         case PRID_IMP_R4700:
 838                 c->cputype = CPU_R4700;
 839                 __cpu_name[cpu] = "R4700";
 840                 set_isa(c, MIPS_CPU_ISA_III);
 841                 c->fpu_msk31 |= FPU_CSR_CONDX;
 842                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 843                              MIPS_CPU_LLSC;
 844                 c->tlbsize = 48;
 845                 break;
 846         case PRID_IMP_TX49:
 847                 c->cputype = CPU_TX49XX;
 848                 __cpu_name[cpu] = "R49XX";
 849                 set_isa(c, MIPS_CPU_ISA_III);
 850                 c->fpu_msk31 |= FPU_CSR_CONDX;
 851                 c->options = R4K_OPTS | MIPS_CPU_LLSC;
 852                 if (!(c->processor_id & 0x08))
 853                         c->options |= MIPS_CPU_FPU | MIPS_CPU_32FPR;
 854                 c->tlbsize = 48;
 855                 break;
 856         case PRID_IMP_R5000:
 857                 c->cputype = CPU_R5000;
 858                 __cpu_name[cpu] = "R5000";
 859                 set_isa(c, MIPS_CPU_ISA_IV);
 860                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 861                              MIPS_CPU_LLSC;
 862                 c->tlbsize = 48;
 863                 break;
 864         case PRID_IMP_R5432:
 865                 c->cputype = CPU_R5432;
 866                 __cpu_name[cpu] = "R5432";
 867                 set_isa(c, MIPS_CPU_ISA_IV);
 868                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 869                              MIPS_CPU_WATCH | MIPS_CPU_LLSC;
 870                 c->tlbsize = 48;
 871                 break;
 872         case PRID_IMP_R5500:
 873                 c->cputype = CPU_R5500;
 874                 __cpu_name[cpu] = "R5500";
 875                 set_isa(c, MIPS_CPU_ISA_IV);
 876                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 877                              MIPS_CPU_WATCH | MIPS_CPU_LLSC;
 878                 c->tlbsize = 48;
 879                 break;
 880         case PRID_IMP_NEVADA:
 881                 c->cputype = CPU_NEVADA;
 882                 __cpu_name[cpu] = "Nevada";
 883                 set_isa(c, MIPS_CPU_ISA_IV);
 884                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 885                              MIPS_CPU_DIVEC | MIPS_CPU_LLSC;
 886                 c->tlbsize = 48;
 887                 break;
 888         case PRID_IMP_R6000:
 889                 c->cputype = CPU_R6000;
 890                 __cpu_name[cpu] = "R6000";
 891                 set_isa(c, MIPS_CPU_ISA_II);
 892                 c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS;
 893                 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
 894                              MIPS_CPU_LLSC;
 895                 c->tlbsize = 32;
 896                 break;
 897         case PRID_IMP_R6000A:
 898                 c->cputype = CPU_R6000A;
 899                 __cpu_name[cpu] = "R6000A";
 900                 set_isa(c, MIPS_CPU_ISA_II);
 901                 c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS;
 902                 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
 903                              MIPS_CPU_LLSC;
 904                 c->tlbsize = 32;
 905                 break;
 906         case PRID_IMP_RM7000:
 907                 c->cputype = CPU_RM7000;
 908                 __cpu_name[cpu] = "RM7000";
 909                 set_isa(c, MIPS_CPU_ISA_IV);
 910                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 911                              MIPS_CPU_LLSC;
 912                 /*
 913                  * Undocumented RM7000:  Bit 29 in the info register of
 914                  * the RM7000 v2.0 indicates if the TLB has 48 or 64
 915                  * entries.
 916                  *
 917                  * 29      1 =>    64 entry JTLB
 918                  *         0 =>    48 entry JTLB
 919                  */
 920                 c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48;
 921                 break;
 922         case PRID_IMP_R8000:
 923                 c->cputype = CPU_R8000;
 924                 __cpu_name[cpu] = "RM8000";
 925                 set_isa(c, MIPS_CPU_ISA_IV);
 926                 c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
 927                              MIPS_CPU_FPU | MIPS_CPU_32FPR |
 928                              MIPS_CPU_LLSC;
 929                 c->tlbsize = 384;      /* has weird TLB: 3-way x 128 */
 930                 break;
 931         case PRID_IMP_R10000:
 932                 c->cputype = CPU_R10000;
 933                 __cpu_name[cpu] = "R10000";
 934                 set_isa(c, MIPS_CPU_ISA_IV);
 935                 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
 936                              MIPS_CPU_FPU | MIPS_CPU_32FPR |
 937                              MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
 938                              MIPS_CPU_LLSC;
 939                 c->tlbsize = 64;
 940                 break;
 941         case PRID_IMP_R12000:
 942                 c->cputype = CPU_R12000;
 943                 __cpu_name[cpu] = "R12000";
 944                 set_isa(c, MIPS_CPU_ISA_IV);
 945                 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
 946                              MIPS_CPU_FPU | MIPS_CPU_32FPR |
 947                              MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
 948                              MIPS_CPU_LLSC;
 949                 c->tlbsize = 64;
 950                 break;
 951         case PRID_IMP_R14000:
 952                 if (((c->processor_id >> 4) & 0x0f) > 2) {
 953                         c->cputype = CPU_R16000;
 954                         __cpu_name[cpu] = "R16000";
 955                 } else {
 956                         c->cputype = CPU_R14000;
 957                         __cpu_name[cpu] = "R14000";
 958                 }
 959                 set_isa(c, MIPS_CPU_ISA_IV);
 960                 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
 961                              MIPS_CPU_FPU | MIPS_CPU_32FPR |
 962                              MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
 963                              MIPS_CPU_LLSC;
 964                 c->tlbsize = 64;
 965                 break;
 966         case PRID_IMP_LOONGSON_64:  /* Loongson-2/3 */
 967                 switch (c->processor_id & PRID_REV_MASK) {
 968                 case PRID_REV_LOONGSON2E:
 969                         c->cputype = CPU_LOONGSON2;
 970                         __cpu_name[cpu] = "ICT Loongson-2";
 971                         set_elf_platform(cpu, "loongson2e");
 972                         set_isa(c, MIPS_CPU_ISA_III);
 973                         c->fpu_msk31 |= FPU_CSR_CONDX;
 974                         break;
 975                 case PRID_REV_LOONGSON2F:
 976                         c->cputype = CPU_LOONGSON2;
 977                         __cpu_name[cpu] = "ICT Loongson-2";
 978                         set_elf_platform(cpu, "loongson2f");
 979                         set_isa(c, MIPS_CPU_ISA_III);
 980                         c->fpu_msk31 |= FPU_CSR_CONDX;
 981                         break;
 982                 case PRID_REV_LOONGSON3A:
 983                         c->cputype = CPU_LOONGSON3;
 984                         __cpu_name[cpu] = "ICT Loongson-3";
 985                         set_elf_platform(cpu, "loongson3a");
 986                         set_isa(c, MIPS_CPU_ISA_M64R1);
 987                         break;
 988                 case PRID_REV_LOONGSON3B_R1:
 989                 case PRID_REV_LOONGSON3B_R2:
 990                         c->cputype = CPU_LOONGSON3;
 991                         __cpu_name[cpu] = "ICT Loongson-3";
 992                         set_elf_platform(cpu, "loongson3b");
 993                         set_isa(c, MIPS_CPU_ISA_M64R1);
 994                         break;
 995                 }
 996
 997                 c->options = R4K_OPTS |
 998                              MIPS_CPU_FPU | MIPS_CPU_LLSC |
 999                              MIPS_CPU_32FPR;
1000                 c->tlbsize = 64;
1001                 c->writecombine = _CACHE_UNCACHED_ACCELERATED;
1002                 break;
1003         case PRID_IMP_LOONGSON_32:  /* Loongson-1 */
1004                 decode_configs(c);
1005
1006                 c->cputype = CPU_LOONGSON1;
1007
1008                 switch (c->processor_id & PRID_REV_MASK) {
1009                 case PRID_REV_LOONGSON1B:
1010                         __cpu_name[cpu] = "Loongson 1B";
1011                         break;
1012                 }
1013
1014                 break;
1015         }
1016 }
1017
1018 static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu)
1019 {
1020         c->writecombine = _CACHE_UNCACHED_ACCELERATED;
1021         switch (c->processor_id & PRID_IMP_MASK) {
1022         case PRID_IMP_QEMU_GENERIC:
1023                 c->writecombine = _CACHE_UNCACHED;
1024                 c->cputype = CPU_QEMU_GENERIC;
1025                 __cpu_name[cpu] = "MIPS GENERIC QEMU";
1026                 break;
1027         case PRID_IMP_4KC:
1028                 c->cputype = CPU_4KC;
1029                 c->writecombine = _CACHE_UNCACHED;
1030                 __cpu_name[cpu] = "MIPS 4Kc";
1031                 break;
1032         case PRID_IMP_4KEC:
1033         case PRID_IMP_4KECR2:
1034                 c->cputype = CPU_4KEC;
1035                 c->writecombine = _CACHE_UNCACHED;
1036                 __cpu_name[cpu] = "MIPS 4KEc";
1037                 break;
1038         case PRID_IMP_4KSC:
1039         case PRID_IMP_4KSD:
1040                 c->cputype = CPU_4KSC;
1041                 c->writecombine = _CACHE_UNCACHED;
1042                 __cpu_name[cpu] = "MIPS 4KSc";
1043                 break;
1044         case PRID_IMP_5KC:
1045                 c->cputype = CPU_5KC;
1046                 c->writecombine = _CACHE_UNCACHED;
1047                 __cpu_name[cpu] = "MIPS 5Kc";
1048                 break;
1049         case PRID_IMP_5KE:
1050                 c->cputype = CPU_5KE;
1051                 c->writecombine = _CACHE_UNCACHED;
1052                 __cpu_name[cpu] = "MIPS 5KE";
1053                 break;
1054         case PRID_IMP_20KC:
1055                 c->cputype = CPU_20KC;
1056                 c->writecombine = _CACHE_UNCACHED;
1057                 __cpu_name[cpu] = "MIPS 20Kc";
1058                 break;
1059         case PRID_IMP_24K:
1060                 c->cputype = CPU_24K;
1061                 c->writecombine = _CACHE_UNCACHED;
1062                 __cpu_name[cpu] = "MIPS 24Kc";
1063                 break;
1064         case PRID_IMP_24KE:
1065                 c->cputype = CPU_24K;
1066                 c->writecombine = _CACHE_UNCACHED;
1067                 __cpu_name[cpu] = "MIPS 24KEc";
1068                 break;
1069         case PRID_IMP_25KF:
1070                 c->cputype = CPU_25KF;
1071                 c->writecombine = _CACHE_UNCACHED;
1072                 __cpu_name[cpu] = "MIPS 25Kc";
1073                 break;
1074         case PRID_IMP_34K:
1075                 c->cputype = CPU_34K;
1076                 c->writecombine = _CACHE_UNCACHED;
1077                 __cpu_name[cpu] = "MIPS 34Kc";
1078                 break;
1079         case PRID_IMP_74K:
1080                 c->cputype = CPU_74K;
1081                 c->writecombine = _CACHE_UNCACHED;
1082                 __cpu_name[cpu] = "MIPS 74Kc";
1083                 break;
1084         case PRID_IMP_M14KC:
1085                 c->cputype = CPU_M14KC;
1086                 c->writecombine = _CACHE_UNCACHED;
1087                 __cpu_name[cpu] = "MIPS M14Kc";
1088                 break;
1089         case PRID_IMP_M14KEC:
1090                 c->cputype = CPU_M14KEC;
1091                 c->writecombine = _CACHE_UNCACHED;
1092                 __cpu_name[cpu] = "MIPS M14KEc";
1093                 break;
1094         case PRID_IMP_1004K:
1095                 c->cputype = CPU_1004K;
1096                 c->writecombine = _CACHE_UNCACHED;
1097                 __cpu_name[cpu] = "MIPS 1004Kc";
1098                 break;
1099         case PRID_IMP_1074K:
1100                 c->cputype = CPU_1074K;
1101                 c->writecombine = _CACHE_UNCACHED;
1102                 __cpu_name[cpu] = "MIPS 1074Kc";
1103                 break;
1104         case PRID_IMP_INTERAPTIV_UP:
1105                 c->cputype = CPU_INTERAPTIV;
1106                 __cpu_name[cpu] = "MIPS interAptiv";
1107                 break;
1108         case PRID_IMP_INTERAPTIV_MP:
1109                 c->cputype = CPU_INTERAPTIV;
1110                 __cpu_name[cpu] = "MIPS interAptiv (multi)";
1111                 break;
1112         case PRID_IMP_PROAPTIV_UP:
1113                 c->cputype = CPU_PROAPTIV;
1114                 __cpu_name[cpu] = "MIPS proAptiv";
1115                 break;
1116         case PRID_IMP_PROAPTIV_MP:
1117                 c->cputype = CPU_PROAPTIV;
1118                 __cpu_name[cpu] = "MIPS proAptiv (multi)";
1119                 break;
1120         case PRID_IMP_P5600:
1121                 c->cputype = CPU_P5600;
1122                 __cpu_name[cpu] = "MIPS P5600";
1123                 break;
1124         case PRID_IMP_M5150:
1125                 c->cputype = CPU_M5150;
1126                 __cpu_name[cpu] = "MIPS M5150";
1127                 break;
1128         }
1129
1130         decode_configs(c);
1131
1132         spram_config();
1133 }
1134
1135 static inline void cpu_probe_alchemy(struct cpuinfo_mips *c, unsigned int cpu)
1136 {
1137         decode_configs(c);
1138         switch (c->processor_id & PRID_IMP_MASK) {
1139         case PRID_IMP_AU1_REV1:
1140         case PRID_IMP_AU1_REV2:
1141                 c->cputype = CPU_ALCHEMY;
1142                 switch ((c->processor_id >> 24) & 0xff) {
1143                 case 0:
1144                         __cpu_name[cpu] = "Au1000";
1145                         break;
1146                 case 1:
1147                         __cpu_name[cpu] = "Au1500";
1148                         break;
1149                 case 2:
1150                         __cpu_name[cpu] = "Au1100";
1151                         break;
1152                 case 3:
1153                         __cpu_name[cpu] = "Au1550";
1154                         break;
1155                 case 4:
1156                         __cpu_name[cpu] = "Au1200";
1157                         if ((c->processor_id & PRID_REV_MASK) == 2)
1158                                 __cpu_name[cpu] = "Au1250";
1159                         break;
1160                 case 5:
1161                         __cpu_name[cpu] = "Au1210";
1162                         break;
1163                 default:
1164                         __cpu_name[cpu] = "Au1xxx";
1165                         break;
1166                 }
1167                 break;
1168         }
1169 }
1170
1171 static inline void cpu_probe_sibyte(struct cpuinfo_mips *c, unsigned int cpu)
1172 {
1173         decode_configs(c);
1174
1175         c->writecombine = _CACHE_UNCACHED_ACCELERATED;
1176         switch (c->processor_id & PRID_IMP_MASK) {
1177         case PRID_IMP_SB1:
1178                 c->cputype = CPU_SB1;
1179                 __cpu_name[cpu] = "SiByte SB1";
1180                 /* FPU in pass1 is known to have issues. */
1181                 if ((c->processor_id & PRID_REV_MASK) < 0x02)
1182                         c->options &= ~(MIPS_CPU_FPU | MIPS_CPU_32FPR);
1183                 break;
1184         case PRID_IMP_SB1A:
1185                 c->cputype = CPU_SB1A;
1186                 __cpu_name[cpu] = "SiByte SB1A";
1187                 break;
1188         }
1189 }
1190
1191 static inline void cpu_probe_sandcraft(struct cpuinfo_mips *c, unsigned int cpu)
1192 {
1193         decode_configs(c);
1194         switch (c->processor_id & PRID_IMP_MASK) {
1195         case PRID_IMP_SR71000:
1196                 c->cputype = CPU_SR71000;
1197                 __cpu_name[cpu] = "Sandcraft SR71000";
1198                 c->scache.ways = 8;
1199                 c->tlbsize = 64;
1200                 break;
1201         }
1202 }
1203
1204 static inline void cpu_probe_nxp(struct cpuinfo_mips *c, unsigned int cpu)
1205 {
1206         decode_configs(c);
1207         switch (c->processor_id & PRID_IMP_MASK) {
1208         case PRID_IMP_PR4450:
1209                 c->cputype = CPU_PR4450;
1210                 __cpu_name[cpu] = "Philips PR4450";
1211                 set_isa(c, MIPS_CPU_ISA_M32R1);
1212                 break;
1213         }
1214 }
1215
1216 static inline void cpu_probe_broadcom(struct cpuinfo_mips *c, unsigned int cpu)
1217 {
1218         decode_configs(c);
1219         switch (c->processor_id & PRID_IMP_MASK) {
1220         case PRID_IMP_BMIPS32_REV4:
1221         case PRID_IMP_BMIPS32_REV8:
1222                 c->cputype = CPU_BMIPS32;
1223                 __cpu_name[cpu] = "Broadcom BMIPS32";
1224                 set_elf_platform(cpu, "bmips32");
1225                 break;
1226         case PRID_IMP_BMIPS3300:
1227         case PRID_IMP_BMIPS3300_ALT:
1228         case PRID_IMP_BMIPS3300_BUG:
1229                 c->cputype = CPU_BMIPS3300;
1230                 __cpu_name[cpu] = "Broadcom BMIPS3300";
1231                 set_elf_platform(cpu, "bmips3300");
1232                 break;
1233         case PRID_IMP_BMIPS43XX: {
1234                 int rev = c->processor_id & PRID_REV_MASK;
1235
1236                 if (rev >= PRID_REV_BMIPS4380_LO &&
1237                                 rev <= PRID_REV_BMIPS4380_HI) {
1238                         c->cputype = CPU_BMIPS4380;
1239                         __cpu_name[cpu] = "Broadcom BMIPS4380";
1240                         set_elf_platform(cpu, "bmips4380");
1241                 } else {
1242                         c->cputype = CPU_BMIPS4350;
1243                         __cpu_name[cpu] = "Broadcom BMIPS4350";
1244                         set_elf_platform(cpu, "bmips4350");
1245                 }
1246                 break;
1247         }
1248         case PRID_IMP_BMIPS5000:
1249         case PRID_IMP_BMIPS5200:
1250                 c->cputype = CPU_BMIPS5000;
1251                 __cpu_name[cpu] = "Broadcom BMIPS5000";
1252                 set_elf_platform(cpu, "bmips5000");
1253                 c->options |= MIPS_CPU_ULRI;
1254                 break;
1255         }
1256 }
1257
1258 static inline void cpu_probe_cavium(struct cpuinfo_mips *c, unsigned int cpu)
1259 {
1260         decode_configs(c);
1261         switch (c->processor_id & PRID_IMP_MASK) {
1262         case PRID_IMP_CAVIUM_CN38XX:
1263         case PRID_IMP_CAVIUM_CN31XX:
1264         case PRID_IMP_CAVIUM_CN30XX:
1265                 c->cputype = CPU_CAVIUM_OCTEON;
1266                 __cpu_name[cpu] = "Cavium Octeon";
1267                 goto platform;
1268         case PRID_IMP_CAVIUM_CN58XX:
1269         case PRID_IMP_CAVIUM_CN56XX:
1270         case PRID_IMP_CAVIUM_CN50XX:
1271         case PRID_IMP_CAVIUM_CN52XX:
1272                 c->cputype = CPU_CAVIUM_OCTEON_PLUS;
1273                 __cpu_name[cpu] = "Cavium Octeon+";
1274 platform:
1275                 set_elf_platform(cpu, "octeon");
1276                 break;
1277         case PRID_IMP_CAVIUM_CN61XX:
1278         case PRID_IMP_CAVIUM_CN63XX:
1279         case PRID_IMP_CAVIUM_CN66XX:
1280         case PRID_IMP_CAVIUM_CN68XX:
1281         case PRID_IMP_CAVIUM_CNF71XX:
1282                 c->cputype = CPU_CAVIUM_OCTEON2;
1283                 __cpu_name[cpu] = "Cavium Octeon II";
1284                 set_elf_platform(cpu, "octeon2");
1285                 break;
1286         case PRID_IMP_CAVIUM_CN70XX:
1287         case PRID_IMP_CAVIUM_CN78XX:
1288                 c->cputype = CPU_CAVIUM_OCTEON3;
1289                 __cpu_name[cpu] = "Cavium Octeon III";
1290                 set_elf_platform(cpu, "octeon3");
1291                 break;
1292         default:
1293                 printk(KERN_INFO "Unknown Octeon chip!\n");
1294                 c->cputype = CPU_UNKNOWN;
1295                 break;
1296         }
1297 }
1298
1299 static inline void cpu_probe_ingenic(struct cpuinfo_mips *c, unsigned int cpu)
1300 {
1301         decode_configs(c);
1302         /* JZRISC does not implement the CP0 counter. */
1303         c->options &= ~MIPS_CPU_COUNTER;
1304         BUG_ON(!__builtin_constant_p(cpu_has_counter) || cpu_has_counter);
1305         switch (c->processor_id & PRID_IMP_MASK) {
1306         case PRID_IMP_JZRISC:
1307                 c->cputype = CPU_JZRISC;
1308                 c->writecombine = _CACHE_UNCACHED_ACCELERATED;
1309                 __cpu_name[cpu] = "Ingenic JZRISC";
1310                 break;
1311         default:
1312                 panic("Unknown Ingenic Processor ID!");
1313                 break;
1314         }
1315 }
1316
1317 static inline void cpu_probe_netlogic(struct cpuinfo_mips *c, int cpu)
1318 {
1319         decode_configs(c);
1320
1321         if ((c->processor_id & PRID_IMP_MASK) == PRID_IMP_NETLOGIC_AU13XX) {
1322                 c->cputype = CPU_ALCHEMY;
1323                 __cpu_name[cpu] = "Au1300";
1324                 /* following stuff is not for Alchemy */
1325                 return;
1326         }
1327
1328         c->options = (MIPS_CPU_TLB       |
1329                         MIPS_CPU_4KEX    |
1330                         MIPS_CPU_COUNTER |
1331                         MIPS_CPU_DIVEC   |
1332                         MIPS_CPU_WATCH   |
1333                         MIPS_CPU_EJTAG   |
1334                         MIPS_CPU_LLSC);
1335
1336         switch (c->processor_id & PRID_IMP_MASK) {
1337         case PRID_IMP_NETLOGIC_XLP2XX:
1338         case PRID_IMP_NETLOGIC_XLP9XX:
1339         case PRID_IMP_NETLOGIC_XLP5XX:
1340                 c->cputype = CPU_XLP;
1341                 __cpu_name[cpu] = "Broadcom XLPII";
1342                 break;
1343
1344         case PRID_IMP_NETLOGIC_XLP8XX:
1345         case PRID_IMP_NETLOGIC_XLP3XX:
1346                 c->cputype = CPU_XLP;
1347                 __cpu_name[cpu] = "Netlogic XLP";
1348                 break;
1349
1350         case PRID_IMP_NETLOGIC_XLR732:
1351         case PRID_IMP_NETLOGIC_XLR716:
1352         case PRID_IMP_NETLOGIC_XLR532:
1353         case PRID_IMP_NETLOGIC_XLR308:
1354         case PRID_IMP_NETLOGIC_XLR532C:
1355         case PRID_IMP_NETLOGIC_XLR516C:
1356         case PRID_IMP_NETLOGIC_XLR508C:
1357         case PRID_IMP_NETLOGIC_XLR308C:
1358                 c->cputype = CPU_XLR;
1359                 __cpu_name[cpu] = "Netlogic XLR";
1360                 break;
1361
1362         case PRID_IMP_NETLOGIC_XLS608:
1363         case PRID_IMP_NETLOGIC_XLS408:
1364         case PRID_IMP_NETLOGIC_XLS404:
1365         case PRID_IMP_NETLOGIC_XLS208:
1366         case PRID_IMP_NETLOGIC_XLS204:
1367         case PRID_IMP_NETLOGIC_XLS108:
1368         case PRID_IMP_NETLOGIC_XLS104:
1369         case PRID_IMP_NETLOGIC_XLS616B:
1370         case PRID_IMP_NETLOGIC_XLS608B:
1371         case PRID_IMP_NETLOGIC_XLS416B:
1372         case PRID_IMP_NETLOGIC_XLS412B:
1373         case PRID_IMP_NETLOGIC_XLS408B:
1374         case PRID_IMP_NETLOGIC_XLS404B:
1375                 c->cputype = CPU_XLR;
1376                 __cpu_name[cpu] = "Netlogic XLS";
1377                 break;
1378
1379         default:
1380                 pr_info("Unknown Netlogic chip id [%02x]!\n",
1381                        c->processor_id);
1382                 c->cputype = CPU_XLR;
1383                 break;
1384         }
1385
1386         if (c->cputype == CPU_XLP) {
1387                 set_isa(c, MIPS_CPU_ISA_M64R2);
1388                 c->options |= (MIPS_CPU_FPU | MIPS_CPU_ULRI | MIPS_CPU_MCHECK);
1389                 /* This will be updated again after all threads are woken up */
1390                 c->tlbsize = ((read_c0_config6() >> 16) & 0xffff) + 1;
1391         } else {
1392                 set_isa(c, MIPS_CPU_ISA_M64R1);
1393                 c->tlbsize = ((read_c0_config1() >> 25) & 0x3f) + 1;
1394         }
1395         c->kscratch_mask = 0xf;
1396 }
1397
1398 #ifdef CONFIG_64BIT
1399 /* For use by uaccess.h */
1400 u64 __ua_limit;
1401 EXPORT_SYMBOL(__ua_limit);
1402 #endif
1403
1404 const char *__cpu_name[NR_CPUS];
1405 const char *__elf_platform;
1406
1407 void cpu_probe(void)
1408 {
1409         struct cpuinfo_mips *c = &current_cpu_data;
1410         unsigned int cpu = smp_processor_id();
1411
1412         c->processor_id = PRID_IMP_UNKNOWN;
1413         c->fpu_id       = FPIR_IMP_NONE;
1414         c->cputype      = CPU_UNKNOWN;
1415         c->writecombine = _CACHE_UNCACHED;
1416
1417         c->fpu_csr31    = FPU_CSR_RN;
1418         c->fpu_msk31    = FPU_CSR_RSVD | FPU_CSR_ABS2008 | FPU_CSR_NAN2008;
1419
1420         c->processor_id = read_c0_prid();
1421         switch (c->processor_id & PRID_COMP_MASK) {
1422         case PRID_COMP_LEGACY:
1423                 cpu_probe_legacy(c, cpu);
1424                 break;
1425         case PRID_COMP_MIPS:
1426                 cpu_probe_mips(c, cpu);
1427                 break;
1428         case PRID_COMP_ALCHEMY:
1429                 cpu_probe_alchemy(c, cpu);
1430                 break;
1431         case PRID_COMP_SIBYTE:
1432                 cpu_probe_sibyte(c, cpu);
1433                 break;
1434         case PRID_COMP_BROADCOM:
1435                 cpu_probe_broadcom(c, cpu);
1436                 break;
1437         case PRID_COMP_SANDCRAFT:
1438                 cpu_probe_sandcraft(c, cpu);
1439                 break;
1440         case PRID_COMP_NXP:
1441                 cpu_probe_nxp(c, cpu);
1442                 break;
1443         case PRID_COMP_CAVIUM:
1444                 cpu_probe_cavium(c, cpu);
1445                 break;
1446         case PRID_COMP_INGENIC:
1447                 cpu_probe_ingenic(c, cpu);
1448                 break;
1449         case PRID_COMP_NETLOGIC:
1450                 cpu_probe_netlogic(c, cpu);
1451                 break;
1452         }
1453
1454         BUG_ON(!__cpu_name[cpu]);
1455         BUG_ON(c->cputype == CPU_UNKNOWN);
1456
1457         /*
1458          * Platform code can force the cpu type to optimize code
1459          * generation. In that case be sure the cpu type is correctly
1460          * manually setup otherwise it could trigger some nasty bugs.
1461          */
1462         BUG_ON(current_cpu_type() != c->cputype);
1463
1464         if (mips_fpu_disabled)
1465                 c->options &= ~MIPS_CPU_FPU;
1466
1467         if (mips_dsp_disabled)
1468                 c->ases &= ~(MIPS_ASE_DSP | MIPS_ASE_DSP2P);
1469
1470         if (mips_htw_disabled) {
1471                 c->options &= ~MIPS_CPU_HTW;
1472                 write_c0_pwctl(read_c0_pwctl() &
1473                                ~(1 << MIPS_PWCTL_PWEN_SHIFT));
1474         }
1475
1476         if (c->options & MIPS_CPU_FPU)
1477                 cpu_set_fpu_opts(c);
1478         else
1479                 cpu_set_nofpu_opts(c);
1480
1481         if (cpu_has_mips_r2_r6) {
1482                 c->srsets = ((read_c0_srsctl() >> 26) & 0x0f) + 1;
1483                 /* R2 has Performance Counter Interrupt indicator */
1484                 c->options |= MIPS_CPU_PCI;
1485         }
1486         else
1487                 c->srsets = 1;
1488
1489         if (cpu_has_msa) {
1490                 c->msa_id = cpu_get_msa_id();
1491                 WARN(c->msa_id & MSA_IR_WRPF,
1492                      "Vector register partitioning unimplemented!");
1493         }
1494
1495         cpu_probe_vmbits(c);
1496
1497 #ifdef CONFIG_64BIT
1498         if (cpu == 0)
1499                 __ua_limit = ~((1ull << cpu_vmbits) - 1);
1500 #endif
1501 }
1502
1503 void cpu_report(void)
1504 {
1505         struct cpuinfo_mips *c = &current_cpu_data;
1506
1507         pr_info("CPU%d revision is: %08x (%s)\n",
1508                 smp_processor_id(), c->processor_id, cpu_name_string());
1509         if (c->options & MIPS_CPU_FPU)
1510                 printk(KERN_INFO "FPU revision is: %08x\n", c->fpu_id);
1511         if (cpu_has_msa)
1512                 pr_info("MSA revision is: %08x\n", c->msa_id);
1513 }