kernel/arch/mips/include/asm/octeon/cvmx-sriox-defs.h

   1 /***********************license start***************
   2  * Author: Cavium Networks
   3  *
   4  * Contact: support@caviumnetworks.com
   5  * This file is part of the OCTEON SDK
   6  *
   7  * Copyright (c) 2003-2012 Cavium Networks
   8  *
   9  * This file is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License, Version 2, as
  11  * published by the Free Software Foundation.
  12  *
  13  * This file is distributed in the hope that it will be useful, but
  14  * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
  15  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
  16  * NONINFRINGEMENT.  See the GNU General Public License for more
  17  * details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this file; if not, write to the Free Software
  21  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  22  * or visit http://www.gnu.org/licenses/.
  23  *
  24  * This file may also be available under a different license from Cavium.
  25  * Contact Cavium Networks for more information
  26  ***********************license end**************************************/
  27
  28 #ifndef __CVMX_SRIOX_DEFS_H__
  29 #define __CVMX_SRIOX_DEFS_H__
  30
  31 #define CVMX_SRIOX_ACC_CTRL(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000148ull) + ((block_id) & 3) * 0x1000000ull)
  32 #define CVMX_SRIOX_ASMBLY_ID(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000200ull) + ((block_id) & 3) * 0x1000000ull)
  33 #define CVMX_SRIOX_ASMBLY_INFO(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000208ull) + ((block_id) & 3) * 0x1000000ull)
  34 #define CVMX_SRIOX_BELL_RESP_CTRL(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000310ull) + ((block_id) & 3) * 0x1000000ull)
  35 #define CVMX_SRIOX_BIST_STATUS(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000108ull) + ((block_id) & 3) * 0x1000000ull)
  36 #define CVMX_SRIOX_IMSG_CTRL(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000508ull) + ((block_id) & 3) * 0x1000000ull)
  37 #define CVMX_SRIOX_IMSG_INST_HDRX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C8000510ull) + (((offset) & 1) + ((block_id) & 3) * 0x200000ull) * 8)
  38 #define CVMX_SRIOX_IMSG_QOS_GRPX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C8000600ull) + (((offset) & 31) + ((block_id) & 3) * 0x200000ull) * 8)
  39 #define CVMX_SRIOX_IMSG_STATUSX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C8000700ull) + (((offset) & 31) + ((block_id) & 3) * 0x200000ull) * 8)
  40 #define CVMX_SRIOX_IMSG_VPORT_THR(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000500ull) + ((block_id) & 3) * 0x1000000ull)
  41 #define CVMX_SRIOX_IMSG_VPORT_THR2(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000528ull) + ((block_id) & 3) * 0x1000000ull)
  42 #define CVMX_SRIOX_INT2_ENABLE(block_id) (CVMX_ADD_IO_SEG(0x00011800C80003E0ull) + ((block_id) & 3) * 0x1000000ull)
  43 #define CVMX_SRIOX_INT2_REG(block_id) (CVMX_ADD_IO_SEG(0x00011800C80003E8ull) + ((block_id) & 3) * 0x1000000ull)
  44 #define CVMX_SRIOX_INT_ENABLE(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000110ull) + ((block_id) & 3) * 0x1000000ull)
  45 #define CVMX_SRIOX_INT_INFO0(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000120ull) + ((block_id) & 3) * 0x1000000ull)
  46 #define CVMX_SRIOX_INT_INFO1(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000128ull) + ((block_id) & 3) * 0x1000000ull)
  47 #define CVMX_SRIOX_INT_INFO2(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000130ull) + ((block_id) & 3) * 0x1000000ull)
  48 #define CVMX_SRIOX_INT_INFO3(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000138ull) + ((block_id) & 3) * 0x1000000ull)
  49 #define CVMX_SRIOX_INT_REG(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000118ull) + ((block_id) & 3) * 0x1000000ull)
  50 #define CVMX_SRIOX_IP_FEATURE(block_id) (CVMX_ADD_IO_SEG(0x00011800C80003F8ull) + ((block_id) & 3) * 0x1000000ull)
  51 #define CVMX_SRIOX_MAC_BUFFERS(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000390ull) + ((block_id) & 3) * 0x1000000ull)
  52 #define CVMX_SRIOX_MAINT_OP(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000158ull) + ((block_id) & 3) * 0x1000000ull)
  53 #define CVMX_SRIOX_MAINT_RD_DATA(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000160ull) + ((block_id) & 3) * 0x1000000ull)
  54 #define CVMX_SRIOX_MCE_TX_CTL(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000240ull) + ((block_id) & 3) * 0x1000000ull)
  55 #define CVMX_SRIOX_MEM_OP_CTRL(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000168ull) + ((block_id) & 3) * 0x1000000ull)
  56 #define CVMX_SRIOX_OMSG_CTRLX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C8000488ull) + (((offset) & 1) + ((block_id) & 3) * 0x40000ull) * 64)
  57 #define CVMX_SRIOX_OMSG_DONE_COUNTSX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C80004B0ull) + (((offset) & 1) + ((block_id) & 3) * 0x40000ull) * 64)
  58 #define CVMX_SRIOX_OMSG_FMP_MRX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C8000498ull) + (((offset) & 1) + ((block_id) & 3) * 0x40000ull) * 64)
  59 #define CVMX_SRIOX_OMSG_NMP_MRX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C80004A0ull) + (((offset) & 1) + ((block_id) & 3) * 0x40000ull) * 64)
  60 #define CVMX_SRIOX_OMSG_PORTX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C8000480ull) + (((offset) & 1) + ((block_id) & 3) * 0x40000ull) * 64)
  61 #define CVMX_SRIOX_OMSG_SILO_THR(block_id) (CVMX_ADD_IO_SEG(0x00011800C80004F8ull) + ((block_id) & 3) * 0x1000000ull)
  62 #define CVMX_SRIOX_OMSG_SP_MRX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C8000490ull) + (((offset) & 1) + ((block_id) & 3) * 0x40000ull) * 64)
  63 #define CVMX_SRIOX_PRIOX_IN_USE(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C80003C0ull) + (((offset) & 3) + ((block_id) & 3) * 0x200000ull) * 8)
  64 #define CVMX_SRIOX_RX_BELL(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000308ull) + ((block_id) & 3) * 0x1000000ull)
  65 #define CVMX_SRIOX_RX_BELL_SEQ(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000300ull) + ((block_id) & 3) * 0x1000000ull)
  66 #define CVMX_SRIOX_RX_STATUS(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000380ull) + ((block_id) & 3) * 0x1000000ull)
  67 #define CVMX_SRIOX_S2M_TYPEX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C8000180ull) + (((offset) & 15) + ((block_id) & 3) * 0x200000ull) * 8)
  68 #define CVMX_SRIOX_SEQ(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000278ull) + ((block_id) & 3) * 0x1000000ull)
  69 #define CVMX_SRIOX_STATUS_REG(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000100ull) + ((block_id) & 3) * 0x1000000ull)
  70 #define CVMX_SRIOX_TAG_CTRL(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000178ull) + ((block_id) & 3) * 0x1000000ull)
  71 #define CVMX_SRIOX_TLP_CREDITS(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000150ull) + ((block_id) & 3) * 0x1000000ull)
  72 #define CVMX_SRIOX_TX_BELL(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000280ull) + ((block_id) & 3) * 0x1000000ull)
  73 #define CVMX_SRIOX_TX_BELL_INFO(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000288ull) + ((block_id) & 3) * 0x1000000ull)
  74 #define CVMX_SRIOX_TX_CTRL(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000170ull) + ((block_id) & 3) * 0x1000000ull)
  75 #define CVMX_SRIOX_TX_EMPHASIS(block_id) (CVMX_ADD_IO_SEG(0x00011800C80003F0ull) + ((block_id) & 3) * 0x1000000ull)
  76 #define CVMX_SRIOX_TX_STATUS(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000388ull) + ((block_id) & 3) * 0x1000000ull)
  77 #define CVMX_SRIOX_WR_DONE_COUNTS(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000340ull) + ((block_id) & 3) * 0x1000000ull)
  78
  79 union cvmx_sriox_acc_ctrl {
  80         uint64_t u64;
  81         struct cvmx_sriox_acc_ctrl_s {
  82 #ifdef __BIG_ENDIAN_BITFIELD
  83                 uint64_t reserved_7_63:57;
  84                 uint64_t deny_adr2:1;
  85                 uint64_t deny_adr1:1;
  86                 uint64_t deny_adr0:1;
  87                 uint64_t reserved_3_3:1;
  88                 uint64_t deny_bar2:1;
  89                 uint64_t deny_bar1:1;
  90                 uint64_t deny_bar0:1;
  91 #else
  92                 uint64_t deny_bar0:1;
  93                 uint64_t deny_bar1:1;
  94                 uint64_t deny_bar2:1;
  95                 uint64_t reserved_3_3:1;
  96                 uint64_t deny_adr0:1;
  97                 uint64_t deny_adr1:1;
  98                 uint64_t deny_adr2:1;
  99                 uint64_t reserved_7_63:57;
 100 #endif
 101         } s;
 102         struct cvmx_sriox_acc_ctrl_cn63xx {
 103 #ifdef __BIG_ENDIAN_BITFIELD
 104                 uint64_t reserved_3_63:61;
 105                 uint64_t deny_bar2:1;
 106                 uint64_t deny_bar1:1;
 107                 uint64_t deny_bar0:1;
 108 #else
 109                 uint64_t deny_bar0:1;
 110                 uint64_t deny_bar1:1;
 111                 uint64_t deny_bar2:1;
 112                 uint64_t reserved_3_63:61;
 113 #endif
 114         } cn63xx;
 115         struct cvmx_sriox_acc_ctrl_cn63xx cn63xxp1;
 116         struct cvmx_sriox_acc_ctrl_s cn66xx;
 117 };
 118
 119 union cvmx_sriox_asmbly_id {
 120         uint64_t u64;
 121         struct cvmx_sriox_asmbly_id_s {
 122 #ifdef __BIG_ENDIAN_BITFIELD
 123                 uint64_t reserved_32_63:32;
 124                 uint64_t assy_id:16;
 125                 uint64_t assy_ven:16;
 126 #else
 127                 uint64_t assy_ven:16;
 128                 uint64_t assy_id:16;
 129                 uint64_t reserved_32_63:32;
 130 #endif
 131         } s;
 132         struct cvmx_sriox_asmbly_id_s cn63xx;
 133         struct cvmx_sriox_asmbly_id_s cn63xxp1;
 134         struct cvmx_sriox_asmbly_id_s cn66xx;
 135 };
 136
 137 union cvmx_sriox_asmbly_info {
 138         uint64_t u64;
 139         struct cvmx_sriox_asmbly_info_s {
 140 #ifdef __BIG_ENDIAN_BITFIELD
 141                 uint64_t reserved_32_63:32;
 142                 uint64_t assy_rev:16;
 143                 uint64_t reserved_0_15:16;
 144 #else
 145                 uint64_t reserved_0_15:16;
 146                 uint64_t assy_rev:16;
 147                 uint64_t reserved_32_63:32;
 148 #endif
 149         } s;
 150         struct cvmx_sriox_asmbly_info_s cn63xx;
 151         struct cvmx_sriox_asmbly_info_s cn63xxp1;
 152         struct cvmx_sriox_asmbly_info_s cn66xx;
 153 };
 154
 155 union cvmx_sriox_bell_resp_ctrl {
 156         uint64_t u64;
 157         struct cvmx_sriox_bell_resp_ctrl_s {
 158 #ifdef __BIG_ENDIAN_BITFIELD
 159                 uint64_t reserved_6_63:58;
 160                 uint64_t rp1_sid:1;
 161                 uint64_t rp0_sid:2;
 162                 uint64_t rp1_pid:1;
 163                 uint64_t rp0_pid:2;
 164 #else
 165                 uint64_t rp0_pid:2;
 166                 uint64_t rp1_pid:1;
 167                 uint64_t rp0_sid:2;
 168                 uint64_t rp1_sid:1;
 169                 uint64_t reserved_6_63:58;
 170 #endif
 171         } s;
 172         struct cvmx_sriox_bell_resp_ctrl_s cn63xx;
 173         struct cvmx_sriox_bell_resp_ctrl_s cn63xxp1;
 174         struct cvmx_sriox_bell_resp_ctrl_s cn66xx;
 175 };
 176
 177 union cvmx_sriox_bist_status {
 178         uint64_t u64;
 179         struct cvmx_sriox_bist_status_s {
 180 #ifdef __BIG_ENDIAN_BITFIELD
 181                 uint64_t reserved_45_63:19;
 182                 uint64_t lram:1;
 183                 uint64_t mram:2;
 184                 uint64_t cram:2;
 185                 uint64_t bell:2;
 186                 uint64_t otag:2;
 187                 uint64_t itag:1;
 188                 uint64_t ofree:1;
 189                 uint64_t rtn:2;
 190                 uint64_t obulk:4;
 191                 uint64_t optrs:4;
 192                 uint64_t oarb2:2;
 193                 uint64_t rxbuf2:2;
 194                 uint64_t oarb:2;
 195                 uint64_t ispf:1;
 196                 uint64_t ospf:1;
 197                 uint64_t txbuf:2;
 198                 uint64_t rxbuf:2;
 199                 uint64_t imsg:5;
 200                 uint64_t omsg:7;
 201 #else
 202                 uint64_t omsg:7;
 203                 uint64_t imsg:5;
 204                 uint64_t rxbuf:2;
 205                 uint64_t txbuf:2;
 206                 uint64_t ospf:1;
 207                 uint64_t ispf:1;
 208                 uint64_t oarb:2;
 209                 uint64_t rxbuf2:2;
 210                 uint64_t oarb2:2;
 211                 uint64_t optrs:4;
 212                 uint64_t obulk:4;
 213                 uint64_t rtn:2;
 214                 uint64_t ofree:1;
 215                 uint64_t itag:1;
 216                 uint64_t otag:2;
 217                 uint64_t bell:2;
 218                 uint64_t cram:2;
 219                 uint64_t mram:2;
 220                 uint64_t lram:1;
 221                 uint64_t reserved_45_63:19;
 222 #endif
 223         } s;
 224         struct cvmx_sriox_bist_status_cn63xx {
 225 #ifdef __BIG_ENDIAN_BITFIELD
 226                 uint64_t reserved_44_63:20;
 227                 uint64_t mram:2;
 228                 uint64_t cram:2;
 229                 uint64_t bell:2;
 230                 uint64_t otag:2;
 231                 uint64_t itag:1;
 232                 uint64_t ofree:1;
 233                 uint64_t rtn:2;
 234                 uint64_t obulk:4;
 235                 uint64_t optrs:4;
 236                 uint64_t oarb2:2;
 237                 uint64_t rxbuf2:2;
 238                 uint64_t oarb:2;
 239                 uint64_t ispf:1;
 240                 uint64_t ospf:1;
 241                 uint64_t txbuf:2;
 242                 uint64_t rxbuf:2;
 243                 uint64_t imsg:5;
 244                 uint64_t omsg:7;
 245 #else
 246                 uint64_t omsg:7;
 247                 uint64_t imsg:5;
 248                 uint64_t rxbuf:2;
 249                 uint64_t txbuf:2;
 250                 uint64_t ospf:1;
 251                 uint64_t ispf:1;
 252                 uint64_t oarb:2;
 253                 uint64_t rxbuf2:2;
 254                 uint64_t oarb2:2;
 255                 uint64_t optrs:4;
 256                 uint64_t obulk:4;
 257                 uint64_t rtn:2;
 258                 uint64_t ofree:1;
 259                 uint64_t itag:1;
 260                 uint64_t otag:2;
 261                 uint64_t bell:2;
 262                 uint64_t cram:2;
 263                 uint64_t mram:2;
 264                 uint64_t reserved_44_63:20;
 265 #endif
 266         } cn63xx;
 267         struct cvmx_sriox_bist_status_cn63xxp1 {
 268 #ifdef __BIG_ENDIAN_BITFIELD
 269                 uint64_t reserved_44_63:20;
 270                 uint64_t mram:2;
 271                 uint64_t cram:2;
 272                 uint64_t bell:2;
 273                 uint64_t otag:2;
 274                 uint64_t itag:1;
 275                 uint64_t ofree:1;
 276                 uint64_t rtn:2;
 277                 uint64_t obulk:4;
 278                 uint64_t optrs:4;
 279                 uint64_t reserved_20_23:4;
 280                 uint64_t oarb:2;
 281                 uint64_t ispf:1;
 282                 uint64_t ospf:1;
 283                 uint64_t txbuf:2;
 284                 uint64_t rxbuf:2;
 285                 uint64_t imsg:5;
 286                 uint64_t omsg:7;
 287 #else
 288                 uint64_t omsg:7;
 289                 uint64_t imsg:5;
 290                 uint64_t rxbuf:2;
 291                 uint64_t txbuf:2;
 292                 uint64_t ospf:1;
 293                 uint64_t ispf:1;
 294                 uint64_t oarb:2;
 295                 uint64_t reserved_20_23:4;
 296                 uint64_t optrs:4;
 297                 uint64_t obulk:4;
 298                 uint64_t rtn:2;
 299                 uint64_t ofree:1;
 300                 uint64_t itag:1;
 301                 uint64_t otag:2;
 302                 uint64_t bell:2;
 303                 uint64_t cram:2;
 304                 uint64_t mram:2;
 305                 uint64_t reserved_44_63:20;
 306 #endif
 307         } cn63xxp1;
 308         struct cvmx_sriox_bist_status_s cn66xx;
 309 };
 310
 311 union cvmx_sriox_imsg_ctrl {
 312         uint64_t u64;
 313         struct cvmx_sriox_imsg_ctrl_s {
 314 #ifdef __BIG_ENDIAN_BITFIELD
 315                 uint64_t reserved_32_63:32;
 316                 uint64_t to_mode:1;
 317                 uint64_t reserved_30_30:1;
 318                 uint64_t rsp_thr:6;
 319                 uint64_t reserved_22_23:2;
 320                 uint64_t rp1_sid:1;
 321                 uint64_t rp0_sid:2;
 322                 uint64_t rp1_pid:1;
 323                 uint64_t rp0_pid:2;
 324                 uint64_t reserved_15_15:1;
 325                 uint64_t prt_sel:3;
 326                 uint64_t lttr:4;
 327                 uint64_t prio:4;
 328                 uint64_t mbox:4;
 329 #else
 330                 uint64_t mbox:4;
 331                 uint64_t prio:4;
 332                 uint64_t lttr:4;
 333                 uint64_t prt_sel:3;
 334                 uint64_t reserved_15_15:1;
 335                 uint64_t rp0_pid:2;
 336                 uint64_t rp1_pid:1;
 337                 uint64_t rp0_sid:2;
 338                 uint64_t rp1_sid:1;
 339                 uint64_t reserved_22_23:2;
 340                 uint64_t rsp_thr:6;
 341                 uint64_t reserved_30_30:1;
 342                 uint64_t to_mode:1;
 343                 uint64_t reserved_32_63:32;
 344 #endif
 345         } s;
 346         struct cvmx_sriox_imsg_ctrl_s cn63xx;
 347         struct cvmx_sriox_imsg_ctrl_s cn63xxp1;
 348         struct cvmx_sriox_imsg_ctrl_s cn66xx;
 349 };
 350
 351 union cvmx_sriox_imsg_inst_hdrx {
 352         uint64_t u64;
 353         struct cvmx_sriox_imsg_inst_hdrx_s {
 354 #ifdef __BIG_ENDIAN_BITFIELD
 355                 uint64_t r:1;
 356                 uint64_t reserved_58_62:5;
 357                 uint64_t pm:2;
 358                 uint64_t reserved_55_55:1;
 359                 uint64_t sl:7;
 360                 uint64_t reserved_46_47:2;
 361                 uint64_t nqos:1;
 362                 uint64_t ngrp:1;
 363                 uint64_t ntt:1;
 364                 uint64_t ntag:1;
 365                 uint64_t reserved_35_41:7;
 366                 uint64_t rs:1;
 367                 uint64_t tt:2;
 368                 uint64_t tag:32;
 369 #else
 370                 uint64_t tag:32;
 371                 uint64_t tt:2;
 372                 uint64_t rs:1;
 373                 uint64_t reserved_35_41:7;
 374                 uint64_t ntag:1;
 375                 uint64_t ntt:1;
 376                 uint64_t ngrp:1;
 377                 uint64_t nqos:1;
 378                 uint64_t reserved_46_47:2;
 379                 uint64_t sl:7;
 380                 uint64_t reserved_55_55:1;
 381                 uint64_t pm:2;
 382                 uint64_t reserved_58_62:5;
 383                 uint64_t r:1;
 384 #endif
 385         } s;
 386         struct cvmx_sriox_imsg_inst_hdrx_s cn63xx;
 387         struct cvmx_sriox_imsg_inst_hdrx_s cn63xxp1;
 388         struct cvmx_sriox_imsg_inst_hdrx_s cn66xx;
 389 };
 390
 391 union cvmx_sriox_imsg_qos_grpx {
 392         uint64_t u64;
 393         struct cvmx_sriox_imsg_qos_grpx_s {
 394 #ifdef __BIG_ENDIAN_BITFIELD
 395                 uint64_t reserved_63_63:1;
 396                 uint64_t qos7:3;
 397                 uint64_t grp7:4;
 398                 uint64_t reserved_55_55:1;
 399                 uint64_t qos6:3;
 400                 uint64_t grp6:4;
 401                 uint64_t reserved_47_47:1;
 402                 uint64_t qos5:3;
 403                 uint64_t grp5:4;
 404                 uint64_t reserved_39_39:1;
 405                 uint64_t qos4:3;
 406                 uint64_t grp4:4;
 407                 uint64_t reserved_31_31:1;
 408                 uint64_t qos3:3;
 409                 uint64_t grp3:4;
 410                 uint64_t reserved_23_23:1;
 411                 uint64_t qos2:3;
 412                 uint64_t grp2:4;
 413                 uint64_t reserved_15_15:1;
 414                 uint64_t qos1:3;
 415                 uint64_t grp1:4;
 416                 uint64_t reserved_7_7:1;
 417                 uint64_t qos0:3;
 418                 uint64_t grp0:4;
 419 #else
 420                 uint64_t grp0:4;
 421                 uint64_t qos0:3;
 422                 uint64_t reserved_7_7:1;
 423                 uint64_t grp1:4;
 424                 uint64_t qos1:3;
 425                 uint64_t reserved_15_15:1;
 426                 uint64_t grp2:4;
 427                 uint64_t qos2:3;
 428                 uint64_t reserved_23_23:1;
 429                 uint64_t grp3:4;
 430                 uint64_t qos3:3;
 431                 uint64_t reserved_31_31:1;
 432                 uint64_t grp4:4;
 433                 uint64_t qos4:3;
 434                 uint64_t reserved_39_39:1;
 435                 uint64_t grp5:4;
 436                 uint64_t qos5:3;
 437                 uint64_t reserved_47_47:1;
 438                 uint64_t grp6:4;
 439                 uint64_t qos6:3;
 440                 uint64_t reserved_55_55:1;
 441                 uint64_t grp7:4;
 442                 uint64_t qos7:3;
 443                 uint64_t reserved_63_63:1;
 444 #endif
 445         } s;
 446         struct cvmx_sriox_imsg_qos_grpx_s cn63xx;
 447         struct cvmx_sriox_imsg_qos_grpx_s cn63xxp1;
 448         struct cvmx_sriox_imsg_qos_grpx_s cn66xx;
 449 };
 450
 451 union cvmx_sriox_imsg_statusx {
 452         uint64_t u64;
 453         struct cvmx_sriox_imsg_statusx_s {
 454 #ifdef __BIG_ENDIAN_BITFIELD
 455                 uint64_t val1:1;
 456                 uint64_t err1:1;
 457                 uint64_t toe1:1;
 458                 uint64_t toc1:1;
 459                 uint64_t prt1:1;
 460                 uint64_t reserved_58_58:1;
 461                 uint64_t tt1:1;
 462                 uint64_t dis1:1;
 463                 uint64_t seg1:4;
 464                 uint64_t mbox1:2;
 465                 uint64_t lttr1:2;
 466                 uint64_t sid1:16;
 467                 uint64_t val0:1;
 468                 uint64_t err0:1;
 469                 uint64_t toe0:1;
 470                 uint64_t toc0:1;
 471                 uint64_t prt0:1;
 472                 uint64_t reserved_26_26:1;
 473                 uint64_t tt0:1;
 474                 uint64_t dis0:1;
 475                 uint64_t seg0:4;
 476                 uint64_t mbox0:2;
 477                 uint64_t lttr0:2;
 478                 uint64_t sid0:16;
 479 #else
 480                 uint64_t sid0:16;
 481                 uint64_t lttr0:2;
 482                 uint64_t mbox0:2;
 483                 uint64_t seg0:4;
 484                 uint64_t dis0:1;
 485                 uint64_t tt0:1;
 486                 uint64_t reserved_26_26:1;
 487                 uint64_t prt0:1;
 488                 uint64_t toc0:1;
 489                 uint64_t toe0:1;
 490                 uint64_t err0:1;
 491                 uint64_t val0:1;
 492                 uint64_t sid1:16;
 493                 uint64_t lttr1:2;
 494                 uint64_t mbox1:2;
 495                 uint64_t seg1:4;
 496                 uint64_t dis1:1;
 497                 uint64_t tt1:1;
 498                 uint64_t reserved_58_58:1;
 499                 uint64_t prt1:1;
 500                 uint64_t toc1:1;
 501                 uint64_t toe1:1;
 502                 uint64_t err1:1;
 503                 uint64_t val1:1;
 504 #endif
 505         } s;
 506         struct cvmx_sriox_imsg_statusx_s cn63xx;
 507         struct cvmx_sriox_imsg_statusx_s cn63xxp1;
 508         struct cvmx_sriox_imsg_statusx_s cn66xx;
 509 };
 510
 511 union cvmx_sriox_imsg_vport_thr {
 512         uint64_t u64;
 513         struct cvmx_sriox_imsg_vport_thr_s {
 514 #ifdef __BIG_ENDIAN_BITFIELD
 515                 uint64_t reserved_54_63:10;
 516                 uint64_t max_tot:6;
 517                 uint64_t reserved_46_47:2;
 518                 uint64_t max_s1:6;
 519                 uint64_t reserved_38_39:2;
 520                 uint64_t max_s0:6;
 521                 uint64_t sp_vport:1;
 522                 uint64_t reserved_20_30:11;
 523                 uint64_t buf_thr:4;
 524                 uint64_t reserved_14_15:2;
 525                 uint64_t max_p1:6;
 526                 uint64_t reserved_6_7:2;
 527                 uint64_t max_p0:6;
 528 #else
 529                 uint64_t max_p0:6;
 530                 uint64_t reserved_6_7:2;
 531                 uint64_t max_p1:6;
 532                 uint64_t reserved_14_15:2;
 533                 uint64_t buf_thr:4;
 534                 uint64_t reserved_20_30:11;
 535                 uint64_t sp_vport:1;
 536                 uint64_t max_s0:6;
 537                 uint64_t reserved_38_39:2;
 538                 uint64_t max_s1:6;
 539                 uint64_t reserved_46_47:2;
 540                 uint64_t max_tot:6;
 541                 uint64_t reserved_54_63:10;
 542 #endif
 543         } s;
 544         struct cvmx_sriox_imsg_vport_thr_s cn63xx;
 545         struct cvmx_sriox_imsg_vport_thr_s cn63xxp1;
 546         struct cvmx_sriox_imsg_vport_thr_s cn66xx;
 547 };
 548
 549 union cvmx_sriox_imsg_vport_thr2 {
 550         uint64_t u64;
 551         struct cvmx_sriox_imsg_vport_thr2_s {
 552 #ifdef __BIG_ENDIAN_BITFIELD
 553                 uint64_t reserved_46_63:18;
 554                 uint64_t max_s3:6;
 555                 uint64_t reserved_38_39:2;
 556                 uint64_t max_s2:6;
 557                 uint64_t reserved_0_31:32;
 558 #else
 559                 uint64_t reserved_0_31:32;
 560                 uint64_t max_s2:6;
 561                 uint64_t reserved_38_39:2;
 562                 uint64_t max_s3:6;
 563                 uint64_t reserved_46_63:18;
 564 #endif
 565         } s;
 566         struct cvmx_sriox_imsg_vport_thr2_s cn66xx;
 567 };
 568
 569 union cvmx_sriox_int2_enable {
 570         uint64_t u64;
 571         struct cvmx_sriox_int2_enable_s {
 572 #ifdef __BIG_ENDIAN_BITFIELD
 573                 uint64_t reserved_1_63:63;
 574                 uint64_t pko_rst:1;
 575 #else
 576                 uint64_t pko_rst:1;
 577                 uint64_t reserved_1_63:63;
 578 #endif
 579         } s;
 580         struct cvmx_sriox_int2_enable_s cn63xx;
 581         struct cvmx_sriox_int2_enable_s cn66xx;
 582 };
 583
 584 union cvmx_sriox_int2_reg {
 585         uint64_t u64;
 586         struct cvmx_sriox_int2_reg_s {
 587 #ifdef __BIG_ENDIAN_BITFIELD
 588                 uint64_t reserved_32_63:32;
 589                 uint64_t int_sum:1;
 590                 uint64_t reserved_1_30:30;
 591                 uint64_t pko_rst:1;
 592 #else
 593                 uint64_t pko_rst:1;
 594                 uint64_t reserved_1_30:30;
 595                 uint64_t int_sum:1;
 596                 uint64_t reserved_32_63:32;
 597 #endif
 598         } s;
 599         struct cvmx_sriox_int2_reg_s cn63xx;
 600         struct cvmx_sriox_int2_reg_s cn66xx;
 601 };
 602
 603 union cvmx_sriox_int_enable {
 604         uint64_t u64;
 605         struct cvmx_sriox_int_enable_s {
 606 #ifdef __BIG_ENDIAN_BITFIELD
 607                 uint64_t reserved_27_63:37;
 608                 uint64_t zero_pkt:1;
 609                 uint64_t ttl_tout:1;
 610                 uint64_t fail:1;
 611                 uint64_t degrade:1;
 612                 uint64_t mac_buf:1;
 613                 uint64_t f_error:1;
 614                 uint64_t rtry_err:1;
 615                 uint64_t pko_err:1;
 616                 uint64_t omsg_err:1;
 617                 uint64_t omsg1:1;
 618                 uint64_t omsg0:1;
 619                 uint64_t link_up:1;
 620                 uint64_t link_dwn:1;
 621                 uint64_t phy_erb:1;
 622                 uint64_t log_erb:1;
 623                 uint64_t soft_rx:1;
 624                 uint64_t soft_tx:1;
 625                 uint64_t mce_rx:1;
 626                 uint64_t mce_tx:1;
 627                 uint64_t wr_done:1;
 628                 uint64_t sli_err:1;
 629                 uint64_t deny_wr:1;
 630                 uint64_t bar_err:1;
 631                 uint64_t maint_op:1;
 632                 uint64_t rxbell:1;
 633                 uint64_t bell_err:1;
 634                 uint64_t txbell:1;
 635 #else
 636                 uint64_t txbell:1;
 637                 uint64_t bell_err:1;
 638                 uint64_t rxbell:1;
 639                 uint64_t maint_op:1;
 640                 uint64_t bar_err:1;
 641                 uint64_t deny_wr:1;
 642                 uint64_t sli_err:1;
 643                 uint64_t wr_done:1;
 644                 uint64_t mce_tx:1;
 645                 uint64_t mce_rx:1;
 646                 uint64_t soft_tx:1;
 647                 uint64_t soft_rx:1;
 648                 uint64_t log_erb:1;
 649                 uint64_t phy_erb:1;
 650                 uint64_t link_dwn:1;
 651                 uint64_t link_up:1;
 652                 uint64_t omsg0:1;
 653                 uint64_t omsg1:1;
 654                 uint64_t omsg_err:1;
 655                 uint64_t pko_err:1;
 656                 uint64_t rtry_err:1;
 657                 uint64_t f_error:1;
 658                 uint64_t mac_buf:1;
 659                 uint64_t degrade:1;
 660                 uint64_t fail:1;
 661                 uint64_t ttl_tout:1;
 662                 uint64_t zero_pkt:1;
 663                 uint64_t reserved_27_63:37;
 664 #endif
 665         } s;
 666         struct cvmx_sriox_int_enable_s cn63xx;
 667         struct cvmx_sriox_int_enable_cn63xxp1 {
 668 #ifdef __BIG_ENDIAN_BITFIELD
 669                 uint64_t reserved_22_63:42;
 670                 uint64_t f_error:1;
 671                 uint64_t rtry_err:1;
 672                 uint64_t pko_err:1;
 673                 uint64_t omsg_err:1;
 674                 uint64_t omsg1:1;
 675                 uint64_t omsg0:1;
 676                 uint64_t link_up:1;
 677                 uint64_t link_dwn:1;
 678                 uint64_t phy_erb:1;
 679                 uint64_t log_erb:1;
 680                 uint64_t soft_rx:1;
 681                 uint64_t soft_tx:1;
 682                 uint64_t mce_rx:1;
 683                 uint64_t mce_tx:1;
 684                 uint64_t wr_done:1;
 685                 uint64_t sli_err:1;
 686                 uint64_t deny_wr:1;
 687                 uint64_t bar_err:1;
 688                 uint64_t maint_op:1;
 689                 uint64_t rxbell:1;
 690                 uint64_t bell_err:1;
 691                 uint64_t txbell:1;
 692 #else
 693                 uint64_t txbell:1;
 694                 uint64_t bell_err:1;
 695                 uint64_t rxbell:1;
 696                 uint64_t maint_op:1;
 697                 uint64_t bar_err:1;
 698                 uint64_t deny_wr:1;
 699                 uint64_t sli_err:1;
 700                 uint64_t wr_done:1;
 701                 uint64_t mce_tx:1;
 702                 uint64_t mce_rx:1;
 703                 uint64_t soft_tx:1;
 704                 uint64_t soft_rx:1;
 705                 uint64_t log_erb:1;
 706                 uint64_t phy_erb:1;
 707                 uint64_t link_dwn:1;
 708                 uint64_t link_up:1;
 709                 uint64_t omsg0:1;
 710                 uint64_t omsg1:1;
 711                 uint64_t omsg_err:1;
 712                 uint64_t pko_err:1;
 713                 uint64_t rtry_err:1;
 714                 uint64_t f_error:1;
 715                 uint64_t reserved_22_63:42;
 716 #endif
 717         } cn63xxp1;
 718         struct cvmx_sriox_int_enable_s cn66xx;
 719 };
 720
 721 union cvmx_sriox_int_info0 {
 722         uint64_t u64;
 723         struct cvmx_sriox_int_info0_s {
 724 #ifdef __BIG_ENDIAN_BITFIELD
 725                 uint64_t cmd:4;
 726                 uint64_t type:4;
 727                 uint64_t tag:8;
 728                 uint64_t reserved_42_47:6;
 729                 uint64_t length:10;
 730                 uint64_t status:3;
 731                 uint64_t reserved_16_28:13;
 732                 uint64_t be0:8;
 733                 uint64_t be1:8;
 734 #else
 735                 uint64_t be1:8;
 736                 uint64_t be0:8;
 737                 uint64_t reserved_16_28:13;
 738                 uint64_t status:3;
 739                 uint64_t length:10;
 740                 uint64_t reserved_42_47:6;
 741                 uint64_t tag:8;
 742                 uint64_t type:4;
 743                 uint64_t cmd:4;
 744 #endif
 745         } s;
 746         struct cvmx_sriox_int_info0_s cn63xx;
 747         struct cvmx_sriox_int_info0_s cn63xxp1;
 748         struct cvmx_sriox_int_info0_s cn66xx;
 749 };
 750
 751 union cvmx_sriox_int_info1 {
 752         uint64_t u64;
 753         struct cvmx_sriox_int_info1_s {
 754 #ifdef __BIG_ENDIAN_BITFIELD
 755                 uint64_t info1:64;
 756 #else
 757                 uint64_t info1:64;
 758 #endif
 759         } s;
 760         struct cvmx_sriox_int_info1_s cn63xx;
 761         struct cvmx_sriox_int_info1_s cn63xxp1;
 762         struct cvmx_sriox_int_info1_s cn66xx;
 763 };
 764
 765 union cvmx_sriox_int_info2 {
 766         uint64_t u64;
 767         struct cvmx_sriox_int_info2_s {
 768 #ifdef __BIG_ENDIAN_BITFIELD
 769                 uint64_t prio:2;
 770                 uint64_t tt:1;
 771                 uint64_t sis:1;
 772                 uint64_t ssize:4;
 773                 uint64_t did:16;
 774                 uint64_t xmbox:4;
 775                 uint64_t mbox:2;
 776                 uint64_t letter:2;
 777                 uint64_t rsrvd:30;
 778                 uint64_t lns:1;
 779                 uint64_t intr:1;
 780 #else
 781                 uint64_t intr:1;
 782                 uint64_t lns:1;
 783                 uint64_t rsrvd:30;
 784                 uint64_t letter:2;
 785                 uint64_t mbox:2;
 786                 uint64_t xmbox:4;
 787                 uint64_t did:16;
 788                 uint64_t ssize:4;
 789                 uint64_t sis:1;
 790                 uint64_t tt:1;
 791                 uint64_t prio:2;
 792 #endif
 793         } s;
 794         struct cvmx_sriox_int_info2_s cn63xx;
 795         struct cvmx_sriox_int_info2_s cn63xxp1;
 796         struct cvmx_sriox_int_info2_s cn66xx;
 797 };
 798
 799 union cvmx_sriox_int_info3 {
 800         uint64_t u64;
 801         struct cvmx_sriox_int_info3_s {
 802 #ifdef __BIG_ENDIAN_BITFIELD
 803                 uint64_t prio:2;
 804                 uint64_t tt:2;
 805                 uint64_t type:4;
 806                 uint64_t other:48;
 807                 uint64_t reserved_0_7:8;
 808 #else
 809                 uint64_t reserved_0_7:8;
 810                 uint64_t other:48;
 811                 uint64_t type:4;
 812                 uint64_t tt:2;
 813                 uint64_t prio:2;
 814 #endif
 815         } s;
 816         struct cvmx_sriox_int_info3_s cn63xx;
 817         struct cvmx_sriox_int_info3_s cn63xxp1;
 818         struct cvmx_sriox_int_info3_s cn66xx;
 819 };
 820
 821 union cvmx_sriox_int_reg {
 822         uint64_t u64;
 823         struct cvmx_sriox_int_reg_s {
 824 #ifdef __BIG_ENDIAN_BITFIELD
 825                 uint64_t reserved_32_63:32;
 826                 uint64_t int2_sum:1;
 827                 uint64_t reserved_27_30:4;
 828                 uint64_t zero_pkt:1;
 829                 uint64_t ttl_tout:1;
 830                 uint64_t fail:1;
 831                 uint64_t degrad:1;
 832                 uint64_t mac_buf:1;
 833                 uint64_t f_error:1;
 834                 uint64_t rtry_err:1;
 835                 uint64_t pko_err:1;
 836                 uint64_t omsg_err:1;
 837                 uint64_t omsg1:1;
 838                 uint64_t omsg0:1;
 839                 uint64_t link_up:1;
 840                 uint64_t link_dwn:1;
 841                 uint64_t phy_erb:1;
 842                 uint64_t log_erb:1;
 843                 uint64_t soft_rx:1;
 844                 uint64_t soft_tx:1;
 845                 uint64_t mce_rx:1;
 846                 uint64_t mce_tx:1;
 847                 uint64_t wr_done:1;
 848                 uint64_t sli_err:1;
 849                 uint64_t deny_wr:1;
 850                 uint64_t bar_err:1;
 851                 uint64_t maint_op:1;
 852                 uint64_t rxbell:1;
 853                 uint64_t bell_err:1;
 854                 uint64_t txbell:1;
 855 #else
 856                 uint64_t txbell:1;
 857                 uint64_t bell_err:1;
 858                 uint64_t rxbell:1;
 859                 uint64_t maint_op:1;
 860                 uint64_t bar_err:1;
 861                 uint64_t deny_wr:1;
 862                 uint64_t sli_err:1;
 863                 uint64_t wr_done:1;
 864                 uint64_t mce_tx:1;
 865                 uint64_t mce_rx:1;
 866                 uint64_t soft_tx:1;
 867                 uint64_t soft_rx:1;
 868                 uint64_t log_erb:1;
 869                 uint64_t phy_erb:1;
 870                 uint64_t link_dwn:1;
 871                 uint64_t link_up:1;
 872                 uint64_t omsg0:1;
 873                 uint64_t omsg1:1;
 874                 uint64_t omsg_err:1;
 875                 uint64_t pko_err:1;
 876                 uint64_t rtry_err:1;
 877                 uint64_t f_error:1;
 878                 uint64_t mac_buf:1;
 879                 uint64_t degrad:1;
 880                 uint64_t fail:1;
 881                 uint64_t ttl_tout:1;
 882                 uint64_t zero_pkt:1;
 883                 uint64_t reserved_27_30:4;
 884                 uint64_t int2_sum:1;
 885                 uint64_t reserved_32_63:32;
 886 #endif
 887         } s;
 888         struct cvmx_sriox_int_reg_s cn63xx;
 889         struct cvmx_sriox_int_reg_cn63xxp1 {
 890 #ifdef __BIG_ENDIAN_BITFIELD
 891                 uint64_t reserved_22_63:42;
 892                 uint64_t f_error:1;
 893                 uint64_t rtry_err:1;
 894                 uint64_t pko_err:1;
 895                 uint64_t omsg_err:1;
 896                 uint64_t omsg1:1;
 897                 uint64_t omsg0:1;
 898                 uint64_t link_up:1;
 899                 uint64_t link_dwn:1;
 900                 uint64_t phy_erb:1;
 901                 uint64_t log_erb:1;
 902                 uint64_t soft_rx:1;
 903                 uint64_t soft_tx:1;
 904                 uint64_t mce_rx:1;
 905                 uint64_t mce_tx:1;
 906                 uint64_t wr_done:1;
 907                 uint64_t sli_err:1;
 908                 uint64_t deny_wr:1;
 909                 uint64_t bar_err:1;
 910                 uint64_t maint_op:1;
 911                 uint64_t rxbell:1;
 912                 uint64_t bell_err:1;
 913                 uint64_t txbell:1;
 914 #else
 915                 uint64_t txbell:1;
 916                 uint64_t bell_err:1;
 917                 uint64_t rxbell:1;
 918                 uint64_t maint_op:1;
 919                 uint64_t bar_err:1;
 920                 uint64_t deny_wr:1;
 921                 uint64_t sli_err:1;
 922                 uint64_t wr_done:1;
 923                 uint64_t mce_tx:1;
 924                 uint64_t mce_rx:1;
 925                 uint64_t soft_tx:1;
 926                 uint64_t soft_rx:1;
 927                 uint64_t log_erb:1;
 928                 uint64_t phy_erb:1;
 929                 uint64_t link_dwn:1;
 930                 uint64_t link_up:1;
 931                 uint64_t omsg0:1;
 932                 uint64_t omsg1:1;
 933                 uint64_t omsg_err:1;
 934                 uint64_t pko_err:1;
 935                 uint64_t rtry_err:1;
 936                 uint64_t f_error:1;
 937                 uint64_t reserved_22_63:42;
 938 #endif
 939         } cn63xxp1;
 940         struct cvmx_sriox_int_reg_s cn66xx;
 941 };
 942
 943 union cvmx_sriox_ip_feature {
 944         uint64_t u64;
 945         struct cvmx_sriox_ip_feature_s {
 946 #ifdef __BIG_ENDIAN_BITFIELD
 947                 uint64_t ops:32;
 948                 uint64_t reserved_15_31:17;
 949                 uint64_t no_vmin:1;
 950                 uint64_t a66:1;
 951                 uint64_t a50:1;
 952                 uint64_t reserved_11_11:1;
 953                 uint64_t tx_flow:1;
 954                 uint64_t pt_width:2;
 955                 uint64_t tx_pol:4;
 956                 uint64_t rx_pol:4;
 957 #else
 958                 uint64_t rx_pol:4;
 959                 uint64_t tx_pol:4;
 960                 uint64_t pt_width:2;
 961                 uint64_t tx_flow:1;
 962                 uint64_t reserved_11_11:1;
 963                 uint64_t a50:1;
 964                 uint64_t a66:1;
 965                 uint64_t no_vmin:1;
 966                 uint64_t reserved_15_31:17;
 967                 uint64_t ops:32;
 968 #endif
 969         } s;
 970         struct cvmx_sriox_ip_feature_cn63xx {
 971 #ifdef __BIG_ENDIAN_BITFIELD
 972                 uint64_t ops:32;
 973                 uint64_t reserved_14_31:18;
 974                 uint64_t a66:1;
 975                 uint64_t a50:1;
 976                 uint64_t reserved_11_11:1;
 977                 uint64_t tx_flow:1;
 978                 uint64_t pt_width:2;
 979                 uint64_t tx_pol:4;
 980                 uint64_t rx_pol:4;
 981 #else
 982                 uint64_t rx_pol:4;
 983                 uint64_t tx_pol:4;
 984                 uint64_t pt_width:2;
 985                 uint64_t tx_flow:1;
 986                 uint64_t reserved_11_11:1;
 987                 uint64_t a50:1;
 988                 uint64_t a66:1;
 989                 uint64_t reserved_14_31:18;
 990                 uint64_t ops:32;
 991 #endif
 992         } cn63xx;
 993         struct cvmx_sriox_ip_feature_cn63xx cn63xxp1;
 994         struct cvmx_sriox_ip_feature_s cn66xx;
 995 };
 996
 997 union cvmx_sriox_mac_buffers {
 998         uint64_t u64;
 999         struct cvmx_sriox_mac_buffers_s {
1000 #ifdef __BIG_ENDIAN_BITFIELD
1001                 uint64_t reserved_56_63:8;
1002                 uint64_t tx_enb:8;
1003                 uint64_t reserved_44_47:4;
1004                 uint64_t tx_inuse:4;
1005                 uint64_t tx_stat:8;
1006                 uint64_t reserved_24_31:8;
1007                 uint64_t rx_enb:8;
1008                 uint64_t reserved_12_15:4;
1009                 uint64_t rx_inuse:4;
1010                 uint64_t rx_stat:8;
1011 #else
1012                 uint64_t rx_stat:8;
1013                 uint64_t rx_inuse:4;
1014                 uint64_t reserved_12_15:4;
1015                 uint64_t rx_enb:8;
1016                 uint64_t reserved_24_31:8;
1017                 uint64_t tx_stat:8;
1018                 uint64_t tx_inuse:4;
1019                 uint64_t reserved_44_47:4;
1020                 uint64_t tx_enb:8;
1021                 uint64_t reserved_56_63:8;
1022 #endif
1023         } s;
1024         struct cvmx_sriox_mac_buffers_s cn63xx;
1025         struct cvmx_sriox_mac_buffers_s cn66xx;
1026 };
1027
1028 union cvmx_sriox_maint_op {
1029         uint64_t u64;
1030         struct cvmx_sriox_maint_op_s {
1031 #ifdef __BIG_ENDIAN_BITFIELD
1032                 uint64_t wr_data:32;
1033                 uint64_t reserved_27_31:5;
1034                 uint64_t fail:1;
1035                 uint64_t pending:1;
1036                 uint64_t op:1;
1037                 uint64_t addr:24;
1038 #else
1039                 uint64_t addr:24;
1040                 uint64_t op:1;
1041                 uint64_t pending:1;
1042                 uint64_t fail:1;
1043                 uint64_t reserved_27_31:5;
1044                 uint64_t wr_data:32;
1045 #endif
1046         } s;
1047         struct cvmx_sriox_maint_op_s cn63xx;
1048         struct cvmx_sriox_maint_op_s cn63xxp1;
1049         struct cvmx_sriox_maint_op_s cn66xx;
1050 };
1051
1052 union cvmx_sriox_maint_rd_data {
1053         uint64_t u64;
1054         struct cvmx_sriox_maint_rd_data_s {
1055 #ifdef __BIG_ENDIAN_BITFIELD
1056                 uint64_t reserved_33_63:31;
1057                 uint64_t valid:1;
1058                 uint64_t rd_data:32;
1059 #else
1060                 uint64_t rd_data:32;
1061                 uint64_t valid:1;
1062                 uint64_t reserved_33_63:31;
1063 #endif
1064         } s;
1065         struct cvmx_sriox_maint_rd_data_s cn63xx;
1066         struct cvmx_sriox_maint_rd_data_s cn63xxp1;
1067         struct cvmx_sriox_maint_rd_data_s cn66xx;
1068 };
1069
1070 union cvmx_sriox_mce_tx_ctl {
1071         uint64_t u64;
1072         struct cvmx_sriox_mce_tx_ctl_s {
1073 #ifdef __BIG_ENDIAN_BITFIELD
1074                 uint64_t reserved_1_63:63;
1075                 uint64_t mce:1;
1076 #else
1077                 uint64_t mce:1;
1078                 uint64_t reserved_1_63:63;
1079 #endif
1080         } s;
1081         struct cvmx_sriox_mce_tx_ctl_s cn63xx;
1082         struct cvmx_sriox_mce_tx_ctl_s cn63xxp1;
1083         struct cvmx_sriox_mce_tx_ctl_s cn66xx;
1084 };
1085
1086 union cvmx_sriox_mem_op_ctrl {
1087         uint64_t u64;
1088         struct cvmx_sriox_mem_op_ctrl_s {
1089 #ifdef __BIG_ENDIAN_BITFIELD
1090                 uint64_t reserved_10_63:54;
1091                 uint64_t rr_ro:1;
1092                 uint64_t w_ro:1;
1093                 uint64_t reserved_6_7:2;
1094                 uint64_t rp1_sid:1;
1095                 uint64_t rp0_sid:2;
1096                 uint64_t rp1_pid:1;
1097                 uint64_t rp0_pid:2;
1098 #else
1099                 uint64_t rp0_pid:2;
1100                 uint64_t rp1_pid:1;
1101                 uint64_t rp0_sid:2;
1102                 uint64_t rp1_sid:1;
1103                 uint64_t reserved_6_7:2;
1104                 uint64_t w_ro:1;
1105                 uint64_t rr_ro:1;
1106                 uint64_t reserved_10_63:54;
1107 #endif
1108         } s;
1109         struct cvmx_sriox_mem_op_ctrl_s cn63xx;
1110         struct cvmx_sriox_mem_op_ctrl_s cn63xxp1;
1111         struct cvmx_sriox_mem_op_ctrl_s cn66xx;
1112 };
1113
1114 union cvmx_sriox_omsg_ctrlx {
1115         uint64_t u64;
1116         struct cvmx_sriox_omsg_ctrlx_s {
1117 #ifdef __BIG_ENDIAN_BITFIELD
1118                 uint64_t testmode:1;
1119                 uint64_t reserved_37_62:26;
1120                 uint64_t silo_max:5;
1121                 uint64_t rtry_thr:16;
1122                 uint64_t rtry_en:1;
1123                 uint64_t reserved_11_14:4;
1124                 uint64_t idm_tt:1;
1125                 uint64_t idm_sis:1;
1126                 uint64_t idm_did:1;
1127                 uint64_t lttr_sp:4;
1128                 uint64_t lttr_mp:4;
1129 #else
1130                 uint64_t lttr_mp:4;
1131                 uint64_t lttr_sp:4;
1132                 uint64_t idm_did:1;
1133                 uint64_t idm_sis:1;
1134                 uint64_t idm_tt:1;
1135                 uint64_t reserved_11_14:4;
1136                 uint64_t rtry_en:1;
1137                 uint64_t rtry_thr:16;
1138                 uint64_t silo_max:5;
1139                 uint64_t reserved_37_62:26;
1140                 uint64_t testmode:1;
1141 #endif
1142         } s;
1143         struct cvmx_sriox_omsg_ctrlx_s cn63xx;
1144         struct cvmx_sriox_omsg_ctrlx_cn63xxp1 {
1145 #ifdef __BIG_ENDIAN_BITFIELD
1146                 uint64_t testmode:1;
1147                 uint64_t reserved_32_62:31;
1148                 uint64_t rtry_thr:16;
1149                 uint64_t rtry_en:1;
1150                 uint64_t reserved_11_14:4;
1151                 uint64_t idm_tt:1;
1152                 uint64_t idm_sis:1;
1153                 uint64_t idm_did:1;
1154                 uint64_t lttr_sp:4;
1155                 uint64_t lttr_mp:4;
1156 #else
1157                 uint64_t lttr_mp:4;
1158                 uint64_t lttr_sp:4;
1159                 uint64_t idm_did:1;
1160                 uint64_t idm_sis:1;
1161                 uint64_t idm_tt:1;
1162                 uint64_t reserved_11_14:4;
1163                 uint64_t rtry_en:1;
1164                 uint64_t rtry_thr:16;
1165                 uint64_t reserved_32_62:31;
1166                 uint64_t testmode:1;
1167 #endif
1168         } cn63xxp1;
1169         struct cvmx_sriox_omsg_ctrlx_s cn66xx;
1170 };
1171
1172 union cvmx_sriox_omsg_done_countsx {
1173         uint64_t u64;
1174         struct cvmx_sriox_omsg_done_countsx_s {
1175 #ifdef __BIG_ENDIAN_BITFIELD
1176                 uint64_t reserved_32_63:32;
1177                 uint64_t bad:16;
1178                 uint64_t good:16;
1179 #else
1180                 uint64_t good:16;
1181                 uint64_t bad:16;
1182                 uint64_t reserved_32_63:32;
1183 #endif
1184         } s;
1185         struct cvmx_sriox_omsg_done_countsx_s cn63xx;
1186         struct cvmx_sriox_omsg_done_countsx_s cn66xx;
1187 };
1188
1189 union cvmx_sriox_omsg_fmp_mrx {
1190         uint64_t u64;
1191         struct cvmx_sriox_omsg_fmp_mrx_s {
1192 #ifdef __BIG_ENDIAN_BITFIELD
1193                 uint64_t reserved_15_63:49;
1194                 uint64_t ctlr_sp:1;
1195                 uint64_t ctlr_fmp:1;
1196                 uint64_t ctlr_nmp:1;
1197                 uint64_t id_sp:1;
1198                 uint64_t id_fmp:1;
1199                 uint64_t id_nmp:1;
1200                 uint64_t id_psd:1;
1201                 uint64_t mbox_sp:1;
1202                 uint64_t mbox_fmp:1;
1203                 uint64_t mbox_nmp:1;
1204                 uint64_t mbox_psd:1;
1205                 uint64_t all_sp:1;
1206                 uint64_t all_fmp:1;
1207                 uint64_t all_nmp:1;
1208                 uint64_t all_psd:1;
1209 #else
1210                 uint64_t all_psd:1;
1211                 uint64_t all_nmp:1;
1212                 uint64_t all_fmp:1;
1213                 uint64_t all_sp:1;
1214                 uint64_t mbox_psd:1;
1215                 uint64_t mbox_nmp:1;
1216                 uint64_t mbox_fmp:1;
1217                 uint64_t mbox_sp:1;
1218                 uint64_t id_psd:1;
1219                 uint64_t id_nmp:1;
1220                 uint64_t id_fmp:1;
1221                 uint64_t id_sp:1;
1222                 uint64_t ctlr_nmp:1;
1223                 uint64_t ctlr_fmp:1;
1224                 uint64_t ctlr_sp:1;
1225                 uint64_t reserved_15_63:49;
1226 #endif
1227         } s;
1228         struct cvmx_sriox_omsg_fmp_mrx_s cn63xx;
1229         struct cvmx_sriox_omsg_fmp_mrx_s cn63xxp1;
1230         struct cvmx_sriox_omsg_fmp_mrx_s cn66xx;
1231 };
1232
1233 union cvmx_sriox_omsg_nmp_mrx {
1234         uint64_t u64;
1235         struct cvmx_sriox_omsg_nmp_mrx_s {
1236 #ifdef __BIG_ENDIAN_BITFIELD
1237                 uint64_t reserved_15_63:49;
1238                 uint64_t ctlr_sp:1;
1239                 uint64_t ctlr_fmp:1;
1240                 uint64_t ctlr_nmp:1;
1241                 uint64_t id_sp:1;
1242                 uint64_t id_fmp:1;
1243                 uint64_t id_nmp:1;
1244                 uint64_t reserved_8_8:1;
1245                 uint64_t mbox_sp:1;
1246                 uint64_t mbox_fmp:1;
1247                 uint64_t mbox_nmp:1;
1248                 uint64_t reserved_4_4:1;
1249                 uint64_t all_sp:1;
1250                 uint64_t all_fmp:1;
1251                 uint64_t all_nmp:1;
1252                 uint64_t reserved_0_0:1;
1253 #else
1254                 uint64_t reserved_0_0:1;
1255                 uint64_t all_nmp:1;
1256                 uint64_t all_fmp:1;
1257                 uint64_t all_sp:1;
1258                 uint64_t reserved_4_4:1;
1259                 uint64_t mbox_nmp:1;
1260                 uint64_t mbox_fmp:1;
1261                 uint64_t mbox_sp:1;
1262                 uint64_t reserved_8_8:1;
1263                 uint64_t id_nmp:1;
1264                 uint64_t id_fmp:1;
1265                 uint64_t id_sp:1;
1266                 uint64_t ctlr_nmp:1;
1267                 uint64_t ctlr_fmp:1;
1268                 uint64_t ctlr_sp:1;
1269                 uint64_t reserved_15_63:49;
1270 #endif
1271         } s;
1272         struct cvmx_sriox_omsg_nmp_mrx_s cn63xx;
1273         struct cvmx_sriox_omsg_nmp_mrx_s cn63xxp1;
1274         struct cvmx_sriox_omsg_nmp_mrx_s cn66xx;
1275 };
1276
1277 union cvmx_sriox_omsg_portx {
1278         uint64_t u64;
1279         struct cvmx_sriox_omsg_portx_s {
1280 #ifdef __BIG_ENDIAN_BITFIELD
1281                 uint64_t reserved_32_63:32;
1282                 uint64_t enable:1;
1283                 uint64_t reserved_3_30:28;
1284                 uint64_t port:3;
1285 #else
1286                 uint64_t port:3;
1287                 uint64_t reserved_3_30:28;
1288                 uint64_t enable:1;
1289                 uint64_t reserved_32_63:32;
1290 #endif
1291         } s;
1292         struct cvmx_sriox_omsg_portx_cn63xx {
1293 #ifdef __BIG_ENDIAN_BITFIELD
1294                 uint64_t reserved_32_63:32;
1295                 uint64_t enable:1;
1296                 uint64_t reserved_2_30:29;
1297                 uint64_t port:2;
1298 #else
1299                 uint64_t port:2;
1300                 uint64_t reserved_2_30:29;
1301                 uint64_t enable:1;
1302                 uint64_t reserved_32_63:32;
1303 #endif
1304         } cn63xx;
1305         struct cvmx_sriox_omsg_portx_cn63xx cn63xxp1;
1306         struct cvmx_sriox_omsg_portx_s cn66xx;
1307 };
1308
1309 union cvmx_sriox_omsg_silo_thr {
1310         uint64_t u64;
1311         struct cvmx_sriox_omsg_silo_thr_s {
1312 #ifdef __BIG_ENDIAN_BITFIELD
1313                 uint64_t reserved_5_63:59;
1314                 uint64_t tot_silo:5;
1315 #else
1316                 uint64_t tot_silo:5;
1317                 uint64_t reserved_5_63:59;
1318 #endif
1319         } s;
1320         struct cvmx_sriox_omsg_silo_thr_s cn63xx;
1321         struct cvmx_sriox_omsg_silo_thr_s cn66xx;
1322 };
1323
1324 union cvmx_sriox_omsg_sp_mrx {
1325         uint64_t u64;
1326         struct cvmx_sriox_omsg_sp_mrx_s {
1327 #ifdef __BIG_ENDIAN_BITFIELD
1328                 uint64_t reserved_16_63:48;
1329                 uint64_t xmbox_sp:1;
1330                 uint64_t ctlr_sp:1;
1331                 uint64_t ctlr_fmp:1;
1332                 uint64_t ctlr_nmp:1;
1333                 uint64_t id_sp:1;
1334                 uint64_t id_fmp:1;
1335                 uint64_t id_nmp:1;
1336                 uint64_t id_psd:1;
1337                 uint64_t mbox_sp:1;
1338                 uint64_t mbox_fmp:1;
1339                 uint64_t mbox_nmp:1;
1340                 uint64_t mbox_psd:1;
1341                 uint64_t all_sp:1;
1342                 uint64_t all_fmp:1;
1343                 uint64_t all_nmp:1;
1344                 uint64_t all_psd:1;
1345 #else
1346                 uint64_t all_psd:1;
1347                 uint64_t all_nmp:1;
1348                 uint64_t all_fmp:1;
1349                 uint64_t all_sp:1;
1350                 uint64_t mbox_psd:1;
1351                 uint64_t mbox_nmp:1;
1352                 uint64_t mbox_fmp:1;
1353                 uint64_t mbox_sp:1;
1354                 uint64_t id_psd:1;
1355                 uint64_t id_nmp:1;
1356                 uint64_t id_fmp:1;
1357                 uint64_t id_sp:1;
1358                 uint64_t ctlr_nmp:1;
1359                 uint64_t ctlr_fmp:1;
1360                 uint64_t ctlr_sp:1;
1361                 uint64_t xmbox_sp:1;
1362                 uint64_t reserved_16_63:48;
1363 #endif
1364         } s;
1365         struct cvmx_sriox_omsg_sp_mrx_s cn63xx;
1366         struct cvmx_sriox_omsg_sp_mrx_s cn63xxp1;
1367         struct cvmx_sriox_omsg_sp_mrx_s cn66xx;
1368 };
1369
1370 union cvmx_sriox_priox_in_use {
1371         uint64_t u64;
1372         struct cvmx_sriox_priox_in_use_s {
1373 #ifdef __BIG_ENDIAN_BITFIELD
1374                 uint64_t reserved_32_63:32;
1375                 uint64_t end_cnt:16;
1376                 uint64_t start_cnt:16;
1377 #else
1378                 uint64_t start_cnt:16;
1379                 uint64_t end_cnt:16;
1380                 uint64_t reserved_32_63:32;
1381 #endif
1382         } s;
1383         struct cvmx_sriox_priox_in_use_s cn63xx;
1384         struct cvmx_sriox_priox_in_use_s cn66xx;
1385 };
1386
1387 union cvmx_sriox_rx_bell {
1388         uint64_t u64;
1389         struct cvmx_sriox_rx_bell_s {
1390 #ifdef __BIG_ENDIAN_BITFIELD
1391                 uint64_t reserved_48_63:16;
1392                 uint64_t data:16;
1393                 uint64_t src_id:16;
1394                 uint64_t count:8;
1395                 uint64_t reserved_5_7:3;
1396                 uint64_t dest_id:1;
1397                 uint64_t id16:1;
1398                 uint64_t reserved_2_2:1;
1399                 uint64_t priority:2;
1400 #else
1401                 uint64_t priority:2;
1402                 uint64_t reserved_2_2:1;
1403                 uint64_t id16:1;
1404                 uint64_t dest_id:1;
1405                 uint64_t reserved_5_7:3;
1406                 uint64_t count:8;
1407                 uint64_t src_id:16;
1408                 uint64_t data:16;
1409                 uint64_t reserved_48_63:16;
1410 #endif
1411         } s;
1412         struct cvmx_sriox_rx_bell_s cn63xx;
1413         struct cvmx_sriox_rx_bell_s cn63xxp1;
1414         struct cvmx_sriox_rx_bell_s cn66xx;
1415 };
1416
1417 union cvmx_sriox_rx_bell_seq {
1418         uint64_t u64;
1419         struct cvmx_sriox_rx_bell_seq_s {
1420 #ifdef __BIG_ENDIAN_BITFIELD
1421                 uint64_t reserved_40_63:24;
1422                 uint64_t count:8;
1423                 uint64_t seq:32;
1424 #else
1425                 uint64_t seq:32;
1426                 uint64_t count:8;
1427                 uint64_t reserved_40_63:24;
1428 #endif
1429         } s;
1430         struct cvmx_sriox_rx_bell_seq_s cn63xx;
1431         struct cvmx_sriox_rx_bell_seq_s cn63xxp1;
1432         struct cvmx_sriox_rx_bell_seq_s cn66xx;
1433 };
1434
1435 union cvmx_sriox_rx_status {
1436         uint64_t u64;
1437         struct cvmx_sriox_rx_status_s {
1438 #ifdef __BIG_ENDIAN_BITFIELD
1439                 uint64_t rtn_pr3:8;
1440                 uint64_t rtn_pr2:8;
1441                 uint64_t rtn_pr1:8;
1442                 uint64_t reserved_28_39:12;
1443                 uint64_t mbox:4;
1444                 uint64_t comp:8;
1445                 uint64_t reserved_13_15:3;
1446                 uint64_t n_post:5;
1447                 uint64_t post:8;
1448 #else
1449                 uint64_t post:8;
1450                 uint64_t n_post:5;
1451                 uint64_t reserved_13_15:3;
1452                 uint64_t comp:8;
1453                 uint64_t mbox:4;
1454                 uint64_t reserved_28_39:12;
1455                 uint64_t rtn_pr1:8;
1456                 uint64_t rtn_pr2:8;
1457                 uint64_t rtn_pr3:8;
1458 #endif
1459         } s;
1460         struct cvmx_sriox_rx_status_s cn63xx;
1461         struct cvmx_sriox_rx_status_s cn63xxp1;
1462         struct cvmx_sriox_rx_status_s cn66xx;
1463 };
1464
1465 union cvmx_sriox_s2m_typex {
1466         uint64_t u64;
1467         struct cvmx_sriox_s2m_typex_s {
1468 #ifdef __BIG_ENDIAN_BITFIELD
1469                 uint64_t reserved_19_63:45;
1470                 uint64_t wr_op:3;
1471                 uint64_t reserved_15_15:1;
1472                 uint64_t rd_op:3;
1473                 uint64_t wr_prior:2;
1474                 uint64_t rd_prior:2;
1475                 uint64_t reserved_6_7:2;
1476                 uint64_t src_id:1;
1477                 uint64_t id16:1;
1478                 uint64_t reserved_2_3:2;
1479                 uint64_t iaow_sel:2;
1480 #else
1481                 uint64_t iaow_sel:2;
1482                 uint64_t reserved_2_3:2;
1483                 uint64_t id16:1;
1484                 uint64_t src_id:1;
1485                 uint64_t reserved_6_7:2;
1486                 uint64_t rd_prior:2;
1487                 uint64_t wr_prior:2;
1488                 uint64_t rd_op:3;
1489                 uint64_t reserved_15_15:1;
1490                 uint64_t wr_op:3;
1491                 uint64_t reserved_19_63:45;
1492 #endif
1493         } s;
1494         struct cvmx_sriox_s2m_typex_s cn63xx;
1495         struct cvmx_sriox_s2m_typex_s cn63xxp1;
1496         struct cvmx_sriox_s2m_typex_s cn66xx;
1497 };
1498
1499 union cvmx_sriox_seq {
1500         uint64_t u64;
1501         struct cvmx_sriox_seq_s {
1502 #ifdef __BIG_ENDIAN_BITFIELD
1503                 uint64_t reserved_32_63:32;
1504                 uint64_t seq:32;
1505 #else
1506                 uint64_t seq:32;
1507                 uint64_t reserved_32_63:32;
1508 #endif
1509         } s;
1510         struct cvmx_sriox_seq_s cn63xx;
1511         struct cvmx_sriox_seq_s cn63xxp1;
1512         struct cvmx_sriox_seq_s cn66xx;
1513 };
1514
1515 union cvmx_sriox_status_reg {
1516         uint64_t u64;
1517         struct cvmx_sriox_status_reg_s {
1518 #ifdef __BIG_ENDIAN_BITFIELD
1519                 uint64_t reserved_2_63:62;
1520                 uint64_t access:1;
1521                 uint64_t srio:1;
1522 #else
1523                 uint64_t srio:1;
1524                 uint64_t access:1;
1525                 uint64_t reserved_2_63:62;
1526 #endif
1527         } s;
1528         struct cvmx_sriox_status_reg_s cn63xx;
1529         struct cvmx_sriox_status_reg_s cn63xxp1;
1530         struct cvmx_sriox_status_reg_s cn66xx;
1531 };
1532
1533 union cvmx_sriox_tag_ctrl {
1534         uint64_t u64;
1535         struct cvmx_sriox_tag_ctrl_s {
1536 #ifdef __BIG_ENDIAN_BITFIELD
1537                 uint64_t reserved_17_63:47;
1538                 uint64_t o_clr:1;
1539                 uint64_t reserved_13_15:3;
1540                 uint64_t otag:5;
1541                 uint64_t reserved_5_7:3;
1542                 uint64_t itag:5;
1543 #else
1544                 uint64_t itag:5;
1545                 uint64_t reserved_5_7:3;
1546                 uint64_t otag:5;
1547                 uint64_t reserved_13_15:3;
1548                 uint64_t o_clr:1;
1549                 uint64_t reserved_17_63:47;
1550 #endif
1551         } s;
1552         struct cvmx_sriox_tag_ctrl_s cn63xx;
1553         struct cvmx_sriox_tag_ctrl_s cn63xxp1;
1554         struct cvmx_sriox_tag_ctrl_s cn66xx;
1555 };
1556
1557 union cvmx_sriox_tlp_credits {
1558         uint64_t u64;
1559         struct cvmx_sriox_tlp_credits_s {
1560 #ifdef __BIG_ENDIAN_BITFIELD
1561                 uint64_t reserved_28_63:36;
1562                 uint64_t mbox:4;
1563                 uint64_t comp:8;
1564                 uint64_t reserved_13_15:3;
1565                 uint64_t n_post:5;
1566                 uint64_t post:8;
1567 #else
1568                 uint64_t post:8;
1569                 uint64_t n_post:5;
1570                 uint64_t reserved_13_15:3;
1571                 uint64_t comp:8;
1572                 uint64_t mbox:4;
1573                 uint64_t reserved_28_63:36;
1574 #endif
1575         } s;
1576         struct cvmx_sriox_tlp_credits_s cn63xx;
1577         struct cvmx_sriox_tlp_credits_s cn63xxp1;
1578         struct cvmx_sriox_tlp_credits_s cn66xx;
1579 };
1580
1581 union cvmx_sriox_tx_bell {
1582         uint64_t u64;
1583         struct cvmx_sriox_tx_bell_s {
1584 #ifdef __BIG_ENDIAN_BITFIELD
1585                 uint64_t reserved_48_63:16;
1586                 uint64_t data:16;
1587                 uint64_t dest_id:16;
1588                 uint64_t reserved_9_15:7;
1589                 uint64_t pending:1;
1590                 uint64_t reserved_5_7:3;
1591                 uint64_t src_id:1;
1592                 uint64_t id16:1;
1593                 uint64_t reserved_2_2:1;
1594                 uint64_t priority:2;
1595 #else
1596                 uint64_t priority:2;
1597                 uint64_t reserved_2_2:1;
1598                 uint64_t id16:1;
1599                 uint64_t src_id:1;
1600                 uint64_t reserved_5_7:3;
1601                 uint64_t pending:1;
1602                 uint64_t reserved_9_15:7;
1603                 uint64_t dest_id:16;
1604                 uint64_t data:16;
1605                 uint64_t reserved_48_63:16;
1606 #endif
1607         } s;
1608         struct cvmx_sriox_tx_bell_s cn63xx;
1609         struct cvmx_sriox_tx_bell_s cn63xxp1;
1610         struct cvmx_sriox_tx_bell_s cn66xx;
1611 };
1612
1613 union cvmx_sriox_tx_bell_info {
1614         uint64_t u64;
1615         struct cvmx_sriox_tx_bell_info_s {
1616 #ifdef __BIG_ENDIAN_BITFIELD
1617                 uint64_t reserved_48_63:16;
1618                 uint64_t data:16;
1619                 uint64_t dest_id:16;
1620                 uint64_t reserved_8_15:8;
1621                 uint64_t timeout:1;
1622                 uint64_t error:1;
1623                 uint64_t retry:1;
1624                 uint64_t src_id:1;
1625                 uint64_t id16:1;
1626                 uint64_t reserved_2_2:1;
1627                 uint64_t priority:2;
1628 #else
1629                 uint64_t priority:2;
1630                 uint64_t reserved_2_2:1;
1631                 uint64_t id16:1;
1632                 uint64_t src_id:1;
1633                 uint64_t retry:1;
1634                 uint64_t error:1;
1635                 uint64_t timeout:1;
1636                 uint64_t reserved_8_15:8;
1637                 uint64_t dest_id:16;
1638                 uint64_t data:16;
1639                 uint64_t reserved_48_63:16;
1640 #endif
1641         } s;
1642         struct cvmx_sriox_tx_bell_info_s cn63xx;
1643         struct cvmx_sriox_tx_bell_info_s cn63xxp1;
1644         struct cvmx_sriox_tx_bell_info_s cn66xx;
1645 };
1646
1647 union cvmx_sriox_tx_ctrl {
1648         uint64_t u64;
1649         struct cvmx_sriox_tx_ctrl_s {
1650 #ifdef __BIG_ENDIAN_BITFIELD
1651                 uint64_t reserved_53_63:11;
1652                 uint64_t tag_th2:5;
1653                 uint64_t reserved_45_47:3;
1654                 uint64_t tag_th1:5;
1655                 uint64_t reserved_37_39:3;
1656                 uint64_t tag_th0:5;
1657                 uint64_t reserved_20_31:12;
1658                 uint64_t tx_th2:4;
1659                 uint64_t reserved_12_15:4;
1660                 uint64_t tx_th1:4;
1661                 uint64_t reserved_4_7:4;
1662                 uint64_t tx_th0:4;
1663 #else
1664                 uint64_t tx_th0:4;
1665                 uint64_t reserved_4_7:4;
1666                 uint64_t tx_th1:4;
1667                 uint64_t reserved_12_15:4;
1668                 uint64_t tx_th2:4;
1669                 uint64_t reserved_20_31:12;
1670                 uint64_t tag_th0:5;
1671                 uint64_t reserved_37_39:3;
1672                 uint64_t tag_th1:5;
1673                 uint64_t reserved_45_47:3;
1674                 uint64_t tag_th2:5;
1675                 uint64_t reserved_53_63:11;
1676 #endif
1677         } s;
1678         struct cvmx_sriox_tx_ctrl_s cn63xx;
1679         struct cvmx_sriox_tx_ctrl_s cn63xxp1;
1680         struct cvmx_sriox_tx_ctrl_s cn66xx;
1681 };
1682
1683 union cvmx_sriox_tx_emphasis {
1684         uint64_t u64;
1685         struct cvmx_sriox_tx_emphasis_s {
1686 #ifdef __BIG_ENDIAN_BITFIELD
1687                 uint64_t reserved_4_63:60;
1688                 uint64_t emph:4;
1689 #else
1690                 uint64_t emph:4;
1691                 uint64_t reserved_4_63:60;
1692 #endif
1693         } s;
1694         struct cvmx_sriox_tx_emphasis_s cn63xx;
1695         struct cvmx_sriox_tx_emphasis_s cn66xx;
1696 };
1697
1698 union cvmx_sriox_tx_status {
1699         uint64_t u64;
1700         struct cvmx_sriox_tx_status_s {
1701 #ifdef __BIG_ENDIAN_BITFIELD
1702                 uint64_t reserved_32_63:32;
1703                 uint64_t s2m_pr3:8;
1704                 uint64_t s2m_pr2:8;
1705                 uint64_t s2m_pr1:8;
1706                 uint64_t s2m_pr0:8;
1707 #else
1708                 uint64_t s2m_pr0:8;
1709                 uint64_t s2m_pr1:8;
1710                 uint64_t s2m_pr2:8;
1711                 uint64_t s2m_pr3:8;
1712                 uint64_t reserved_32_63:32;
1713 #endif
1714         } s;
1715         struct cvmx_sriox_tx_status_s cn63xx;
1716         struct cvmx_sriox_tx_status_s cn63xxp1;
1717         struct cvmx_sriox_tx_status_s cn66xx;
1718 };
1719
1720 union cvmx_sriox_wr_done_counts {
1721         uint64_t u64;
1722         struct cvmx_sriox_wr_done_counts_s {
1723 #ifdef __BIG_ENDIAN_BITFIELD
1724                 uint64_t reserved_32_63:32;
1725                 uint64_t bad:16;
1726                 uint64_t good:16;
1727 #else
1728                 uint64_t good:16;
1729                 uint64_t bad:16;
1730                 uint64_t reserved_32_63:32;
1731 #endif
1732         } s;
1733         struct cvmx_sriox_wr_done_counts_s cn63xx;
1734         struct cvmx_sriox_wr_done_counts_s cn66xx;
1735 };
1736
1737 #endif