kernel/arch/mips/include/asm/octeon/cvmx-pow-defs.h

   1 /***********************license start***************
   2  * Author: Cavium Networks
   3  *
   4  * Contact: support@caviumnetworks.com
   5  * This file is part of the OCTEON SDK
   6  *
   7  * Copyright (c) 2003-2012 Cavium Networks
   8  *
   9  * This file is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License, Version 2, as
  11  * published by the Free Software Foundation.
  12  *
  13  * This file is distributed in the hope that it will be useful, but
  14  * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
  15  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
  16  * NONINFRINGEMENT.  See the GNU General Public License for more
  17  * details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this file; if not, write to the Free Software
  21  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  22  * or visit http://www.gnu.org/licenses/.
  23  *
  24  * This file may also be available under a different license from Cavium.
  25  * Contact Cavium Networks for more information
  26  ***********************license end**************************************/
  27
  28 #ifndef __CVMX_POW_DEFS_H__
  29 #define __CVMX_POW_DEFS_H__
  30
  31 #define CVMX_POW_BIST_STAT (CVMX_ADD_IO_SEG(0x00016700000003F8ull))
  32 #define CVMX_POW_DS_PC (CVMX_ADD_IO_SEG(0x0001670000000398ull))
  33 #define CVMX_POW_ECC_ERR (CVMX_ADD_IO_SEG(0x0001670000000218ull))
  34 #define CVMX_POW_INT_CTL (CVMX_ADD_IO_SEG(0x0001670000000220ull))
  35 #define CVMX_POW_IQ_CNTX(offset) (CVMX_ADD_IO_SEG(0x0001670000000340ull) + ((offset) & 7) * 8)
  36 #define CVMX_POW_IQ_COM_CNT (CVMX_ADD_IO_SEG(0x0001670000000388ull))
  37 #define CVMX_POW_IQ_INT (CVMX_ADD_IO_SEG(0x0001670000000238ull))
  38 #define CVMX_POW_IQ_INT_EN (CVMX_ADD_IO_SEG(0x0001670000000240ull))
  39 #define CVMX_POW_IQ_THRX(offset) (CVMX_ADD_IO_SEG(0x00016700000003A0ull) + ((offset) & 7) * 8)
  40 #define CVMX_POW_NOS_CNT (CVMX_ADD_IO_SEG(0x0001670000000228ull))
  41 #define CVMX_POW_NW_TIM (CVMX_ADD_IO_SEG(0x0001670000000210ull))
  42 #define CVMX_POW_PF_RST_MSK (CVMX_ADD_IO_SEG(0x0001670000000230ull))
  43 #define CVMX_POW_PP_GRP_MSKX(offset) (CVMX_ADD_IO_SEG(0x0001670000000000ull) + ((offset) & 15) * 8)
  44 #define CVMX_POW_QOS_RNDX(offset) (CVMX_ADD_IO_SEG(0x00016700000001C0ull) + ((offset) & 7) * 8)
  45 #define CVMX_POW_QOS_THRX(offset) (CVMX_ADD_IO_SEG(0x0001670000000180ull) + ((offset) & 7) * 8)
  46 #define CVMX_POW_TS_PC (CVMX_ADD_IO_SEG(0x0001670000000390ull))
  47 #define CVMX_POW_WA_COM_PC (CVMX_ADD_IO_SEG(0x0001670000000380ull))
  48 #define CVMX_POW_WA_PCX(offset) (CVMX_ADD_IO_SEG(0x0001670000000300ull) + ((offset) & 7) * 8)
  49 #define CVMX_POW_WQ_INT (CVMX_ADD_IO_SEG(0x0001670000000200ull))
  50 #define CVMX_POW_WQ_INT_CNTX(offset) (CVMX_ADD_IO_SEG(0x0001670000000100ull) + ((offset) & 15) * 8)
  51 #define CVMX_POW_WQ_INT_PC (CVMX_ADD_IO_SEG(0x0001670000000208ull))
  52 #define CVMX_POW_WQ_INT_THRX(offset) (CVMX_ADD_IO_SEG(0x0001670000000080ull) + ((offset) & 15) * 8)
  53 #define CVMX_POW_WS_PCX(offset) (CVMX_ADD_IO_SEG(0x0001670000000280ull) + ((offset) & 15) * 8)
  54
  55 union cvmx_pow_bist_stat {
  56         uint64_t u64;
  57         struct cvmx_pow_bist_stat_s {
  58 #ifdef __BIG_ENDIAN_BITFIELD
  59                 uint64_t reserved_32_63:32;
  60                 uint64_t pp:16;
  61                 uint64_t reserved_0_15:16;
  62 #else
  63                 uint64_t reserved_0_15:16;
  64                 uint64_t pp:16;
  65                 uint64_t reserved_32_63:32;
  66 #endif
  67         } s;
  68         struct cvmx_pow_bist_stat_cn30xx {
  69 #ifdef __BIG_ENDIAN_BITFIELD
  70                 uint64_t reserved_17_63:47;
  71                 uint64_t pp:1;
  72                 uint64_t reserved_9_15:7;
  73                 uint64_t cam:1;
  74                 uint64_t nbt1:1;
  75                 uint64_t nbt0:1;
  76                 uint64_t index:1;
  77                 uint64_t fidx:1;
  78                 uint64_t nbr1:1;
  79                 uint64_t nbr0:1;
  80                 uint64_t pend:1;
  81                 uint64_t adr:1;
  82 #else
  83                 uint64_t adr:1;
  84                 uint64_t pend:1;
  85                 uint64_t nbr0:1;
  86                 uint64_t nbr1:1;
  87                 uint64_t fidx:1;
  88                 uint64_t index:1;
  89                 uint64_t nbt0:1;
  90                 uint64_t nbt1:1;
  91                 uint64_t cam:1;
  92                 uint64_t reserved_9_15:7;
  93                 uint64_t pp:1;
  94                 uint64_t reserved_17_63:47;
  95 #endif
  96         } cn30xx;
  97         struct cvmx_pow_bist_stat_cn31xx {
  98 #ifdef __BIG_ENDIAN_BITFIELD
  99                 uint64_t reserved_18_63:46;
 100                 uint64_t pp:2;
 101                 uint64_t reserved_9_15:7;
 102                 uint64_t cam:1;
 103                 uint64_t nbt1:1;
 104                 uint64_t nbt0:1;
 105                 uint64_t index:1;
 106                 uint64_t fidx:1;
 107                 uint64_t nbr1:1;
 108                 uint64_t nbr0:1;
 109                 uint64_t pend:1;
 110                 uint64_t adr:1;
 111 #else
 112                 uint64_t adr:1;
 113                 uint64_t pend:1;
 114                 uint64_t nbr0:1;
 115                 uint64_t nbr1:1;
 116                 uint64_t fidx:1;
 117                 uint64_t index:1;
 118                 uint64_t nbt0:1;
 119                 uint64_t nbt1:1;
 120                 uint64_t cam:1;
 121                 uint64_t reserved_9_15:7;
 122                 uint64_t pp:2;
 123                 uint64_t reserved_18_63:46;
 124 #endif
 125         } cn31xx;
 126         struct cvmx_pow_bist_stat_cn38xx {
 127 #ifdef __BIG_ENDIAN_BITFIELD
 128                 uint64_t reserved_32_63:32;
 129                 uint64_t pp:16;
 130                 uint64_t reserved_10_15:6;
 131                 uint64_t cam:1;
 132                 uint64_t nbt:1;
 133                 uint64_t index:1;
 134                 uint64_t fidx:1;
 135                 uint64_t nbr1:1;
 136                 uint64_t nbr0:1;
 137                 uint64_t pend1:1;
 138                 uint64_t pend0:1;
 139                 uint64_t adr1:1;
 140                 uint64_t adr0:1;
 141 #else
 142                 uint64_t adr0:1;
 143                 uint64_t adr1:1;
 144                 uint64_t pend0:1;
 145                 uint64_t pend1:1;
 146                 uint64_t nbr0:1;
 147                 uint64_t nbr1:1;
 148                 uint64_t fidx:1;
 149                 uint64_t index:1;
 150                 uint64_t nbt:1;
 151                 uint64_t cam:1;
 152                 uint64_t reserved_10_15:6;
 153                 uint64_t pp:16;
 154                 uint64_t reserved_32_63:32;
 155 #endif
 156         } cn38xx;
 157         struct cvmx_pow_bist_stat_cn38xx cn38xxp2;
 158         struct cvmx_pow_bist_stat_cn31xx cn50xx;
 159         struct cvmx_pow_bist_stat_cn52xx {
 160 #ifdef __BIG_ENDIAN_BITFIELD
 161                 uint64_t reserved_20_63:44;
 162                 uint64_t pp:4;
 163                 uint64_t reserved_9_15:7;
 164                 uint64_t cam:1;
 165                 uint64_t nbt1:1;
 166                 uint64_t nbt0:1;
 167                 uint64_t index:1;
 168                 uint64_t fidx:1;
 169                 uint64_t nbr1:1;
 170                 uint64_t nbr0:1;
 171                 uint64_t pend:1;
 172                 uint64_t adr:1;
 173 #else
 174                 uint64_t adr:1;
 175                 uint64_t pend:1;
 176                 uint64_t nbr0:1;
 177                 uint64_t nbr1:1;
 178                 uint64_t fidx:1;
 179                 uint64_t index:1;
 180                 uint64_t nbt0:1;
 181                 uint64_t nbt1:1;
 182                 uint64_t cam:1;
 183                 uint64_t reserved_9_15:7;
 184                 uint64_t pp:4;
 185                 uint64_t reserved_20_63:44;
 186 #endif
 187         } cn52xx;
 188         struct cvmx_pow_bist_stat_cn52xx cn52xxp1;
 189         struct cvmx_pow_bist_stat_cn56xx {
 190 #ifdef __BIG_ENDIAN_BITFIELD
 191                 uint64_t reserved_28_63:36;
 192                 uint64_t pp:12;
 193                 uint64_t reserved_10_15:6;
 194                 uint64_t cam:1;
 195                 uint64_t nbt:1;
 196                 uint64_t index:1;
 197                 uint64_t fidx:1;
 198                 uint64_t nbr1:1;
 199                 uint64_t nbr0:1;
 200                 uint64_t pend1:1;
 201                 uint64_t pend0:1;
 202                 uint64_t adr1:1;
 203                 uint64_t adr0:1;
 204 #else
 205                 uint64_t adr0:1;
 206                 uint64_t adr1:1;
 207                 uint64_t pend0:1;
 208                 uint64_t pend1:1;
 209                 uint64_t nbr0:1;
 210                 uint64_t nbr1:1;
 211                 uint64_t fidx:1;
 212                 uint64_t index:1;
 213                 uint64_t nbt:1;
 214                 uint64_t cam:1;
 215                 uint64_t reserved_10_15:6;
 216                 uint64_t pp:12;
 217                 uint64_t reserved_28_63:36;
 218 #endif
 219         } cn56xx;
 220         struct cvmx_pow_bist_stat_cn56xx cn56xxp1;
 221         struct cvmx_pow_bist_stat_cn38xx cn58xx;
 222         struct cvmx_pow_bist_stat_cn38xx cn58xxp1;
 223         struct cvmx_pow_bist_stat_cn61xx {
 224 #ifdef __BIG_ENDIAN_BITFIELD
 225                 uint64_t reserved_20_63:44;
 226                 uint64_t pp:4;
 227                 uint64_t reserved_12_15:4;
 228                 uint64_t cam:1;
 229                 uint64_t nbr:3;
 230                 uint64_t nbt:4;
 231                 uint64_t index:1;
 232                 uint64_t fidx:1;
 233                 uint64_t pend:1;
 234                 uint64_t adr:1;
 235 #else
 236                 uint64_t adr:1;
 237                 uint64_t pend:1;
 238                 uint64_t fidx:1;
 239                 uint64_t index:1;
 240                 uint64_t nbt:4;
 241                 uint64_t nbr:3;
 242                 uint64_t cam:1;
 243                 uint64_t reserved_12_15:4;
 244                 uint64_t pp:4;
 245                 uint64_t reserved_20_63:44;
 246 #endif
 247         } cn61xx;
 248         struct cvmx_pow_bist_stat_cn63xx {
 249 #ifdef __BIG_ENDIAN_BITFIELD
 250                 uint64_t reserved_22_63:42;
 251                 uint64_t pp:6;
 252                 uint64_t reserved_12_15:4;
 253                 uint64_t cam:1;
 254                 uint64_t nbr:3;
 255                 uint64_t nbt:4;
 256                 uint64_t index:1;
 257                 uint64_t fidx:1;
 258                 uint64_t pend:1;
 259                 uint64_t adr:1;
 260 #else
 261                 uint64_t adr:1;
 262                 uint64_t pend:1;
 263                 uint64_t fidx:1;
 264                 uint64_t index:1;
 265                 uint64_t nbt:4;
 266                 uint64_t nbr:3;
 267                 uint64_t cam:1;
 268                 uint64_t reserved_12_15:4;
 269                 uint64_t pp:6;
 270                 uint64_t reserved_22_63:42;
 271 #endif
 272         } cn63xx;
 273         struct cvmx_pow_bist_stat_cn63xx cn63xxp1;
 274         struct cvmx_pow_bist_stat_cn66xx {
 275 #ifdef __BIG_ENDIAN_BITFIELD
 276                 uint64_t reserved_26_63:38;
 277                 uint64_t pp:10;
 278                 uint64_t reserved_12_15:4;
 279                 uint64_t cam:1;
 280                 uint64_t nbr:3;
 281                 uint64_t nbt:4;
 282                 uint64_t index:1;
 283                 uint64_t fidx:1;
 284                 uint64_t pend:1;
 285                 uint64_t adr:1;
 286 #else
 287                 uint64_t adr:1;
 288                 uint64_t pend:1;
 289                 uint64_t fidx:1;
 290                 uint64_t index:1;
 291                 uint64_t nbt:4;
 292                 uint64_t nbr:3;
 293                 uint64_t cam:1;
 294                 uint64_t reserved_12_15:4;
 295                 uint64_t pp:10;
 296                 uint64_t reserved_26_63:38;
 297 #endif
 298         } cn66xx;
 299         struct cvmx_pow_bist_stat_cn61xx cnf71xx;
 300 };
 301
 302 union cvmx_pow_ds_pc {
 303         uint64_t u64;
 304         struct cvmx_pow_ds_pc_s {
 305 #ifdef __BIG_ENDIAN_BITFIELD
 306                 uint64_t reserved_32_63:32;
 307                 uint64_t ds_pc:32;
 308 #else
 309                 uint64_t ds_pc:32;
 310                 uint64_t reserved_32_63:32;
 311 #endif
 312         } s;
 313         struct cvmx_pow_ds_pc_s cn30xx;
 314         struct cvmx_pow_ds_pc_s cn31xx;
 315         struct cvmx_pow_ds_pc_s cn38xx;
 316         struct cvmx_pow_ds_pc_s cn38xxp2;
 317         struct cvmx_pow_ds_pc_s cn50xx;
 318         struct cvmx_pow_ds_pc_s cn52xx;
 319         struct cvmx_pow_ds_pc_s cn52xxp1;
 320         struct cvmx_pow_ds_pc_s cn56xx;
 321         struct cvmx_pow_ds_pc_s cn56xxp1;
 322         struct cvmx_pow_ds_pc_s cn58xx;
 323         struct cvmx_pow_ds_pc_s cn58xxp1;
 324         struct cvmx_pow_ds_pc_s cn61xx;
 325         struct cvmx_pow_ds_pc_s cn63xx;
 326         struct cvmx_pow_ds_pc_s cn63xxp1;
 327         struct cvmx_pow_ds_pc_s cn66xx;
 328         struct cvmx_pow_ds_pc_s cnf71xx;
 329 };
 330
 331 union cvmx_pow_ecc_err {
 332         uint64_t u64;
 333         struct cvmx_pow_ecc_err_s {
 334 #ifdef __BIG_ENDIAN_BITFIELD
 335                 uint64_t reserved_45_63:19;
 336                 uint64_t iop_ie:13;
 337                 uint64_t reserved_29_31:3;
 338                 uint64_t iop:13;
 339                 uint64_t reserved_14_15:2;
 340                 uint64_t rpe_ie:1;
 341                 uint64_t rpe:1;
 342                 uint64_t reserved_9_11:3;
 343                 uint64_t syn:5;
 344                 uint64_t dbe_ie:1;
 345                 uint64_t sbe_ie:1;
 346                 uint64_t dbe:1;
 347                 uint64_t sbe:1;
 348 #else
 349                 uint64_t sbe:1;
 350                 uint64_t dbe:1;
 351                 uint64_t sbe_ie:1;
 352                 uint64_t dbe_ie:1;
 353                 uint64_t syn:5;
 354                 uint64_t reserved_9_11:3;
 355                 uint64_t rpe:1;
 356                 uint64_t rpe_ie:1;
 357                 uint64_t reserved_14_15:2;
 358                 uint64_t iop:13;
 359                 uint64_t reserved_29_31:3;
 360                 uint64_t iop_ie:13;
 361                 uint64_t reserved_45_63:19;
 362 #endif
 363         } s;
 364         struct cvmx_pow_ecc_err_s cn30xx;
 365         struct cvmx_pow_ecc_err_cn31xx {
 366 #ifdef __BIG_ENDIAN_BITFIELD
 367                 uint64_t reserved_14_63:50;
 368                 uint64_t rpe_ie:1;
 369                 uint64_t rpe:1;
 370                 uint64_t reserved_9_11:3;
 371                 uint64_t syn:5;
 372                 uint64_t dbe_ie:1;
 373                 uint64_t sbe_ie:1;
 374                 uint64_t dbe:1;
 375                 uint64_t sbe:1;
 376 #else
 377                 uint64_t sbe:1;
 378                 uint64_t dbe:1;
 379                 uint64_t sbe_ie:1;
 380                 uint64_t dbe_ie:1;
 381                 uint64_t syn:5;
 382                 uint64_t reserved_9_11:3;
 383                 uint64_t rpe:1;
 384                 uint64_t rpe_ie:1;
 385                 uint64_t reserved_14_63:50;
 386 #endif
 387         } cn31xx;
 388         struct cvmx_pow_ecc_err_s cn38xx;
 389         struct cvmx_pow_ecc_err_cn31xx cn38xxp2;
 390         struct cvmx_pow_ecc_err_s cn50xx;
 391         struct cvmx_pow_ecc_err_s cn52xx;
 392         struct cvmx_pow_ecc_err_s cn52xxp1;
 393         struct cvmx_pow_ecc_err_s cn56xx;
 394         struct cvmx_pow_ecc_err_s cn56xxp1;
 395         struct cvmx_pow_ecc_err_s cn58xx;
 396         struct cvmx_pow_ecc_err_s cn58xxp1;
 397         struct cvmx_pow_ecc_err_s cn61xx;
 398         struct cvmx_pow_ecc_err_s cn63xx;
 399         struct cvmx_pow_ecc_err_s cn63xxp1;
 400         struct cvmx_pow_ecc_err_s cn66xx;
 401         struct cvmx_pow_ecc_err_s cnf71xx;
 402 };
 403
 404 union cvmx_pow_int_ctl {
 405         uint64_t u64;
 406         struct cvmx_pow_int_ctl_s {
 407 #ifdef __BIG_ENDIAN_BITFIELD
 408                 uint64_t reserved_6_63:58;
 409                 uint64_t pfr_dis:1;
 410                 uint64_t nbr_thr:5;
 411 #else
 412                 uint64_t nbr_thr:5;
 413                 uint64_t pfr_dis:1;
 414                 uint64_t reserved_6_63:58;
 415 #endif
 416         } s;
 417         struct cvmx_pow_int_ctl_s cn30xx;
 418         struct cvmx_pow_int_ctl_s cn31xx;
 419         struct cvmx_pow_int_ctl_s cn38xx;
 420         struct cvmx_pow_int_ctl_s cn38xxp2;
 421         struct cvmx_pow_int_ctl_s cn50xx;
 422         struct cvmx_pow_int_ctl_s cn52xx;
 423         struct cvmx_pow_int_ctl_s cn52xxp1;
 424         struct cvmx_pow_int_ctl_s cn56xx;
 425         struct cvmx_pow_int_ctl_s cn56xxp1;
 426         struct cvmx_pow_int_ctl_s cn58xx;
 427         struct cvmx_pow_int_ctl_s cn58xxp1;
 428         struct cvmx_pow_int_ctl_s cn61xx;
 429         struct cvmx_pow_int_ctl_s cn63xx;
 430         struct cvmx_pow_int_ctl_s cn63xxp1;
 431         struct cvmx_pow_int_ctl_s cn66xx;
 432         struct cvmx_pow_int_ctl_s cnf71xx;
 433 };
 434
 435 union cvmx_pow_iq_cntx {
 436         uint64_t u64;
 437         struct cvmx_pow_iq_cntx_s {
 438 #ifdef __BIG_ENDIAN_BITFIELD
 439                 uint64_t reserved_32_63:32;
 440                 uint64_t iq_cnt:32;
 441 #else
 442                 uint64_t iq_cnt:32;
 443                 uint64_t reserved_32_63:32;
 444 #endif
 445         } s;
 446         struct cvmx_pow_iq_cntx_s cn30xx;
 447         struct cvmx_pow_iq_cntx_s cn31xx;
 448         struct cvmx_pow_iq_cntx_s cn38xx;
 449         struct cvmx_pow_iq_cntx_s cn38xxp2;
 450         struct cvmx_pow_iq_cntx_s cn50xx;
 451         struct cvmx_pow_iq_cntx_s cn52xx;
 452         struct cvmx_pow_iq_cntx_s cn52xxp1;
 453         struct cvmx_pow_iq_cntx_s cn56xx;
 454         struct cvmx_pow_iq_cntx_s cn56xxp1;
 455         struct cvmx_pow_iq_cntx_s cn58xx;
 456         struct cvmx_pow_iq_cntx_s cn58xxp1;
 457         struct cvmx_pow_iq_cntx_s cn61xx;
 458         struct cvmx_pow_iq_cntx_s cn63xx;
 459         struct cvmx_pow_iq_cntx_s cn63xxp1;
 460         struct cvmx_pow_iq_cntx_s cn66xx;
 461         struct cvmx_pow_iq_cntx_s cnf71xx;
 462 };
 463
 464 union cvmx_pow_iq_com_cnt {
 465         uint64_t u64;
 466         struct cvmx_pow_iq_com_cnt_s {
 467 #ifdef __BIG_ENDIAN_BITFIELD
 468                 uint64_t reserved_32_63:32;
 469                 uint64_t iq_cnt:32;
 470 #else
 471                 uint64_t iq_cnt:32;
 472                 uint64_t reserved_32_63:32;
 473 #endif
 474         } s;
 475         struct cvmx_pow_iq_com_cnt_s cn30xx;
 476         struct cvmx_pow_iq_com_cnt_s cn31xx;
 477         struct cvmx_pow_iq_com_cnt_s cn38xx;
 478         struct cvmx_pow_iq_com_cnt_s cn38xxp2;
 479         struct cvmx_pow_iq_com_cnt_s cn50xx;
 480         struct cvmx_pow_iq_com_cnt_s cn52xx;
 481         struct cvmx_pow_iq_com_cnt_s cn52xxp1;
 482         struct cvmx_pow_iq_com_cnt_s cn56xx;
 483         struct cvmx_pow_iq_com_cnt_s cn56xxp1;
 484         struct cvmx_pow_iq_com_cnt_s cn58xx;
 485         struct cvmx_pow_iq_com_cnt_s cn58xxp1;
 486         struct cvmx_pow_iq_com_cnt_s cn61xx;
 487         struct cvmx_pow_iq_com_cnt_s cn63xx;
 488         struct cvmx_pow_iq_com_cnt_s cn63xxp1;
 489         struct cvmx_pow_iq_com_cnt_s cn66xx;
 490         struct cvmx_pow_iq_com_cnt_s cnf71xx;
 491 };
 492
 493 union cvmx_pow_iq_int {
 494         uint64_t u64;
 495         struct cvmx_pow_iq_int_s {
 496 #ifdef __BIG_ENDIAN_BITFIELD
 497                 uint64_t reserved_8_63:56;
 498                 uint64_t iq_int:8;
 499 #else
 500                 uint64_t iq_int:8;
 501                 uint64_t reserved_8_63:56;
 502 #endif
 503         } s;
 504         struct cvmx_pow_iq_int_s cn52xx;
 505         struct cvmx_pow_iq_int_s cn52xxp1;
 506         struct cvmx_pow_iq_int_s cn56xx;
 507         struct cvmx_pow_iq_int_s cn56xxp1;
 508         struct cvmx_pow_iq_int_s cn61xx;
 509         struct cvmx_pow_iq_int_s cn63xx;
 510         struct cvmx_pow_iq_int_s cn63xxp1;
 511         struct cvmx_pow_iq_int_s cn66xx;
 512         struct cvmx_pow_iq_int_s cnf71xx;
 513 };
 514
 515 union cvmx_pow_iq_int_en {
 516         uint64_t u64;
 517         struct cvmx_pow_iq_int_en_s {
 518 #ifdef __BIG_ENDIAN_BITFIELD
 519                 uint64_t reserved_8_63:56;
 520                 uint64_t int_en:8;
 521 #else
 522                 uint64_t int_en:8;
 523                 uint64_t reserved_8_63:56;
 524 #endif
 525         } s;
 526         struct cvmx_pow_iq_int_en_s cn52xx;
 527         struct cvmx_pow_iq_int_en_s cn52xxp1;
 528         struct cvmx_pow_iq_int_en_s cn56xx;
 529         struct cvmx_pow_iq_int_en_s cn56xxp1;
 530         struct cvmx_pow_iq_int_en_s cn61xx;
 531         struct cvmx_pow_iq_int_en_s cn63xx;
 532         struct cvmx_pow_iq_int_en_s cn63xxp1;
 533         struct cvmx_pow_iq_int_en_s cn66xx;
 534         struct cvmx_pow_iq_int_en_s cnf71xx;
 535 };
 536
 537 union cvmx_pow_iq_thrx {
 538         uint64_t u64;
 539         struct cvmx_pow_iq_thrx_s {
 540 #ifdef __BIG_ENDIAN_BITFIELD
 541                 uint64_t reserved_32_63:32;
 542                 uint64_t iq_thr:32;
 543 #else
 544                 uint64_t iq_thr:32;
 545                 uint64_t reserved_32_63:32;
 546 #endif
 547         } s;
 548         struct cvmx_pow_iq_thrx_s cn52xx;
 549         struct cvmx_pow_iq_thrx_s cn52xxp1;
 550         struct cvmx_pow_iq_thrx_s cn56xx;
 551         struct cvmx_pow_iq_thrx_s cn56xxp1;
 552         struct cvmx_pow_iq_thrx_s cn61xx;
 553         struct cvmx_pow_iq_thrx_s cn63xx;
 554         struct cvmx_pow_iq_thrx_s cn63xxp1;
 555         struct cvmx_pow_iq_thrx_s cn66xx;
 556         struct cvmx_pow_iq_thrx_s cnf71xx;
 557 };
 558
 559 union cvmx_pow_nos_cnt {
 560         uint64_t u64;
 561         struct cvmx_pow_nos_cnt_s {
 562 #ifdef __BIG_ENDIAN_BITFIELD
 563                 uint64_t reserved_12_63:52;
 564                 uint64_t nos_cnt:12;
 565 #else
 566                 uint64_t nos_cnt:12;
 567                 uint64_t reserved_12_63:52;
 568 #endif
 569         } s;
 570         struct cvmx_pow_nos_cnt_cn30xx {
 571 #ifdef __BIG_ENDIAN_BITFIELD
 572                 uint64_t reserved_7_63:57;
 573                 uint64_t nos_cnt:7;
 574 #else
 575                 uint64_t nos_cnt:7;
 576                 uint64_t reserved_7_63:57;
 577 #endif
 578         } cn30xx;
 579         struct cvmx_pow_nos_cnt_cn31xx {
 580 #ifdef __BIG_ENDIAN_BITFIELD
 581                 uint64_t reserved_9_63:55;
 582                 uint64_t nos_cnt:9;
 583 #else
 584                 uint64_t nos_cnt:9;
 585                 uint64_t reserved_9_63:55;
 586 #endif
 587         } cn31xx;
 588         struct cvmx_pow_nos_cnt_s cn38xx;
 589         struct cvmx_pow_nos_cnt_s cn38xxp2;
 590         struct cvmx_pow_nos_cnt_cn31xx cn50xx;
 591         struct cvmx_pow_nos_cnt_cn52xx {
 592 #ifdef __BIG_ENDIAN_BITFIELD
 593                 uint64_t reserved_10_63:54;
 594                 uint64_t nos_cnt:10;
 595 #else
 596                 uint64_t nos_cnt:10;
 597                 uint64_t reserved_10_63:54;
 598 #endif
 599         } cn52xx;
 600         struct cvmx_pow_nos_cnt_cn52xx cn52xxp1;
 601         struct cvmx_pow_nos_cnt_s cn56xx;
 602         struct cvmx_pow_nos_cnt_s cn56xxp1;
 603         struct cvmx_pow_nos_cnt_s cn58xx;
 604         struct cvmx_pow_nos_cnt_s cn58xxp1;
 605         struct cvmx_pow_nos_cnt_cn52xx cn61xx;
 606         struct cvmx_pow_nos_cnt_cn63xx {
 607 #ifdef __BIG_ENDIAN_BITFIELD
 608                 uint64_t reserved_11_63:53;
 609                 uint64_t nos_cnt:11;
 610 #else
 611                 uint64_t nos_cnt:11;
 612                 uint64_t reserved_11_63:53;
 613 #endif
 614         } cn63xx;
 615         struct cvmx_pow_nos_cnt_cn63xx cn63xxp1;
 616         struct cvmx_pow_nos_cnt_cn63xx cn66xx;
 617         struct cvmx_pow_nos_cnt_cn52xx cnf71xx;
 618 };
 619
 620 union cvmx_pow_nw_tim {
 621         uint64_t u64;
 622         struct cvmx_pow_nw_tim_s {
 623 #ifdef __BIG_ENDIAN_BITFIELD
 624                 uint64_t reserved_10_63:54;
 625                 uint64_t nw_tim:10;
 626 #else
 627                 uint64_t nw_tim:10;
 628                 uint64_t reserved_10_63:54;
 629 #endif
 630         } s;
 631         struct cvmx_pow_nw_tim_s cn30xx;
 632         struct cvmx_pow_nw_tim_s cn31xx;
 633         struct cvmx_pow_nw_tim_s cn38xx;
 634         struct cvmx_pow_nw_tim_s cn38xxp2;
 635         struct cvmx_pow_nw_tim_s cn50xx;
 636         struct cvmx_pow_nw_tim_s cn52xx;
 637         struct cvmx_pow_nw_tim_s cn52xxp1;
 638         struct cvmx_pow_nw_tim_s cn56xx;
 639         struct cvmx_pow_nw_tim_s cn56xxp1;
 640         struct cvmx_pow_nw_tim_s cn58xx;
 641         struct cvmx_pow_nw_tim_s cn58xxp1;
 642         struct cvmx_pow_nw_tim_s cn61xx;
 643         struct cvmx_pow_nw_tim_s cn63xx;
 644         struct cvmx_pow_nw_tim_s cn63xxp1;
 645         struct cvmx_pow_nw_tim_s cn66xx;
 646         struct cvmx_pow_nw_tim_s cnf71xx;
 647 };
 648
 649 union cvmx_pow_pf_rst_msk {
 650         uint64_t u64;
 651         struct cvmx_pow_pf_rst_msk_s {
 652 #ifdef __BIG_ENDIAN_BITFIELD
 653                 uint64_t reserved_8_63:56;
 654                 uint64_t rst_msk:8;
 655 #else
 656                 uint64_t rst_msk:8;
 657                 uint64_t reserved_8_63:56;
 658 #endif
 659         } s;
 660         struct cvmx_pow_pf_rst_msk_s cn50xx;
 661         struct cvmx_pow_pf_rst_msk_s cn52xx;
 662         struct cvmx_pow_pf_rst_msk_s cn52xxp1;
 663         struct cvmx_pow_pf_rst_msk_s cn56xx;
 664         struct cvmx_pow_pf_rst_msk_s cn56xxp1;
 665         struct cvmx_pow_pf_rst_msk_s cn58xx;
 666         struct cvmx_pow_pf_rst_msk_s cn58xxp1;
 667         struct cvmx_pow_pf_rst_msk_s cn61xx;
 668         struct cvmx_pow_pf_rst_msk_s cn63xx;
 669         struct cvmx_pow_pf_rst_msk_s cn63xxp1;
 670         struct cvmx_pow_pf_rst_msk_s cn66xx;
 671         struct cvmx_pow_pf_rst_msk_s cnf71xx;
 672 };
 673
 674 union cvmx_pow_pp_grp_mskx {
 675         uint64_t u64;
 676         struct cvmx_pow_pp_grp_mskx_s {
 677 #ifdef __BIG_ENDIAN_BITFIELD
 678                 uint64_t reserved_48_63:16;
 679                 uint64_t qos7_pri:4;
 680                 uint64_t qos6_pri:4;
 681                 uint64_t qos5_pri:4;
 682                 uint64_t qos4_pri:4;
 683                 uint64_t qos3_pri:4;
 684                 uint64_t qos2_pri:4;
 685                 uint64_t qos1_pri:4;
 686                 uint64_t qos0_pri:4;
 687                 uint64_t grp_msk:16;
 688 #else
 689                 uint64_t grp_msk:16;
 690                 uint64_t qos0_pri:4;
 691                 uint64_t qos1_pri:4;
 692                 uint64_t qos2_pri:4;
 693                 uint64_t qos3_pri:4;
 694                 uint64_t qos4_pri:4;
 695                 uint64_t qos5_pri:4;
 696                 uint64_t qos6_pri:4;
 697                 uint64_t qos7_pri:4;
 698                 uint64_t reserved_48_63:16;
 699 #endif
 700         } s;
 701         struct cvmx_pow_pp_grp_mskx_cn30xx {
 702 #ifdef __BIG_ENDIAN_BITFIELD
 703                 uint64_t reserved_16_63:48;
 704                 uint64_t grp_msk:16;
 705 #else
 706                 uint64_t grp_msk:16;
 707                 uint64_t reserved_16_63:48;
 708 #endif
 709         } cn30xx;
 710         struct cvmx_pow_pp_grp_mskx_cn30xx cn31xx;
 711         struct cvmx_pow_pp_grp_mskx_cn30xx cn38xx;
 712         struct cvmx_pow_pp_grp_mskx_cn30xx cn38xxp2;
 713         struct cvmx_pow_pp_grp_mskx_s cn50xx;
 714         struct cvmx_pow_pp_grp_mskx_s cn52xx;
 715         struct cvmx_pow_pp_grp_mskx_s cn52xxp1;
 716         struct cvmx_pow_pp_grp_mskx_s cn56xx;
 717         struct cvmx_pow_pp_grp_mskx_s cn56xxp1;
 718         struct cvmx_pow_pp_grp_mskx_s cn58xx;
 719         struct cvmx_pow_pp_grp_mskx_s cn58xxp1;
 720         struct cvmx_pow_pp_grp_mskx_s cn61xx;
 721         struct cvmx_pow_pp_grp_mskx_s cn63xx;
 722         struct cvmx_pow_pp_grp_mskx_s cn63xxp1;
 723         struct cvmx_pow_pp_grp_mskx_s cn66xx;
 724         struct cvmx_pow_pp_grp_mskx_s cnf71xx;
 725 };
 726
 727 union cvmx_pow_qos_rndx {
 728         uint64_t u64;
 729         struct cvmx_pow_qos_rndx_s {
 730 #ifdef __BIG_ENDIAN_BITFIELD
 731                 uint64_t reserved_32_63:32;
 732                 uint64_t rnd_p3:8;
 733                 uint64_t rnd_p2:8;
 734                 uint64_t rnd_p1:8;
 735                 uint64_t rnd:8;
 736 #else
 737                 uint64_t rnd:8;
 738                 uint64_t rnd_p1:8;
 739                 uint64_t rnd_p2:8;
 740                 uint64_t rnd_p3:8;
 741                 uint64_t reserved_32_63:32;
 742 #endif
 743         } s;
 744         struct cvmx_pow_qos_rndx_s cn30xx;
 745         struct cvmx_pow_qos_rndx_s cn31xx;
 746         struct cvmx_pow_qos_rndx_s cn38xx;
 747         struct cvmx_pow_qos_rndx_s cn38xxp2;
 748         struct cvmx_pow_qos_rndx_s cn50xx;
 749         struct cvmx_pow_qos_rndx_s cn52xx;
 750         struct cvmx_pow_qos_rndx_s cn52xxp1;
 751         struct cvmx_pow_qos_rndx_s cn56xx;
 752         struct cvmx_pow_qos_rndx_s cn56xxp1;
 753         struct cvmx_pow_qos_rndx_s cn58xx;
 754         struct cvmx_pow_qos_rndx_s cn58xxp1;
 755         struct cvmx_pow_qos_rndx_s cn61xx;
 756         struct cvmx_pow_qos_rndx_s cn63xx;
 757         struct cvmx_pow_qos_rndx_s cn63xxp1;
 758         struct cvmx_pow_qos_rndx_s cn66xx;
 759         struct cvmx_pow_qos_rndx_s cnf71xx;
 760 };
 761
 762 union cvmx_pow_qos_thrx {
 763         uint64_t u64;
 764         struct cvmx_pow_qos_thrx_s {
 765 #ifdef __BIG_ENDIAN_BITFIELD
 766                 uint64_t reserved_60_63:4;
 767                 uint64_t des_cnt:12;
 768                 uint64_t buf_cnt:12;
 769                 uint64_t free_cnt:12;
 770                 uint64_t reserved_23_23:1;
 771                 uint64_t max_thr:11;
 772                 uint64_t reserved_11_11:1;
 773                 uint64_t min_thr:11;
 774 #else
 775                 uint64_t min_thr:11;
 776                 uint64_t reserved_11_11:1;
 777                 uint64_t max_thr:11;
 778                 uint64_t reserved_23_23:1;
 779                 uint64_t free_cnt:12;
 780                 uint64_t buf_cnt:12;
 781                 uint64_t des_cnt:12;
 782                 uint64_t reserved_60_63:4;
 783 #endif
 784         } s;
 785         struct cvmx_pow_qos_thrx_cn30xx {
 786 #ifdef __BIG_ENDIAN_BITFIELD
 787                 uint64_t reserved_55_63:9;
 788                 uint64_t des_cnt:7;
 789                 uint64_t reserved_43_47:5;
 790                 uint64_t buf_cnt:7;
 791                 uint64_t reserved_31_35:5;
 792                 uint64_t free_cnt:7;
 793                 uint64_t reserved_18_23:6;
 794                 uint64_t max_thr:6;
 795                 uint64_t reserved_6_11:6;
 796                 uint64_t min_thr:6;
 797 #else
 798                 uint64_t min_thr:6;
 799                 uint64_t reserved_6_11:6;
 800                 uint64_t max_thr:6;
 801                 uint64_t reserved_18_23:6;
 802                 uint64_t free_cnt:7;
 803                 uint64_t reserved_31_35:5;
 804                 uint64_t buf_cnt:7;
 805                 uint64_t reserved_43_47:5;
 806                 uint64_t des_cnt:7;
 807                 uint64_t reserved_55_63:9;
 808 #endif
 809         } cn30xx;
 810         struct cvmx_pow_qos_thrx_cn31xx {
 811 #ifdef __BIG_ENDIAN_BITFIELD
 812                 uint64_t reserved_57_63:7;
 813                 uint64_t des_cnt:9;
 814                 uint64_t reserved_45_47:3;
 815                 uint64_t buf_cnt:9;
 816                 uint64_t reserved_33_35:3;
 817                 uint64_t free_cnt:9;
 818                 uint64_t reserved_20_23:4;
 819                 uint64_t max_thr:8;
 820                 uint64_t reserved_8_11:4;
 821                 uint64_t min_thr:8;
 822 #else
 823                 uint64_t min_thr:8;
 824                 uint64_t reserved_8_11:4;
 825                 uint64_t max_thr:8;
 826                 uint64_t reserved_20_23:4;
 827                 uint64_t free_cnt:9;
 828                 uint64_t reserved_33_35:3;
 829                 uint64_t buf_cnt:9;
 830                 uint64_t reserved_45_47:3;
 831                 uint64_t des_cnt:9;
 832                 uint64_t reserved_57_63:7;
 833 #endif
 834         } cn31xx;
 835         struct cvmx_pow_qos_thrx_s cn38xx;
 836         struct cvmx_pow_qos_thrx_s cn38xxp2;
 837         struct cvmx_pow_qos_thrx_cn31xx cn50xx;
 838         struct cvmx_pow_qos_thrx_cn52xx {
 839 #ifdef __BIG_ENDIAN_BITFIELD
 840                 uint64_t reserved_58_63:6;
 841                 uint64_t des_cnt:10;
 842                 uint64_t reserved_46_47:2;
 843                 uint64_t buf_cnt:10;
 844                 uint64_t reserved_34_35:2;
 845                 uint64_t free_cnt:10;
 846                 uint64_t reserved_21_23:3;
 847                 uint64_t max_thr:9;
 848                 uint64_t reserved_9_11:3;
 849                 uint64_t min_thr:9;
 850 #else
 851                 uint64_t min_thr:9;
 852                 uint64_t reserved_9_11:3;
 853                 uint64_t max_thr:9;
 854                 uint64_t reserved_21_23:3;
 855                 uint64_t free_cnt:10;
 856                 uint64_t reserved_34_35:2;
 857                 uint64_t buf_cnt:10;
 858                 uint64_t reserved_46_47:2;
 859                 uint64_t des_cnt:10;
 860                 uint64_t reserved_58_63:6;
 861 #endif
 862         } cn52xx;
 863         struct cvmx_pow_qos_thrx_cn52xx cn52xxp1;
 864         struct cvmx_pow_qos_thrx_s cn56xx;
 865         struct cvmx_pow_qos_thrx_s cn56xxp1;
 866         struct cvmx_pow_qos_thrx_s cn58xx;
 867         struct cvmx_pow_qos_thrx_s cn58xxp1;
 868         struct cvmx_pow_qos_thrx_cn52xx cn61xx;
 869         struct cvmx_pow_qos_thrx_cn63xx {
 870 #ifdef __BIG_ENDIAN_BITFIELD
 871                 uint64_t reserved_59_63:5;
 872                 uint64_t des_cnt:11;
 873                 uint64_t reserved_47_47:1;
 874                 uint64_t buf_cnt:11;
 875                 uint64_t reserved_35_35:1;
 876                 uint64_t free_cnt:11;
 877                 uint64_t reserved_22_23:2;
 878                 uint64_t max_thr:10;
 879                 uint64_t reserved_10_11:2;
 880                 uint64_t min_thr:10;
 881 #else
 882                 uint64_t min_thr:10;
 883                 uint64_t reserved_10_11:2;
 884                 uint64_t max_thr:10;
 885                 uint64_t reserved_22_23:2;
 886                 uint64_t free_cnt:11;
 887                 uint64_t reserved_35_35:1;
 888                 uint64_t buf_cnt:11;
 889                 uint64_t reserved_47_47:1;
 890                 uint64_t des_cnt:11;
 891                 uint64_t reserved_59_63:5;
 892 #endif
 893         } cn63xx;
 894         struct cvmx_pow_qos_thrx_cn63xx cn63xxp1;
 895         struct cvmx_pow_qos_thrx_cn63xx cn66xx;
 896         struct cvmx_pow_qos_thrx_cn52xx cnf71xx;
 897 };
 898
 899 union cvmx_pow_ts_pc {
 900         uint64_t u64;
 901         struct cvmx_pow_ts_pc_s {
 902 #ifdef __BIG_ENDIAN_BITFIELD
 903                 uint64_t reserved_32_63:32;
 904                 uint64_t ts_pc:32;
 905 #else
 906                 uint64_t ts_pc:32;
 907                 uint64_t reserved_32_63:32;
 908 #endif
 909         } s;
 910         struct cvmx_pow_ts_pc_s cn30xx;
 911         struct cvmx_pow_ts_pc_s cn31xx;
 912         struct cvmx_pow_ts_pc_s cn38xx;
 913         struct cvmx_pow_ts_pc_s cn38xxp2;
 914         struct cvmx_pow_ts_pc_s cn50xx;
 915         struct cvmx_pow_ts_pc_s cn52xx;
 916         struct cvmx_pow_ts_pc_s cn52xxp1;
 917         struct cvmx_pow_ts_pc_s cn56xx;
 918         struct cvmx_pow_ts_pc_s cn56xxp1;
 919         struct cvmx_pow_ts_pc_s cn58xx;
 920         struct cvmx_pow_ts_pc_s cn58xxp1;
 921         struct cvmx_pow_ts_pc_s cn61xx;
 922         struct cvmx_pow_ts_pc_s cn63xx;
 923         struct cvmx_pow_ts_pc_s cn63xxp1;
 924         struct cvmx_pow_ts_pc_s cn66xx;
 925         struct cvmx_pow_ts_pc_s cnf71xx;
 926 };
 927
 928 union cvmx_pow_wa_com_pc {
 929         uint64_t u64;
 930         struct cvmx_pow_wa_com_pc_s {
 931 #ifdef __BIG_ENDIAN_BITFIELD
 932                 uint64_t reserved_32_63:32;
 933                 uint64_t wa_pc:32;
 934 #else
 935                 uint64_t wa_pc:32;
 936                 uint64_t reserved_32_63:32;
 937 #endif
 938         } s;
 939         struct cvmx_pow_wa_com_pc_s cn30xx;
 940         struct cvmx_pow_wa_com_pc_s cn31xx;
 941         struct cvmx_pow_wa_com_pc_s cn38xx;
 942         struct cvmx_pow_wa_com_pc_s cn38xxp2;
 943         struct cvmx_pow_wa_com_pc_s cn50xx;
 944         struct cvmx_pow_wa_com_pc_s cn52xx;
 945         struct cvmx_pow_wa_com_pc_s cn52xxp1;
 946         struct cvmx_pow_wa_com_pc_s cn56xx;
 947         struct cvmx_pow_wa_com_pc_s cn56xxp1;
 948         struct cvmx_pow_wa_com_pc_s cn58xx;
 949         struct cvmx_pow_wa_com_pc_s cn58xxp1;
 950         struct cvmx_pow_wa_com_pc_s cn61xx;
 951         struct cvmx_pow_wa_com_pc_s cn63xx;
 952         struct cvmx_pow_wa_com_pc_s cn63xxp1;
 953         struct cvmx_pow_wa_com_pc_s cn66xx;
 954         struct cvmx_pow_wa_com_pc_s cnf71xx;
 955 };
 956
 957 union cvmx_pow_wa_pcx {
 958         uint64_t u64;
 959         struct cvmx_pow_wa_pcx_s {
 960 #ifdef __BIG_ENDIAN_BITFIELD
 961                 uint64_t reserved_32_63:32;
 962                 uint64_t wa_pc:32;
 963 #else
 964                 uint64_t wa_pc:32;
 965                 uint64_t reserved_32_63:32;
 966 #endif
 967         } s;
 968         struct cvmx_pow_wa_pcx_s cn30xx;
 969         struct cvmx_pow_wa_pcx_s cn31xx;
 970         struct cvmx_pow_wa_pcx_s cn38xx;
 971         struct cvmx_pow_wa_pcx_s cn38xxp2;
 972         struct cvmx_pow_wa_pcx_s cn50xx;
 973         struct cvmx_pow_wa_pcx_s cn52xx;
 974         struct cvmx_pow_wa_pcx_s cn52xxp1;
 975         struct cvmx_pow_wa_pcx_s cn56xx;
 976         struct cvmx_pow_wa_pcx_s cn56xxp1;
 977         struct cvmx_pow_wa_pcx_s cn58xx;
 978         struct cvmx_pow_wa_pcx_s cn58xxp1;
 979         struct cvmx_pow_wa_pcx_s cn61xx;
 980         struct cvmx_pow_wa_pcx_s cn63xx;
 981         struct cvmx_pow_wa_pcx_s cn63xxp1;
 982         struct cvmx_pow_wa_pcx_s cn66xx;
 983         struct cvmx_pow_wa_pcx_s cnf71xx;
 984 };
 985
 986 union cvmx_pow_wq_int {
 987         uint64_t u64;
 988         struct cvmx_pow_wq_int_s {
 989 #ifdef __BIG_ENDIAN_BITFIELD
 990                 uint64_t reserved_32_63:32;
 991                 uint64_t iq_dis:16;
 992                 uint64_t wq_int:16;
 993 #else
 994                 uint64_t wq_int:16;
 995                 uint64_t iq_dis:16;
 996                 uint64_t reserved_32_63:32;
 997 #endif
 998         } s;
 999         struct cvmx_pow_wq_int_s cn30xx;
1000         struct cvmx_pow_wq_int_s cn31xx;
1001         struct cvmx_pow_wq_int_s cn38xx;
1002         struct cvmx_pow_wq_int_s cn38xxp2;
1003         struct cvmx_pow_wq_int_s cn50xx;
1004         struct cvmx_pow_wq_int_s cn52xx;
1005         struct cvmx_pow_wq_int_s cn52xxp1;
1006         struct cvmx_pow_wq_int_s cn56xx;
1007         struct cvmx_pow_wq_int_s cn56xxp1;
1008         struct cvmx_pow_wq_int_s cn58xx;
1009         struct cvmx_pow_wq_int_s cn58xxp1;
1010         struct cvmx_pow_wq_int_s cn61xx;
1011         struct cvmx_pow_wq_int_s cn63xx;
1012         struct cvmx_pow_wq_int_s cn63xxp1;
1013         struct cvmx_pow_wq_int_s cn66xx;
1014         struct cvmx_pow_wq_int_s cnf71xx;
1015 };
1016
1017 union cvmx_pow_wq_int_cntx {
1018         uint64_t u64;
1019         struct cvmx_pow_wq_int_cntx_s {
1020 #ifdef __BIG_ENDIAN_BITFIELD
1021                 uint64_t reserved_28_63:36;
1022                 uint64_t tc_cnt:4;
1023                 uint64_t ds_cnt:12;
1024                 uint64_t iq_cnt:12;
1025 #else
1026                 uint64_t iq_cnt:12;
1027                 uint64_t ds_cnt:12;
1028                 uint64_t tc_cnt:4;
1029                 uint64_t reserved_28_63:36;
1030 #endif
1031         } s;
1032         struct cvmx_pow_wq_int_cntx_cn30xx {
1033 #ifdef __BIG_ENDIAN_BITFIELD
1034                 uint64_t reserved_28_63:36;
1035                 uint64_t tc_cnt:4;
1036                 uint64_t reserved_19_23:5;
1037                 uint64_t ds_cnt:7;
1038                 uint64_t reserved_7_11:5;
1039                 uint64_t iq_cnt:7;
1040 #else
1041                 uint64_t iq_cnt:7;
1042                 uint64_t reserved_7_11:5;
1043                 uint64_t ds_cnt:7;
1044                 uint64_t reserved_19_23:5;
1045                 uint64_t tc_cnt:4;
1046                 uint64_t reserved_28_63:36;
1047 #endif
1048         } cn30xx;
1049         struct cvmx_pow_wq_int_cntx_cn31xx {
1050 #ifdef __BIG_ENDIAN_BITFIELD
1051                 uint64_t reserved_28_63:36;
1052                 uint64_t tc_cnt:4;
1053                 uint64_t reserved_21_23:3;
1054                 uint64_t ds_cnt:9;
1055                 uint64_t reserved_9_11:3;
1056                 uint64_t iq_cnt:9;
1057 #else
1058                 uint64_t iq_cnt:9;
1059                 uint64_t reserved_9_11:3;
1060                 uint64_t ds_cnt:9;
1061                 uint64_t reserved_21_23:3;
1062                 uint64_t tc_cnt:4;
1063                 uint64_t reserved_28_63:36;
1064 #endif
1065         } cn31xx;
1066         struct cvmx_pow_wq_int_cntx_s cn38xx;
1067         struct cvmx_pow_wq_int_cntx_s cn38xxp2;
1068         struct cvmx_pow_wq_int_cntx_cn31xx cn50xx;
1069         struct cvmx_pow_wq_int_cntx_cn52xx {
1070 #ifdef __BIG_ENDIAN_BITFIELD
1071                 uint64_t reserved_28_63:36;
1072                 uint64_t tc_cnt:4;
1073                 uint64_t reserved_22_23:2;
1074                 uint64_t ds_cnt:10;
1075                 uint64_t reserved_10_11:2;
1076                 uint64_t iq_cnt:10;
1077 #else
1078                 uint64_t iq_cnt:10;
1079                 uint64_t reserved_10_11:2;
1080                 uint64_t ds_cnt:10;
1081                 uint64_t reserved_22_23:2;
1082                 uint64_t tc_cnt:4;
1083                 uint64_t reserved_28_63:36;
1084 #endif
1085         } cn52xx;
1086         struct cvmx_pow_wq_int_cntx_cn52xx cn52xxp1;
1087         struct cvmx_pow_wq_int_cntx_s cn56xx;
1088         struct cvmx_pow_wq_int_cntx_s cn56xxp1;
1089         struct cvmx_pow_wq_int_cntx_s cn58xx;
1090         struct cvmx_pow_wq_int_cntx_s cn58xxp1;
1091         struct cvmx_pow_wq_int_cntx_cn52xx cn61xx;
1092         struct cvmx_pow_wq_int_cntx_cn63xx {
1093 #ifdef __BIG_ENDIAN_BITFIELD
1094                 uint64_t reserved_28_63:36;
1095                 uint64_t tc_cnt:4;
1096                 uint64_t reserved_23_23:1;
1097                 uint64_t ds_cnt:11;
1098                 uint64_t reserved_11_11:1;
1099                 uint64_t iq_cnt:11;
1100 #else
1101                 uint64_t iq_cnt:11;
1102                 uint64_t reserved_11_11:1;
1103                 uint64_t ds_cnt:11;
1104                 uint64_t reserved_23_23:1;
1105                 uint64_t tc_cnt:4;
1106                 uint64_t reserved_28_63:36;
1107 #endif
1108         } cn63xx;
1109         struct cvmx_pow_wq_int_cntx_cn63xx cn63xxp1;
1110         struct cvmx_pow_wq_int_cntx_cn63xx cn66xx;
1111         struct cvmx_pow_wq_int_cntx_cn52xx cnf71xx;
1112 };
1113
1114 union cvmx_pow_wq_int_pc {
1115         uint64_t u64;
1116         struct cvmx_pow_wq_int_pc_s {
1117 #ifdef __BIG_ENDIAN_BITFIELD
1118                 uint64_t reserved_60_63:4;
1119                 uint64_t pc:28;
1120                 uint64_t reserved_28_31:4;
1121                 uint64_t pc_thr:20;
1122                 uint64_t reserved_0_7:8;
1123 #else
1124                 uint64_t reserved_0_7:8;
1125                 uint64_t pc_thr:20;
1126                 uint64_t reserved_28_31:4;
1127                 uint64_t pc:28;
1128                 uint64_t reserved_60_63:4;
1129 #endif
1130         } s;
1131         struct cvmx_pow_wq_int_pc_s cn30xx;
1132         struct cvmx_pow_wq_int_pc_s cn31xx;
1133         struct cvmx_pow_wq_int_pc_s cn38xx;
1134         struct cvmx_pow_wq_int_pc_s cn38xxp2;
1135         struct cvmx_pow_wq_int_pc_s cn50xx;
1136         struct cvmx_pow_wq_int_pc_s cn52xx;
1137         struct cvmx_pow_wq_int_pc_s cn52xxp1;
1138         struct cvmx_pow_wq_int_pc_s cn56xx;
1139         struct cvmx_pow_wq_int_pc_s cn56xxp1;
1140         struct cvmx_pow_wq_int_pc_s cn58xx;
1141         struct cvmx_pow_wq_int_pc_s cn58xxp1;
1142         struct cvmx_pow_wq_int_pc_s cn61xx;
1143         struct cvmx_pow_wq_int_pc_s cn63xx;
1144         struct cvmx_pow_wq_int_pc_s cn63xxp1;
1145         struct cvmx_pow_wq_int_pc_s cn66xx;
1146         struct cvmx_pow_wq_int_pc_s cnf71xx;
1147 };
1148
1149 union cvmx_pow_wq_int_thrx {
1150         uint64_t u64;
1151         struct cvmx_pow_wq_int_thrx_s {
1152 #ifdef __BIG_ENDIAN_BITFIELD
1153                 uint64_t reserved_29_63:35;
1154                 uint64_t tc_en:1;
1155                 uint64_t tc_thr:4;
1156                 uint64_t reserved_23_23:1;
1157                 uint64_t ds_thr:11;
1158                 uint64_t reserved_11_11:1;
1159                 uint64_t iq_thr:11;
1160 #else
1161                 uint64_t iq_thr:11;
1162                 uint64_t reserved_11_11:1;
1163                 uint64_t ds_thr:11;
1164                 uint64_t reserved_23_23:1;
1165                 uint64_t tc_thr:4;
1166                 uint64_t tc_en:1;
1167                 uint64_t reserved_29_63:35;
1168 #endif
1169         } s;
1170         struct cvmx_pow_wq_int_thrx_cn30xx {
1171 #ifdef __BIG_ENDIAN_BITFIELD
1172                 uint64_t reserved_29_63:35;
1173                 uint64_t tc_en:1;
1174                 uint64_t tc_thr:4;
1175                 uint64_t reserved_18_23:6;
1176                 uint64_t ds_thr:6;
1177                 uint64_t reserved_6_11:6;
1178                 uint64_t iq_thr:6;
1179 #else
1180                 uint64_t iq_thr:6;
1181                 uint64_t reserved_6_11:6;
1182                 uint64_t ds_thr:6;
1183                 uint64_t reserved_18_23:6;
1184                 uint64_t tc_thr:4;
1185                 uint64_t tc_en:1;
1186                 uint64_t reserved_29_63:35;
1187 #endif
1188         } cn30xx;
1189         struct cvmx_pow_wq_int_thrx_cn31xx {
1190 #ifdef __BIG_ENDIAN_BITFIELD
1191                 uint64_t reserved_29_63:35;
1192                 uint64_t tc_en:1;
1193                 uint64_t tc_thr:4;
1194                 uint64_t reserved_20_23:4;
1195                 uint64_t ds_thr:8;
1196                 uint64_t reserved_8_11:4;
1197                 uint64_t iq_thr:8;
1198 #else
1199                 uint64_t iq_thr:8;
1200                 uint64_t reserved_8_11:4;
1201                 uint64_t ds_thr:8;
1202                 uint64_t reserved_20_23:4;
1203                 uint64_t tc_thr:4;
1204                 uint64_t tc_en:1;
1205                 uint64_t reserved_29_63:35;
1206 #endif
1207         } cn31xx;
1208         struct cvmx_pow_wq_int_thrx_s cn38xx;
1209         struct cvmx_pow_wq_int_thrx_s cn38xxp2;
1210         struct cvmx_pow_wq_int_thrx_cn31xx cn50xx;
1211         struct cvmx_pow_wq_int_thrx_cn52xx {
1212 #ifdef __BIG_ENDIAN_BITFIELD
1213                 uint64_t reserved_29_63:35;
1214                 uint64_t tc_en:1;
1215                 uint64_t tc_thr:4;
1216                 uint64_t reserved_21_23:3;
1217                 uint64_t ds_thr:9;
1218                 uint64_t reserved_9_11:3;
1219                 uint64_t iq_thr:9;
1220 #else
1221                 uint64_t iq_thr:9;
1222                 uint64_t reserved_9_11:3;
1223                 uint64_t ds_thr:9;
1224                 uint64_t reserved_21_23:3;
1225                 uint64_t tc_thr:4;
1226                 uint64_t tc_en:1;
1227                 uint64_t reserved_29_63:35;
1228 #endif
1229         } cn52xx;
1230         struct cvmx_pow_wq_int_thrx_cn52xx cn52xxp1;
1231         struct cvmx_pow_wq_int_thrx_s cn56xx;
1232         struct cvmx_pow_wq_int_thrx_s cn56xxp1;
1233         struct cvmx_pow_wq_int_thrx_s cn58xx;
1234         struct cvmx_pow_wq_int_thrx_s cn58xxp1;
1235         struct cvmx_pow_wq_int_thrx_cn52xx cn61xx;
1236         struct cvmx_pow_wq_int_thrx_cn63xx {
1237 #ifdef __BIG_ENDIAN_BITFIELD
1238                 uint64_t reserved_29_63:35;
1239                 uint64_t tc_en:1;
1240                 uint64_t tc_thr:4;
1241                 uint64_t reserved_22_23:2;
1242                 uint64_t ds_thr:10;
1243                 uint64_t reserved_10_11:2;
1244                 uint64_t iq_thr:10;
1245 #else
1246                 uint64_t iq_thr:10;
1247                 uint64_t reserved_10_11:2;
1248                 uint64_t ds_thr:10;
1249                 uint64_t reserved_22_23:2;
1250                 uint64_t tc_thr:4;
1251                 uint64_t tc_en:1;
1252                 uint64_t reserved_29_63:35;
1253 #endif
1254         } cn63xx;
1255         struct cvmx_pow_wq_int_thrx_cn63xx cn63xxp1;
1256         struct cvmx_pow_wq_int_thrx_cn63xx cn66xx;
1257         struct cvmx_pow_wq_int_thrx_cn52xx cnf71xx;
1258 };
1259
1260 union cvmx_pow_ws_pcx {
1261         uint64_t u64;
1262         struct cvmx_pow_ws_pcx_s {
1263 #ifdef __BIG_ENDIAN_BITFIELD
1264                 uint64_t reserved_32_63:32;
1265                 uint64_t ws_pc:32;
1266 #else
1267                 uint64_t ws_pc:32;
1268                 uint64_t reserved_32_63:32;
1269 #endif
1270         } s;
1271         struct cvmx_pow_ws_pcx_s cn30xx;
1272         struct cvmx_pow_ws_pcx_s cn31xx;
1273         struct cvmx_pow_ws_pcx_s cn38xx;
1274         struct cvmx_pow_ws_pcx_s cn38xxp2;
1275         struct cvmx_pow_ws_pcx_s cn50xx;
1276         struct cvmx_pow_ws_pcx_s cn52xx;
1277         struct cvmx_pow_ws_pcx_s cn52xxp1;
1278         struct cvmx_pow_ws_pcx_s cn56xx;
1279         struct cvmx_pow_ws_pcx_s cn56xxp1;
1280         struct cvmx_pow_ws_pcx_s cn58xx;
1281         struct cvmx_pow_ws_pcx_s cn58xxp1;
1282         struct cvmx_pow_ws_pcx_s cn61xx;
1283         struct cvmx_pow_ws_pcx_s cn63xx;
1284         struct cvmx_pow_ws_pcx_s cn63xxp1;
1285         struct cvmx_pow_ws_pcx_s cn66xx;
1286         struct cvmx_pow_ws_pcx_s cnf71xx;
1287 };
1288
1289 #endif