kernel/arch/mips/include/asm/octeon/cvmx-pemx-defs.h

   1 /***********************license start***************
   2  * Author: Cavium Networks
   3  *
   4  * Contact: support@caviumnetworks.com
   5  * This file is part of the OCTEON SDK
   6  *
   7  * Copyright (c) 2003-2012 Cavium Networks
   8  *
   9  * This file is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License, Version 2, as
  11  * published by the Free Software Foundation.
  12  *
  13  * This file is distributed in the hope that it will be useful, but
  14  * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
  15  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
  16  * NONINFRINGEMENT.  See the GNU General Public License for more
  17  * details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this file; if not, write to the Free Software
  21  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  22  * or visit http://www.gnu.org/licenses/.
  23  *
  24  * This file may also be available under a different license from Cavium.
  25  * Contact Cavium Networks for more information
  26  ***********************license end**************************************/
  27
  28 #ifndef __CVMX_PEMX_DEFS_H__
  29 #define __CVMX_PEMX_DEFS_H__
  30
  31 #define CVMX_PEMX_BAR1_INDEXX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C00000A8ull) + (((offset) & 15) + ((block_id) & 1) * 0x200000ull) * 8)
  32 #define CVMX_PEMX_BAR2_MASK(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000130ull) + ((block_id) & 1) * 0x1000000ull)
  33 #define CVMX_PEMX_BAR_CTL(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000128ull) + ((block_id) & 1) * 0x1000000ull)
  34 #define CVMX_PEMX_BIST_STATUS(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000018ull) + ((block_id) & 1) * 0x1000000ull)
  35 #define CVMX_PEMX_BIST_STATUS2(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000420ull) + ((block_id) & 1) * 0x1000000ull)
  36 #define CVMX_PEMX_CFG_RD(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000030ull) + ((block_id) & 1) * 0x1000000ull)
  37 #define CVMX_PEMX_CFG_WR(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000028ull) + ((block_id) & 1) * 0x1000000ull)
  38 #define CVMX_PEMX_CPL_LUT_VALID(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000098ull) + ((block_id) & 1) * 0x1000000ull)
  39 #define CVMX_PEMX_CTL_STATUS(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000000ull) + ((block_id) & 1) * 0x1000000ull)
  40 #define CVMX_PEMX_DBG_INFO(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000008ull) + ((block_id) & 1) * 0x1000000ull)
  41 #define CVMX_PEMX_DBG_INFO_EN(block_id) (CVMX_ADD_IO_SEG(0x00011800C00000A0ull) + ((block_id) & 1) * 0x1000000ull)
  42 #define CVMX_PEMX_DIAG_STATUS(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000020ull) + ((block_id) & 1) * 0x1000000ull)
  43 #define CVMX_PEMX_INB_READ_CREDITS(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000138ull) + ((block_id) & 1) * 0x1000000ull)
  44 #define CVMX_PEMX_INT_ENB(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000410ull) + ((block_id) & 1) * 0x1000000ull)
  45 #define CVMX_PEMX_INT_ENB_INT(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000418ull) + ((block_id) & 1) * 0x1000000ull)
  46 #define CVMX_PEMX_INT_SUM(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000408ull) + ((block_id) & 1) * 0x1000000ull)
  47 #define CVMX_PEMX_P2N_BAR0_START(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000080ull) + ((block_id) & 1) * 0x1000000ull)
  48 #define CVMX_PEMX_P2N_BAR1_START(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000088ull) + ((block_id) & 1) * 0x1000000ull)
  49 #define CVMX_PEMX_P2N_BAR2_START(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000090ull) + ((block_id) & 1) * 0x1000000ull)
  50 #define CVMX_PEMX_P2P_BARX_END(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C0000048ull) + (((offset) & 3) + ((block_id) & 1) * 0x100000ull) * 16)
  51 #define CVMX_PEMX_P2P_BARX_START(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C0000040ull) + (((offset) & 3) + ((block_id) & 1) * 0x100000ull) * 16)
  52 #define CVMX_PEMX_TLP_CREDITS(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000038ull) + ((block_id) & 1) * 0x1000000ull)
  53
  54 union cvmx_pemx_bar1_indexx {
  55         uint64_t u64;
  56         struct cvmx_pemx_bar1_indexx_s {
  57 #ifdef __BIG_ENDIAN_BITFIELD
  58                 uint64_t reserved_20_63:44;
  59                 uint64_t addr_idx:16;
  60                 uint64_t ca:1;
  61                 uint64_t end_swp:2;
  62                 uint64_t addr_v:1;
  63 #else
  64                 uint64_t addr_v:1;
  65                 uint64_t end_swp:2;
  66                 uint64_t ca:1;
  67                 uint64_t addr_idx:16;
  68                 uint64_t reserved_20_63:44;
  69 #endif
  70         } s;
  71         struct cvmx_pemx_bar1_indexx_s cn61xx;
  72         struct cvmx_pemx_bar1_indexx_s cn63xx;
  73         struct cvmx_pemx_bar1_indexx_s cn63xxp1;
  74         struct cvmx_pemx_bar1_indexx_s cn66xx;
  75         struct cvmx_pemx_bar1_indexx_s cn68xx;
  76         struct cvmx_pemx_bar1_indexx_s cn68xxp1;
  77         struct cvmx_pemx_bar1_indexx_s cnf71xx;
  78 };
  79
  80 union cvmx_pemx_bar2_mask {
  81         uint64_t u64;
  82         struct cvmx_pemx_bar2_mask_s {
  83 #ifdef __BIG_ENDIAN_BITFIELD
  84                 uint64_t reserved_38_63:26;
  85                 uint64_t mask:35;
  86                 uint64_t reserved_0_2:3;
  87 #else
  88                 uint64_t reserved_0_2:3;
  89                 uint64_t mask:35;
  90                 uint64_t reserved_38_63:26;
  91 #endif
  92         } s;
  93         struct cvmx_pemx_bar2_mask_s cn61xx;
  94         struct cvmx_pemx_bar2_mask_s cn66xx;
  95         struct cvmx_pemx_bar2_mask_s cn68xx;
  96         struct cvmx_pemx_bar2_mask_s cn68xxp1;
  97         struct cvmx_pemx_bar2_mask_s cnf71xx;
  98 };
  99
 100 union cvmx_pemx_bar_ctl {
 101         uint64_t u64;
 102         struct cvmx_pemx_bar_ctl_s {
 103 #ifdef __BIG_ENDIAN_BITFIELD
 104                 uint64_t reserved_7_63:57;
 105                 uint64_t bar1_siz:3;
 106                 uint64_t bar2_enb:1;
 107                 uint64_t bar2_esx:2;
 108                 uint64_t bar2_cax:1;
 109 #else
 110                 uint64_t bar2_cax:1;
 111                 uint64_t bar2_esx:2;
 112                 uint64_t bar2_enb:1;
 113                 uint64_t bar1_siz:3;
 114                 uint64_t reserved_7_63:57;
 115 #endif
 116         } s;
 117         struct cvmx_pemx_bar_ctl_s cn61xx;
 118         struct cvmx_pemx_bar_ctl_s cn63xx;
 119         struct cvmx_pemx_bar_ctl_s cn63xxp1;
 120         struct cvmx_pemx_bar_ctl_s cn66xx;
 121         struct cvmx_pemx_bar_ctl_s cn68xx;
 122         struct cvmx_pemx_bar_ctl_s cn68xxp1;
 123         struct cvmx_pemx_bar_ctl_s cnf71xx;
 124 };
 125
 126 union cvmx_pemx_bist_status {
 127         uint64_t u64;
 128         struct cvmx_pemx_bist_status_s {
 129 #ifdef __BIG_ENDIAN_BITFIELD
 130                 uint64_t reserved_8_63:56;
 131                 uint64_t retry:1;
 132                 uint64_t rqdata0:1;
 133                 uint64_t rqdata1:1;
 134                 uint64_t rqdata2:1;
 135                 uint64_t rqdata3:1;
 136                 uint64_t rqhdr1:1;
 137                 uint64_t rqhdr0:1;
 138                 uint64_t sot:1;
 139 #else
 140                 uint64_t sot:1;
 141                 uint64_t rqhdr0:1;
 142                 uint64_t rqhdr1:1;
 143                 uint64_t rqdata3:1;
 144                 uint64_t rqdata2:1;
 145                 uint64_t rqdata1:1;
 146                 uint64_t rqdata0:1;
 147                 uint64_t retry:1;
 148                 uint64_t reserved_8_63:56;
 149 #endif
 150         } s;
 151         struct cvmx_pemx_bist_status_s cn61xx;
 152         struct cvmx_pemx_bist_status_s cn63xx;
 153         struct cvmx_pemx_bist_status_s cn63xxp1;
 154         struct cvmx_pemx_bist_status_s cn66xx;
 155         struct cvmx_pemx_bist_status_s cn68xx;
 156         struct cvmx_pemx_bist_status_s cn68xxp1;
 157         struct cvmx_pemx_bist_status_s cnf71xx;
 158 };
 159
 160 union cvmx_pemx_bist_status2 {
 161         uint64_t u64;
 162         struct cvmx_pemx_bist_status2_s {
 163 #ifdef __BIG_ENDIAN_BITFIELD
 164                 uint64_t reserved_10_63:54;
 165                 uint64_t e2p_cpl:1;
 166                 uint64_t e2p_n:1;
 167                 uint64_t e2p_p:1;
 168                 uint64_t peai_p2e:1;
 169                 uint64_t pef_tpf1:1;
 170                 uint64_t pef_tpf0:1;
 171                 uint64_t pef_tnf:1;
 172                 uint64_t pef_tcf1:1;
 173                 uint64_t pef_tc0:1;
 174                 uint64_t ppf:1;
 175 #else
 176                 uint64_t ppf:1;
 177                 uint64_t pef_tc0:1;
 178                 uint64_t pef_tcf1:1;
 179                 uint64_t pef_tnf:1;
 180                 uint64_t pef_tpf0:1;
 181                 uint64_t pef_tpf1:1;
 182                 uint64_t peai_p2e:1;
 183                 uint64_t e2p_p:1;
 184                 uint64_t e2p_n:1;
 185                 uint64_t e2p_cpl:1;
 186                 uint64_t reserved_10_63:54;
 187 #endif
 188         } s;
 189         struct cvmx_pemx_bist_status2_s cn61xx;
 190         struct cvmx_pemx_bist_status2_s cn63xx;
 191         struct cvmx_pemx_bist_status2_s cn63xxp1;
 192         struct cvmx_pemx_bist_status2_s cn66xx;
 193         struct cvmx_pemx_bist_status2_s cn68xx;
 194         struct cvmx_pemx_bist_status2_s cn68xxp1;
 195         struct cvmx_pemx_bist_status2_s cnf71xx;
 196 };
 197
 198 union cvmx_pemx_cfg_rd {
 199         uint64_t u64;
 200         struct cvmx_pemx_cfg_rd_s {
 201 #ifdef __BIG_ENDIAN_BITFIELD
 202                 uint64_t data:32;
 203                 uint64_t addr:32;
 204 #else
 205                 uint64_t addr:32;
 206                 uint64_t data:32;
 207 #endif
 208         } s;
 209         struct cvmx_pemx_cfg_rd_s cn61xx;
 210         struct cvmx_pemx_cfg_rd_s cn63xx;
 211         struct cvmx_pemx_cfg_rd_s cn63xxp1;
 212         struct cvmx_pemx_cfg_rd_s cn66xx;
 213         struct cvmx_pemx_cfg_rd_s cn68xx;
 214         struct cvmx_pemx_cfg_rd_s cn68xxp1;
 215         struct cvmx_pemx_cfg_rd_s cnf71xx;
 216 };
 217
 218 union cvmx_pemx_cfg_wr {
 219         uint64_t u64;
 220         struct cvmx_pemx_cfg_wr_s {
 221 #ifdef __BIG_ENDIAN_BITFIELD
 222                 uint64_t data:32;
 223                 uint64_t addr:32;
 224 #else
 225                 uint64_t addr:32;
 226                 uint64_t data:32;
 227 #endif
 228         } s;
 229         struct cvmx_pemx_cfg_wr_s cn61xx;
 230         struct cvmx_pemx_cfg_wr_s cn63xx;
 231         struct cvmx_pemx_cfg_wr_s cn63xxp1;
 232         struct cvmx_pemx_cfg_wr_s cn66xx;
 233         struct cvmx_pemx_cfg_wr_s cn68xx;
 234         struct cvmx_pemx_cfg_wr_s cn68xxp1;
 235         struct cvmx_pemx_cfg_wr_s cnf71xx;
 236 };
 237
 238 union cvmx_pemx_cpl_lut_valid {
 239         uint64_t u64;
 240         struct cvmx_pemx_cpl_lut_valid_s {
 241 #ifdef __BIG_ENDIAN_BITFIELD
 242                 uint64_t reserved_32_63:32;
 243                 uint64_t tag:32;
 244 #else
 245                 uint64_t tag:32;
 246                 uint64_t reserved_32_63:32;
 247 #endif
 248         } s;
 249         struct cvmx_pemx_cpl_lut_valid_s cn61xx;
 250         struct cvmx_pemx_cpl_lut_valid_s cn63xx;
 251         struct cvmx_pemx_cpl_lut_valid_s cn63xxp1;
 252         struct cvmx_pemx_cpl_lut_valid_s cn66xx;
 253         struct cvmx_pemx_cpl_lut_valid_s cn68xx;
 254         struct cvmx_pemx_cpl_lut_valid_s cn68xxp1;
 255         struct cvmx_pemx_cpl_lut_valid_s cnf71xx;
 256 };
 257
 258 union cvmx_pemx_ctl_status {
 259         uint64_t u64;
 260         struct cvmx_pemx_ctl_status_s {
 261 #ifdef __BIG_ENDIAN_BITFIELD
 262                 uint64_t reserved_48_63:16;
 263                 uint64_t auto_sd:1;
 264                 uint64_t dnum:5;
 265                 uint64_t pbus:8;
 266                 uint64_t reserved_32_33:2;
 267                 uint64_t cfg_rtry:16;
 268                 uint64_t reserved_12_15:4;
 269                 uint64_t pm_xtoff:1;
 270                 uint64_t pm_xpme:1;
 271                 uint64_t ob_p_cmd:1;
 272                 uint64_t reserved_7_8:2;
 273                 uint64_t nf_ecrc:1;
 274                 uint64_t dly_one:1;
 275                 uint64_t lnk_enb:1;
 276                 uint64_t ro_ctlp:1;
 277                 uint64_t fast_lm:1;
 278                 uint64_t inv_ecrc:1;
 279                 uint64_t inv_lcrc:1;
 280 #else
 281                 uint64_t inv_lcrc:1;
 282                 uint64_t inv_ecrc:1;
 283                 uint64_t fast_lm:1;
 284                 uint64_t ro_ctlp:1;
 285                 uint64_t lnk_enb:1;
 286                 uint64_t dly_one:1;
 287                 uint64_t nf_ecrc:1;
 288                 uint64_t reserved_7_8:2;
 289                 uint64_t ob_p_cmd:1;
 290                 uint64_t pm_xpme:1;
 291                 uint64_t pm_xtoff:1;
 292                 uint64_t reserved_12_15:4;
 293                 uint64_t cfg_rtry:16;
 294                 uint64_t reserved_32_33:2;
 295                 uint64_t pbus:8;
 296                 uint64_t dnum:5;
 297                 uint64_t auto_sd:1;
 298                 uint64_t reserved_48_63:16;
 299 #endif
 300         } s;
 301         struct cvmx_pemx_ctl_status_s cn61xx;
 302         struct cvmx_pemx_ctl_status_s cn63xx;
 303         struct cvmx_pemx_ctl_status_s cn63xxp1;
 304         struct cvmx_pemx_ctl_status_s cn66xx;
 305         struct cvmx_pemx_ctl_status_s cn68xx;
 306         struct cvmx_pemx_ctl_status_s cn68xxp1;
 307         struct cvmx_pemx_ctl_status_s cnf71xx;
 308 };
 309
 310 union cvmx_pemx_dbg_info {
 311         uint64_t u64;
 312         struct cvmx_pemx_dbg_info_s {
 313 #ifdef __BIG_ENDIAN_BITFIELD
 314                 uint64_t reserved_31_63:33;
 315                 uint64_t ecrc_e:1;
 316                 uint64_t rawwpp:1;
 317                 uint64_t racpp:1;
 318                 uint64_t ramtlp:1;
 319                 uint64_t rarwdns:1;
 320                 uint64_t caar:1;
 321                 uint64_t racca:1;
 322                 uint64_t racur:1;
 323                 uint64_t rauc:1;
 324                 uint64_t rqo:1;
 325                 uint64_t fcuv:1;
 326                 uint64_t rpe:1;
 327                 uint64_t fcpvwt:1;
 328                 uint64_t dpeoosd:1;
 329                 uint64_t rtwdle:1;
 330                 uint64_t rdwdle:1;
 331                 uint64_t mre:1;
 332                 uint64_t rte:1;
 333                 uint64_t acto:1;
 334                 uint64_t rvdm:1;
 335                 uint64_t rumep:1;
 336                 uint64_t rptamrc:1;
 337                 uint64_t rpmerc:1;
 338                 uint64_t rfemrc:1;
 339                 uint64_t rnfemrc:1;
 340                 uint64_t rcemrc:1;
 341                 uint64_t rpoison:1;
 342                 uint64_t recrce:1;
 343                 uint64_t rtlplle:1;
 344                 uint64_t rtlpmal:1;
 345                 uint64_t spoison:1;
 346 #else
 347                 uint64_t spoison:1;
 348                 uint64_t rtlpmal:1;
 349                 uint64_t rtlplle:1;
 350                 uint64_t recrce:1;
 351                 uint64_t rpoison:1;
 352                 uint64_t rcemrc:1;
 353                 uint64_t rnfemrc:1;
 354                 uint64_t rfemrc:1;
 355                 uint64_t rpmerc:1;
 356                 uint64_t rptamrc:1;
 357                 uint64_t rumep:1;
 358                 uint64_t rvdm:1;
 359                 uint64_t acto:1;
 360                 uint64_t rte:1;
 361                 uint64_t mre:1;
 362                 uint64_t rdwdle:1;
 363                 uint64_t rtwdle:1;
 364                 uint64_t dpeoosd:1;
 365                 uint64_t fcpvwt:1;
 366                 uint64_t rpe:1;
 367                 uint64_t fcuv:1;
 368                 uint64_t rqo:1;
 369                 uint64_t rauc:1;
 370                 uint64_t racur:1;
 371                 uint64_t racca:1;
 372                 uint64_t caar:1;
 373                 uint64_t rarwdns:1;
 374                 uint64_t ramtlp:1;
 375                 uint64_t racpp:1;
 376                 uint64_t rawwpp:1;
 377                 uint64_t ecrc_e:1;
 378                 uint64_t reserved_31_63:33;
 379 #endif
 380         } s;
 381         struct cvmx_pemx_dbg_info_s cn61xx;
 382         struct cvmx_pemx_dbg_info_s cn63xx;
 383         struct cvmx_pemx_dbg_info_s cn63xxp1;
 384         struct cvmx_pemx_dbg_info_s cn66xx;
 385         struct cvmx_pemx_dbg_info_s cn68xx;
 386         struct cvmx_pemx_dbg_info_s cn68xxp1;
 387         struct cvmx_pemx_dbg_info_s cnf71xx;
 388 };
 389
 390 union cvmx_pemx_dbg_info_en {
 391         uint64_t u64;
 392         struct cvmx_pemx_dbg_info_en_s {
 393 #ifdef __BIG_ENDIAN_BITFIELD
 394                 uint64_t reserved_31_63:33;
 395                 uint64_t ecrc_e:1;
 396                 uint64_t rawwpp:1;
 397                 uint64_t racpp:1;
 398                 uint64_t ramtlp:1;
 399                 uint64_t rarwdns:1;
 400                 uint64_t caar:1;
 401                 uint64_t racca:1;
 402                 uint64_t racur:1;
 403                 uint64_t rauc:1;
 404                 uint64_t rqo:1;
 405                 uint64_t fcuv:1;
 406                 uint64_t rpe:1;
 407                 uint64_t fcpvwt:1;
 408                 uint64_t dpeoosd:1;
 409                 uint64_t rtwdle:1;
 410                 uint64_t rdwdle:1;
 411                 uint64_t mre:1;
 412                 uint64_t rte:1;
 413                 uint64_t acto:1;
 414                 uint64_t rvdm:1;
 415                 uint64_t rumep:1;
 416                 uint64_t rptamrc:1;
 417                 uint64_t rpmerc:1;
 418                 uint64_t rfemrc:1;
 419                 uint64_t rnfemrc:1;
 420                 uint64_t rcemrc:1;
 421                 uint64_t rpoison:1;
 422                 uint64_t recrce:1;
 423                 uint64_t rtlplle:1;
 424                 uint64_t rtlpmal:1;
 425                 uint64_t spoison:1;
 426 #else
 427                 uint64_t spoison:1;
 428                 uint64_t rtlpmal:1;
 429                 uint64_t rtlplle:1;
 430                 uint64_t recrce:1;
 431                 uint64_t rpoison:1;
 432                 uint64_t rcemrc:1;
 433                 uint64_t rnfemrc:1;
 434                 uint64_t rfemrc:1;
 435                 uint64_t rpmerc:1;
 436                 uint64_t rptamrc:1;
 437                 uint64_t rumep:1;
 438                 uint64_t rvdm:1;
 439                 uint64_t acto:1;
 440                 uint64_t rte:1;
 441                 uint64_t mre:1;
 442                 uint64_t rdwdle:1;
 443                 uint64_t rtwdle:1;
 444                 uint64_t dpeoosd:1;
 445                 uint64_t fcpvwt:1;
 446                 uint64_t rpe:1;
 447                 uint64_t fcuv:1;
 448                 uint64_t rqo:1;
 449                 uint64_t rauc:1;
 450                 uint64_t racur:1;
 451                 uint64_t racca:1;
 452                 uint64_t caar:1;
 453                 uint64_t rarwdns:1;
 454                 uint64_t ramtlp:1;
 455                 uint64_t racpp:1;
 456                 uint64_t rawwpp:1;
 457                 uint64_t ecrc_e:1;
 458                 uint64_t reserved_31_63:33;
 459 #endif
 460         } s;
 461         struct cvmx_pemx_dbg_info_en_s cn61xx;
 462         struct cvmx_pemx_dbg_info_en_s cn63xx;
 463         struct cvmx_pemx_dbg_info_en_s cn63xxp1;
 464         struct cvmx_pemx_dbg_info_en_s cn66xx;
 465         struct cvmx_pemx_dbg_info_en_s cn68xx;
 466         struct cvmx_pemx_dbg_info_en_s cn68xxp1;
 467         struct cvmx_pemx_dbg_info_en_s cnf71xx;
 468 };
 469
 470 union cvmx_pemx_diag_status {
 471         uint64_t u64;
 472         struct cvmx_pemx_diag_status_s {
 473 #ifdef __BIG_ENDIAN_BITFIELD
 474                 uint64_t reserved_4_63:60;
 475                 uint64_t pm_dst:1;
 476                 uint64_t pm_stat:1;
 477                 uint64_t pm_en:1;
 478                 uint64_t aux_en:1;
 479 #else
 480                 uint64_t aux_en:1;
 481                 uint64_t pm_en:1;
 482                 uint64_t pm_stat:1;
 483                 uint64_t pm_dst:1;
 484                 uint64_t reserved_4_63:60;
 485 #endif
 486         } s;
 487         struct cvmx_pemx_diag_status_s cn61xx;
 488         struct cvmx_pemx_diag_status_s cn63xx;
 489         struct cvmx_pemx_diag_status_s cn63xxp1;
 490         struct cvmx_pemx_diag_status_s cn66xx;
 491         struct cvmx_pemx_diag_status_s cn68xx;
 492         struct cvmx_pemx_diag_status_s cn68xxp1;
 493         struct cvmx_pemx_diag_status_s cnf71xx;
 494 };
 495
 496 union cvmx_pemx_inb_read_credits {
 497         uint64_t u64;
 498         struct cvmx_pemx_inb_read_credits_s {
 499 #ifdef __BIG_ENDIAN_BITFIELD
 500                 uint64_t reserved_6_63:58;
 501                 uint64_t num:6;
 502 #else
 503                 uint64_t num:6;
 504                 uint64_t reserved_6_63:58;
 505 #endif
 506         } s;
 507         struct cvmx_pemx_inb_read_credits_s cn61xx;
 508         struct cvmx_pemx_inb_read_credits_s cn66xx;
 509         struct cvmx_pemx_inb_read_credits_s cn68xx;
 510         struct cvmx_pemx_inb_read_credits_s cnf71xx;
 511 };
 512
 513 union cvmx_pemx_int_enb {
 514         uint64_t u64;
 515         struct cvmx_pemx_int_enb_s {
 516 #ifdef __BIG_ENDIAN_BITFIELD
 517                 uint64_t reserved_14_63:50;
 518                 uint64_t crs_dr:1;
 519                 uint64_t crs_er:1;
 520                 uint64_t rdlk:1;
 521                 uint64_t exc:1;
 522                 uint64_t un_bx:1;
 523                 uint64_t un_b2:1;
 524                 uint64_t un_b1:1;
 525                 uint64_t up_bx:1;
 526                 uint64_t up_b2:1;
 527                 uint64_t up_b1:1;
 528                 uint64_t pmem:1;
 529                 uint64_t pmei:1;
 530                 uint64_t se:1;
 531                 uint64_t aeri:1;
 532 #else
 533                 uint64_t aeri:1;
 534                 uint64_t se:1;
 535                 uint64_t pmei:1;
 536                 uint64_t pmem:1;
 537                 uint64_t up_b1:1;
 538                 uint64_t up_b2:1;
 539                 uint64_t up_bx:1;
 540                 uint64_t un_b1:1;
 541                 uint64_t un_b2:1;
 542                 uint64_t un_bx:1;
 543                 uint64_t exc:1;
 544                 uint64_t rdlk:1;
 545                 uint64_t crs_er:1;
 546                 uint64_t crs_dr:1;
 547                 uint64_t reserved_14_63:50;
 548 #endif
 549         } s;
 550         struct cvmx_pemx_int_enb_s cn61xx;
 551         struct cvmx_pemx_int_enb_s cn63xx;
 552         struct cvmx_pemx_int_enb_s cn63xxp1;
 553         struct cvmx_pemx_int_enb_s cn66xx;
 554         struct cvmx_pemx_int_enb_s cn68xx;
 555         struct cvmx_pemx_int_enb_s cn68xxp1;
 556         struct cvmx_pemx_int_enb_s cnf71xx;
 557 };
 558
 559 union cvmx_pemx_int_enb_int {
 560         uint64_t u64;
 561         struct cvmx_pemx_int_enb_int_s {
 562 #ifdef __BIG_ENDIAN_BITFIELD
 563                 uint64_t reserved_14_63:50;
 564                 uint64_t crs_dr:1;
 565                 uint64_t crs_er:1;
 566                 uint64_t rdlk:1;
 567                 uint64_t exc:1;
 568                 uint64_t un_bx:1;
 569                 uint64_t un_b2:1;
 570                 uint64_t un_b1:1;
 571                 uint64_t up_bx:1;
 572                 uint64_t up_b2:1;
 573                 uint64_t up_b1:1;
 574                 uint64_t pmem:1;
 575                 uint64_t pmei:1;
 576                 uint64_t se:1;
 577                 uint64_t aeri:1;
 578 #else
 579                 uint64_t aeri:1;
 580                 uint64_t se:1;
 581                 uint64_t pmei:1;
 582                 uint64_t pmem:1;
 583                 uint64_t up_b1:1;
 584                 uint64_t up_b2:1;
 585                 uint64_t up_bx:1;
 586                 uint64_t un_b1:1;
 587                 uint64_t un_b2:1;
 588                 uint64_t un_bx:1;
 589                 uint64_t exc:1;
 590                 uint64_t rdlk:1;
 591                 uint64_t crs_er:1;
 592                 uint64_t crs_dr:1;
 593                 uint64_t reserved_14_63:50;
 594 #endif
 595         } s;
 596         struct cvmx_pemx_int_enb_int_s cn61xx;
 597         struct cvmx_pemx_int_enb_int_s cn63xx;
 598         struct cvmx_pemx_int_enb_int_s cn63xxp1;
 599         struct cvmx_pemx_int_enb_int_s cn66xx;
 600         struct cvmx_pemx_int_enb_int_s cn68xx;
 601         struct cvmx_pemx_int_enb_int_s cn68xxp1;
 602         struct cvmx_pemx_int_enb_int_s cnf71xx;
 603 };
 604
 605 union cvmx_pemx_int_sum {
 606         uint64_t u64;
 607         struct cvmx_pemx_int_sum_s {
 608 #ifdef __BIG_ENDIAN_BITFIELD
 609                 uint64_t reserved_14_63:50;
 610                 uint64_t crs_dr:1;
 611                 uint64_t crs_er:1;
 612                 uint64_t rdlk:1;
 613                 uint64_t exc:1;
 614                 uint64_t un_bx:1;
 615                 uint64_t un_b2:1;
 616                 uint64_t un_b1:1;
 617                 uint64_t up_bx:1;
 618                 uint64_t up_b2:1;
 619                 uint64_t up_b1:1;
 620                 uint64_t pmem:1;
 621                 uint64_t pmei:1;
 622                 uint64_t se:1;
 623                 uint64_t aeri:1;
 624 #else
 625                 uint64_t aeri:1;
 626                 uint64_t se:1;
 627                 uint64_t pmei:1;
 628                 uint64_t pmem:1;
 629                 uint64_t up_b1:1;
 630                 uint64_t up_b2:1;
 631                 uint64_t up_bx:1;
 632                 uint64_t un_b1:1;
 633                 uint64_t un_b2:1;
 634                 uint64_t un_bx:1;
 635                 uint64_t exc:1;
 636                 uint64_t rdlk:1;
 637                 uint64_t crs_er:1;
 638                 uint64_t crs_dr:1;
 639                 uint64_t reserved_14_63:50;
 640 #endif
 641         } s;
 642         struct cvmx_pemx_int_sum_s cn61xx;
 643         struct cvmx_pemx_int_sum_s cn63xx;
 644         struct cvmx_pemx_int_sum_s cn63xxp1;
 645         struct cvmx_pemx_int_sum_s cn66xx;
 646         struct cvmx_pemx_int_sum_s cn68xx;
 647         struct cvmx_pemx_int_sum_s cn68xxp1;
 648         struct cvmx_pemx_int_sum_s cnf71xx;
 649 };
 650
 651 union cvmx_pemx_p2n_bar0_start {
 652         uint64_t u64;
 653         struct cvmx_pemx_p2n_bar0_start_s {
 654 #ifdef __BIG_ENDIAN_BITFIELD
 655                 uint64_t addr:50;
 656                 uint64_t reserved_0_13:14;
 657 #else
 658                 uint64_t reserved_0_13:14;
 659                 uint64_t addr:50;
 660 #endif
 661         } s;
 662         struct cvmx_pemx_p2n_bar0_start_s cn61xx;
 663         struct cvmx_pemx_p2n_bar0_start_s cn63xx;
 664         struct cvmx_pemx_p2n_bar0_start_s cn63xxp1;
 665         struct cvmx_pemx_p2n_bar0_start_s cn66xx;
 666         struct cvmx_pemx_p2n_bar0_start_s cn68xx;
 667         struct cvmx_pemx_p2n_bar0_start_s cn68xxp1;
 668         struct cvmx_pemx_p2n_bar0_start_s cnf71xx;
 669 };
 670
 671 union cvmx_pemx_p2n_bar1_start {
 672         uint64_t u64;
 673         struct cvmx_pemx_p2n_bar1_start_s {
 674 #ifdef __BIG_ENDIAN_BITFIELD
 675                 uint64_t addr:38;
 676                 uint64_t reserved_0_25:26;
 677 #else
 678                 uint64_t reserved_0_25:26;
 679                 uint64_t addr:38;
 680 #endif
 681         } s;
 682         struct cvmx_pemx_p2n_bar1_start_s cn61xx;
 683         struct cvmx_pemx_p2n_bar1_start_s cn63xx;
 684         struct cvmx_pemx_p2n_bar1_start_s cn63xxp1;
 685         struct cvmx_pemx_p2n_bar1_start_s cn66xx;
 686         struct cvmx_pemx_p2n_bar1_start_s cn68xx;
 687         struct cvmx_pemx_p2n_bar1_start_s cn68xxp1;
 688         struct cvmx_pemx_p2n_bar1_start_s cnf71xx;
 689 };
 690
 691 union cvmx_pemx_p2n_bar2_start {
 692         uint64_t u64;
 693         struct cvmx_pemx_p2n_bar2_start_s {
 694 #ifdef __BIG_ENDIAN_BITFIELD
 695                 uint64_t addr:23;
 696                 uint64_t reserved_0_40:41;
 697 #else
 698                 uint64_t reserved_0_40:41;
 699                 uint64_t addr:23;
 700 #endif
 701         } s;
 702         struct cvmx_pemx_p2n_bar2_start_s cn61xx;
 703         struct cvmx_pemx_p2n_bar2_start_s cn63xx;
 704         struct cvmx_pemx_p2n_bar2_start_s cn63xxp1;
 705         struct cvmx_pemx_p2n_bar2_start_s cn66xx;
 706         struct cvmx_pemx_p2n_bar2_start_s cn68xx;
 707         struct cvmx_pemx_p2n_bar2_start_s cn68xxp1;
 708         struct cvmx_pemx_p2n_bar2_start_s cnf71xx;
 709 };
 710
 711 union cvmx_pemx_p2p_barx_end {
 712         uint64_t u64;
 713         struct cvmx_pemx_p2p_barx_end_s {
 714 #ifdef __BIG_ENDIAN_BITFIELD
 715                 uint64_t addr:52;
 716                 uint64_t reserved_0_11:12;
 717 #else
 718                 uint64_t reserved_0_11:12;
 719                 uint64_t addr:52;
 720 #endif
 721         } s;
 722         struct cvmx_pemx_p2p_barx_end_s cn63xx;
 723         struct cvmx_pemx_p2p_barx_end_s cn63xxp1;
 724         struct cvmx_pemx_p2p_barx_end_s cn66xx;
 725         struct cvmx_pemx_p2p_barx_end_s cn68xx;
 726         struct cvmx_pemx_p2p_barx_end_s cn68xxp1;
 727 };
 728
 729 union cvmx_pemx_p2p_barx_start {
 730         uint64_t u64;
 731         struct cvmx_pemx_p2p_barx_start_s {
 732 #ifdef __BIG_ENDIAN_BITFIELD
 733                 uint64_t addr:52;
 734                 uint64_t reserved_0_11:12;
 735 #else
 736                 uint64_t reserved_0_11:12;
 737                 uint64_t addr:52;
 738 #endif
 739         } s;
 740         struct cvmx_pemx_p2p_barx_start_s cn63xx;
 741         struct cvmx_pemx_p2p_barx_start_s cn63xxp1;
 742         struct cvmx_pemx_p2p_barx_start_s cn66xx;
 743         struct cvmx_pemx_p2p_barx_start_s cn68xx;
 744         struct cvmx_pemx_p2p_barx_start_s cn68xxp1;
 745 };
 746
 747 union cvmx_pemx_tlp_credits {
 748         uint64_t u64;
 749         struct cvmx_pemx_tlp_credits_s {
 750 #ifdef __BIG_ENDIAN_BITFIELD
 751                 uint64_t reserved_56_63:8;
 752                 uint64_t peai_ppf:8;
 753                 uint64_t pem_cpl:8;
 754                 uint64_t pem_np:8;
 755                 uint64_t pem_p:8;
 756                 uint64_t sli_cpl:8;
 757                 uint64_t sli_np:8;
 758                 uint64_t sli_p:8;
 759 #else
 760                 uint64_t sli_p:8;
 761                 uint64_t sli_np:8;
 762                 uint64_t sli_cpl:8;
 763                 uint64_t pem_p:8;
 764                 uint64_t pem_np:8;
 765                 uint64_t pem_cpl:8;
 766                 uint64_t peai_ppf:8;
 767                 uint64_t reserved_56_63:8;
 768 #endif
 769         } s;
 770         struct cvmx_pemx_tlp_credits_cn61xx {
 771 #ifdef __BIG_ENDIAN_BITFIELD
 772                 uint64_t reserved_56_63:8;
 773                 uint64_t peai_ppf:8;
 774                 uint64_t reserved_24_47:24;
 775                 uint64_t sli_cpl:8;
 776                 uint64_t sli_np:8;
 777                 uint64_t sli_p:8;
 778 #else
 779                 uint64_t sli_p:8;
 780                 uint64_t sli_np:8;
 781                 uint64_t sli_cpl:8;
 782                 uint64_t reserved_24_47:24;
 783                 uint64_t peai_ppf:8;
 784                 uint64_t reserved_56_63:8;
 785 #endif
 786         } cn61xx;
 787         struct cvmx_pemx_tlp_credits_s cn63xx;
 788         struct cvmx_pemx_tlp_credits_s cn63xxp1;
 789         struct cvmx_pemx_tlp_credits_s cn66xx;
 790         struct cvmx_pemx_tlp_credits_s cn68xx;
 791         struct cvmx_pemx_tlp_credits_s cn68xxp1;
 792         struct cvmx_pemx_tlp_credits_cn61xx cnf71xx;
 793 };
 794
 795 #endif