kernel/arch/mips/include/asm/netlogic/xlr/bridge.h

   1 /*
   2  * Copyright (c) 2003-2012 Broadcom Corporation
   3  * All Rights Reserved
   4  *
   5  * This software is available to you under a choice of one of two
   6  * licenses.  You may choose to be licensed under the terms of the GNU
   7  * General Public License (GPL) Version 2, available from the file
   8  * COPYING in the main directory of this source tree, or the Broadcom
   9  * license below:
  10  *
  11  * Redistribution and use in source and binary forms, with or without
  12  * modification, are permitted provided that the following conditions
  13  * are met:
  14  *
  15  * 1. Redistributions of source code must retain the above copyright
  16  *    notice, this list of conditions and the following disclaimer.
  17  * 2. Redistributions in binary form must reproduce the above copyright
  18  *    notice, this list of conditions and the following disclaimer in
  19  *    the documentation and/or other materials provided with the
  20  *    distribution.
  21  *
  22  * THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR
  23  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  24  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  25  * ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM OR CONTRIBUTORS BE LIABLE
  26  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  27  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  28  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
  29  * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
  30  * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
  31  * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
  32  * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  33  */
  34 #ifndef _ASM_NLM_BRIDGE_H_
  35 #define _ASM_NLM_BRIDGE_H_
  36
  37 #define BRIDGE_DRAM_0_BAR               0
  38 #define BRIDGE_DRAM_1_BAR               1
  39 #define BRIDGE_DRAM_2_BAR               2
  40 #define BRIDGE_DRAM_3_BAR               3
  41 #define BRIDGE_DRAM_4_BAR               4
  42 #define BRIDGE_DRAM_5_BAR               5
  43 #define BRIDGE_DRAM_6_BAR               6
  44 #define BRIDGE_DRAM_7_BAR               7
  45 #define BRIDGE_DRAM_CHN_0_MTR_0_BAR     8
  46 #define BRIDGE_DRAM_CHN_0_MTR_1_BAR     9
  47 #define BRIDGE_DRAM_CHN_0_MTR_2_BAR     10
  48 #define BRIDGE_DRAM_CHN_0_MTR_3_BAR     11
  49 #define BRIDGE_DRAM_CHN_0_MTR_4_BAR     12
  50 #define BRIDGE_DRAM_CHN_0_MTR_5_BAR     13
  51 #define BRIDGE_DRAM_CHN_0_MTR_6_BAR     14
  52 #define BRIDGE_DRAM_CHN_0_MTR_7_BAR     15
  53 #define BRIDGE_DRAM_CHN_1_MTR_0_BAR     16
  54 #define BRIDGE_DRAM_CHN_1_MTR_1_BAR     17
  55 #define BRIDGE_DRAM_CHN_1_MTR_2_BAR     18
  56 #define BRIDGE_DRAM_CHN_1_MTR_3_BAR     19
  57 #define BRIDGE_DRAM_CHN_1_MTR_4_BAR     20
  58 #define BRIDGE_DRAM_CHN_1_MTR_5_BAR     21
  59 #define BRIDGE_DRAM_CHN_1_MTR_6_BAR     22
  60 #define BRIDGE_DRAM_CHN_1_MTR_7_BAR     23
  61 #define BRIDGE_CFG_BAR                  24
  62 #define BRIDGE_PHNX_IO_BAR              25
  63 #define BRIDGE_FLASH_BAR                26
  64 #define BRIDGE_SRAM_BAR                 27
  65 #define BRIDGE_HTMEM_BAR                28
  66 #define BRIDGE_HTINT_BAR                29
  67 #define BRIDGE_HTPIC_BAR                30
  68 #define BRIDGE_HTSM_BAR                 31
  69 #define BRIDGE_HTIO_BAR                 32
  70 #define BRIDGE_HTCFG_BAR                33
  71 #define BRIDGE_PCIXCFG_BAR              34
  72 #define BRIDGE_PCIXMEM_BAR              35
  73 #define BRIDGE_PCIXIO_BAR               36
  74 #define BRIDGE_DEVICE_MASK              37
  75 #define BRIDGE_AERR_INTR_LOG1           38
  76 #define BRIDGE_AERR_INTR_LOG2           39
  77 #define BRIDGE_AERR_INTR_LOG3           40
  78 #define BRIDGE_AERR_DEV_STAT            41
  79 #define BRIDGE_AERR1_LOG1               42
  80 #define BRIDGE_AERR1_LOG2               43
  81 #define BRIDGE_AERR1_LOG3               44
  82 #define BRIDGE_AERR1_DEV_STAT           45
  83 #define BRIDGE_AERR_INTR_EN             46
  84 #define BRIDGE_AERR_UPG                 47
  85 #define BRIDGE_AERR_CLEAR               48
  86 #define BRIDGE_AERR1_CLEAR              49
  87 #define BRIDGE_SBE_COUNTS               50
  88 #define BRIDGE_DBE_COUNTS               51
  89 #define BRIDGE_BITERR_INT_EN            52
  90
  91 #define BRIDGE_SYS2IO_CREDITS           53
  92 #define BRIDGE_EVNT_CNT_CTRL1           54
  93 #define BRIDGE_EVNT_COUNTER1            55
  94 #define BRIDGE_EVNT_CNT_CTRL2           56
  95 #define BRIDGE_EVNT_COUNTER2            57
  96 #define BRIDGE_RESERVED1                58
  97
  98 #define BRIDGE_DEFEATURE                59
  99 #define BRIDGE_SCRATCH0                 60
 100 #define BRIDGE_SCRATCH1                 61
 101 #define BRIDGE_SCRATCH2                 62
 102 #define BRIDGE_SCRATCH3                 63
 103
 104 #endif