kernel/arch/mips/include/asm/kvm_host.h

   1 /*
   2 * This file is subject to the terms and conditions of the GNU General Public
   3 * License.  See the file "COPYING" in the main directory of this archive
   4 * for more details.
   5 *
   6 * Copyright (C) 2012  MIPS Technologies, Inc.  All rights reserved.
   7 * Authors: Sanjay Lal <sanjayl@kymasys.com>
   8 */
   9
  10 #ifndef __MIPS_KVM_HOST_H__
  11 #define __MIPS_KVM_HOST_H__
  12
  13 #include <linux/mutex.h>
  14 #include <linux/hrtimer.h>
  15 #include <linux/interrupt.h>
  16 #include <linux/types.h>
  17 #include <linux/kvm.h>
  18 #include <linux/kvm_types.h>
  19 #include <linux/threads.h>
  20 #include <linux/spinlock.h>
  21
  22 /* MIPS KVM register ids */
  23 #define MIPS_CP0_32(_R, _S)                                     \
  24         (KVM_REG_MIPS_CP0 | KVM_REG_SIZE_U32 | (8 * (_R) + (_S)))
  25
  26 #define MIPS_CP0_64(_R, _S)                                     \
  27         (KVM_REG_MIPS_CP0 | KVM_REG_SIZE_U64 | (8 * (_R) + (_S)))
  28
  29 #define KVM_REG_MIPS_CP0_INDEX          MIPS_CP0_32(0, 0)
  30 #define KVM_REG_MIPS_CP0_ENTRYLO0       MIPS_CP0_64(2, 0)
  31 #define KVM_REG_MIPS_CP0_ENTRYLO1       MIPS_CP0_64(3, 0)
  32 #define KVM_REG_MIPS_CP0_CONTEXT        MIPS_CP0_64(4, 0)
  33 #define KVM_REG_MIPS_CP0_USERLOCAL      MIPS_CP0_64(4, 2)
  34 #define KVM_REG_MIPS_CP0_PAGEMASK       MIPS_CP0_32(5, 0)
  35 #define KVM_REG_MIPS_CP0_PAGEGRAIN      MIPS_CP0_32(5, 1)
  36 #define KVM_REG_MIPS_CP0_WIRED          MIPS_CP0_32(6, 0)
  37 #define KVM_REG_MIPS_CP0_HWRENA         MIPS_CP0_32(7, 0)
  38 #define KVM_REG_MIPS_CP0_BADVADDR       MIPS_CP0_64(8, 0)
  39 #define KVM_REG_MIPS_CP0_COUNT          MIPS_CP0_32(9, 0)
  40 #define KVM_REG_MIPS_CP0_ENTRYHI        MIPS_CP0_64(10, 0)
  41 #define KVM_REG_MIPS_CP0_COMPARE        MIPS_CP0_32(11, 0)
  42 #define KVM_REG_MIPS_CP0_STATUS         MIPS_CP0_32(12, 0)
  43 #define KVM_REG_MIPS_CP0_CAUSE          MIPS_CP0_32(13, 0)
  44 #define KVM_REG_MIPS_CP0_EPC            MIPS_CP0_64(14, 0)
  45 #define KVM_REG_MIPS_CP0_PRID           MIPS_CP0_32(15, 0)
  46 #define KVM_REG_MIPS_CP0_EBASE          MIPS_CP0_64(15, 1)
  47 #define KVM_REG_MIPS_CP0_CONFIG         MIPS_CP0_32(16, 0)
  48 #define KVM_REG_MIPS_CP0_CONFIG1        MIPS_CP0_32(16, 1)
  49 #define KVM_REG_MIPS_CP0_CONFIG2        MIPS_CP0_32(16, 2)
  50 #define KVM_REG_MIPS_CP0_CONFIG3        MIPS_CP0_32(16, 3)
  51 #define KVM_REG_MIPS_CP0_CONFIG4        MIPS_CP0_32(16, 4)
  52 #define KVM_REG_MIPS_CP0_CONFIG5        MIPS_CP0_32(16, 5)
  53 #define KVM_REG_MIPS_CP0_CONFIG7        MIPS_CP0_32(16, 7)
  54 #define KVM_REG_MIPS_CP0_XCONTEXT       MIPS_CP0_64(20, 0)
  55 #define KVM_REG_MIPS_CP0_ERROREPC       MIPS_CP0_64(30, 0)
  56
  57
  58 #define KVM_MAX_VCPUS           1
  59 #define KVM_USER_MEM_SLOTS      8
  60 /* memory slots that does not exposed to userspace */
  61 #define KVM_PRIVATE_MEM_SLOTS   0
  62
  63 #define KVM_COALESCED_MMIO_PAGE_OFFSET 1
  64 #define KVM_HALT_POLL_NS_DEFAULT 500000
  65
  66
  67
  68 /* Special address that contains the comm page, used for reducing # of traps */
  69 #define KVM_GUEST_COMMPAGE_ADDR         0x0
  70
  71 #define KVM_GUEST_KERNEL_MODE(vcpu)     ((kvm_read_c0_guest_status(vcpu->arch.cop0) & (ST0_EXL | ST0_ERL)) || \
  72                                         ((kvm_read_c0_guest_status(vcpu->arch.cop0) & KSU_USER) == 0))
  73
  74 #define KVM_GUEST_KUSEG                 0x00000000UL
  75 #define KVM_GUEST_KSEG0                 0x40000000UL
  76 #define KVM_GUEST_KSEG23                0x60000000UL
  77 #define KVM_GUEST_KSEGX(a)              ((_ACAST32_(a)) & 0x60000000)
  78 #define KVM_GUEST_CPHYSADDR(a)          ((_ACAST32_(a)) & 0x1fffffff)
  79
  80 #define KVM_GUEST_CKSEG0ADDR(a)         (KVM_GUEST_CPHYSADDR(a) | KVM_GUEST_KSEG0)
  81 #define KVM_GUEST_CKSEG1ADDR(a)         (KVM_GUEST_CPHYSADDR(a) | KVM_GUEST_KSEG1)
  82 #define KVM_GUEST_CKSEG23ADDR(a)        (KVM_GUEST_CPHYSADDR(a) | KVM_GUEST_KSEG23)
  83
  84 /*
  85  * Map an address to a certain kernel segment
  86  */
  87 #define KVM_GUEST_KSEG0ADDR(a)          (KVM_GUEST_CPHYSADDR(a) | KVM_GUEST_KSEG0)
  88 #define KVM_GUEST_KSEG1ADDR(a)          (KVM_GUEST_CPHYSADDR(a) | KVM_GUEST_KSEG1)
  89 #define KVM_GUEST_KSEG23ADDR(a)         (KVM_GUEST_CPHYSADDR(a) | KVM_GUEST_KSEG23)
  90
  91 #define KVM_INVALID_PAGE                0xdeadbeef
  92 #define KVM_INVALID_INST                0xdeadbeef
  93 #define KVM_INVALID_ADDR                0xdeadbeef
  94
  95 #define KVM_MALTA_GUEST_RTC_ADDR        0xb8000070UL
  96
  97 #define GUEST_TICKS_PER_JIFFY           (40000000/HZ)
  98 #define MS_TO_NS(x)                     (x * 1E6L)
  99
 100 #define CAUSEB_DC                       27
 101 #define CAUSEF_DC                       (_ULCAST_(1) << 27)
 102
 103 extern atomic_t kvm_mips_instance;
 104 extern pfn_t(*kvm_mips_gfn_to_pfn) (struct kvm *kvm, gfn_t gfn);
 105 extern void (*kvm_mips_release_pfn_clean) (pfn_t pfn);
 106 extern bool(*kvm_mips_is_error_pfn) (pfn_t pfn);
 107
 108 struct kvm_vm_stat {
 109         u32 remote_tlb_flush;
 110 };
 111
 112 struct kvm_vcpu_stat {
 113         u32 wait_exits;
 114         u32 cache_exits;
 115         u32 signal_exits;
 116         u32 int_exits;
 117         u32 cop_unusable_exits;
 118         u32 tlbmod_exits;
 119         u32 tlbmiss_ld_exits;
 120         u32 tlbmiss_st_exits;
 121         u32 addrerr_st_exits;
 122         u32 addrerr_ld_exits;
 123         u32 syscall_exits;
 124         u32 resvd_inst_exits;
 125         u32 break_inst_exits;
 126         u32 trap_inst_exits;
 127         u32 msa_fpe_exits;
 128         u32 fpe_exits;
 129         u32 msa_disabled_exits;
 130         u32 flush_dcache_exits;
 131         u32 halt_successful_poll;
 132         u32 halt_attempted_poll;
 133         u32 halt_wakeup;
 134 };
 135
 136 enum kvm_mips_exit_types {
 137         WAIT_EXITS,
 138         CACHE_EXITS,
 139         SIGNAL_EXITS,
 140         INT_EXITS,
 141         COP_UNUSABLE_EXITS,
 142         TLBMOD_EXITS,
 143         TLBMISS_LD_EXITS,
 144         TLBMISS_ST_EXITS,
 145         ADDRERR_ST_EXITS,
 146         ADDRERR_LD_EXITS,
 147         SYSCALL_EXITS,
 148         RESVD_INST_EXITS,
 149         BREAK_INST_EXITS,
 150         TRAP_INST_EXITS,
 151         MSA_FPE_EXITS,
 152         FPE_EXITS,
 153         MSA_DISABLED_EXITS,
 154         FLUSH_DCACHE_EXITS,
 155         MAX_KVM_MIPS_EXIT_TYPES
 156 };
 157
 158 struct kvm_arch_memory_slot {
 159 };
 160
 161 struct kvm_arch {
 162         /* Guest GVA->HPA page table */
 163         unsigned long *guest_pmap;
 164         unsigned long guest_pmap_npages;
 165
 166         /* Wired host TLB used for the commpage */
 167         int commpage_tlb;
 168 };
 169
 170 #define N_MIPS_COPROC_REGS      32
 171 #define N_MIPS_COPROC_SEL       8
 172
 173 struct mips_coproc {
 174         unsigned long reg[N_MIPS_COPROC_REGS][N_MIPS_COPROC_SEL];
 175 #ifdef CONFIG_KVM_MIPS_DEBUG_COP0_COUNTERS
 176         unsigned long stat[N_MIPS_COPROC_REGS][N_MIPS_COPROC_SEL];
 177 #endif
 178 };
 179
 180 /*
 181  * Coprocessor 0 register names
 182  */
 183 #define MIPS_CP0_TLB_INDEX      0
 184 #define MIPS_CP0_TLB_RANDOM     1
 185 #define MIPS_CP0_TLB_LOW        2
 186 #define MIPS_CP0_TLB_LO0        2
 187 #define MIPS_CP0_TLB_LO1        3
 188 #define MIPS_CP0_TLB_CONTEXT    4
 189 #define MIPS_CP0_TLB_PG_MASK    5
 190 #define MIPS_CP0_TLB_WIRED      6
 191 #define MIPS_CP0_HWRENA         7
 192 #define MIPS_CP0_BAD_VADDR      8
 193 #define MIPS_CP0_COUNT          9
 194 #define MIPS_CP0_TLB_HI         10
 195 #define MIPS_CP0_COMPARE        11
 196 #define MIPS_CP0_STATUS         12
 197 #define MIPS_CP0_CAUSE          13
 198 #define MIPS_CP0_EXC_PC         14
 199 #define MIPS_CP0_PRID           15
 200 #define MIPS_CP0_CONFIG         16
 201 #define MIPS_CP0_LLADDR         17
 202 #define MIPS_CP0_WATCH_LO       18
 203 #define MIPS_CP0_WATCH_HI       19
 204 #define MIPS_CP0_TLB_XCONTEXT   20
 205 #define MIPS_CP0_ECC            26
 206 #define MIPS_CP0_CACHE_ERR      27
 207 #define MIPS_CP0_TAG_LO         28
 208 #define MIPS_CP0_TAG_HI         29
 209 #define MIPS_CP0_ERROR_PC       30
 210 #define MIPS_CP0_DEBUG          23
 211 #define MIPS_CP0_DEPC           24
 212 #define MIPS_CP0_PERFCNT        25
 213 #define MIPS_CP0_ERRCTL         26
 214 #define MIPS_CP0_DATA_LO        28
 215 #define MIPS_CP0_DATA_HI        29
 216 #define MIPS_CP0_DESAVE         31
 217
 218 #define MIPS_CP0_CONFIG_SEL     0
 219 #define MIPS_CP0_CONFIG1_SEL    1
 220 #define MIPS_CP0_CONFIG2_SEL    2
 221 #define MIPS_CP0_CONFIG3_SEL    3
 222 #define MIPS_CP0_CONFIG4_SEL    4
 223 #define MIPS_CP0_CONFIG5_SEL    5
 224
 225 /* Config0 register bits */
 226 #define CP0C0_M                 31
 227 #define CP0C0_K23               28
 228 #define CP0C0_KU                25
 229 #define CP0C0_MDU               20
 230 #define CP0C0_MM                17
 231 #define CP0C0_BM                16
 232 #define CP0C0_BE                15
 233 #define CP0C0_AT                13
 234 #define CP0C0_AR                10
 235 #define CP0C0_MT                7
 236 #define CP0C0_VI                3
 237 #define CP0C0_K0                0
 238
 239 /* Config1 register bits */
 240 #define CP0C1_M                 31
 241 #define CP0C1_MMU               25
 242 #define CP0C1_IS                22
 243 #define CP0C1_IL                19
 244 #define CP0C1_IA                16
 245 #define CP0C1_DS                13
 246 #define CP0C1_DL                10
 247 #define CP0C1_DA                7
 248 #define CP0C1_C2                6
 249 #define CP0C1_MD                5
 250 #define CP0C1_PC                4
 251 #define CP0C1_WR                3
 252 #define CP0C1_CA                2
 253 #define CP0C1_EP                1
 254 #define CP0C1_FP                0
 255
 256 /* Config2 Register bits */
 257 #define CP0C2_M                 31
 258 #define CP0C2_TU                28
 259 #define CP0C2_TS                24
 260 #define CP0C2_TL                20
 261 #define CP0C2_TA                16
 262 #define CP0C2_SU                12
 263 #define CP0C2_SS                8
 264 #define CP0C2_SL                4
 265 #define CP0C2_SA                0
 266
 267 /* Config3 Register bits */
 268 #define CP0C3_M                 31
 269 #define CP0C3_ISA_ON_EXC        16
 270 #define CP0C3_ULRI              13
 271 #define CP0C3_DSPP              10
 272 #define CP0C3_LPA               7
 273 #define CP0C3_VEIC              6
 274 #define CP0C3_VInt              5
 275 #define CP0C3_SP                4
 276 #define CP0C3_MT                2
 277 #define CP0C3_SM                1
 278 #define CP0C3_TL                0
 279
 280 /* MMU types, the first four entries have the same layout as the
 281    CP0C0_MT field.  */
 282 enum mips_mmu_types {
 283         MMU_TYPE_NONE,
 284         MMU_TYPE_R4000,
 285         MMU_TYPE_RESERVED,
 286         MMU_TYPE_FMT,
 287         MMU_TYPE_R3000,
 288         MMU_TYPE_R6000,
 289         MMU_TYPE_R8000
 290 };
 291
 292 /*
 293  * Trap codes
 294  */
 295 #define T_INT                   0       /* Interrupt pending */
 296 #define T_TLB_MOD               1       /* TLB modified fault */
 297 #define T_TLB_LD_MISS           2       /* TLB miss on load or ifetch */
 298 #define T_TLB_ST_MISS           3       /* TLB miss on a store */
 299 #define T_ADDR_ERR_LD           4       /* Address error on a load or ifetch */
 300 #define T_ADDR_ERR_ST           5       /* Address error on a store */
 301 #define T_BUS_ERR_IFETCH        6       /* Bus error on an ifetch */
 302 #define T_BUS_ERR_LD_ST         7       /* Bus error on a load or store */
 303 #define T_SYSCALL               8       /* System call */
 304 #define T_BREAK                 9       /* Breakpoint */
 305 #define T_RES_INST              10      /* Reserved instruction exception */
 306 #define T_COP_UNUSABLE          11      /* Coprocessor unusable */
 307 #define T_OVFLOW                12      /* Arithmetic overflow */
 308
 309 /*
 310  * Trap definitions added for r4000 port.
 311  */
 312 #define T_TRAP                  13      /* Trap instruction */
 313 #define T_VCEI                  14      /* Virtual coherency exception */
 314 #define T_MSAFPE                14      /* MSA floating point exception */
 315 #define T_FPE                   15      /* Floating point exception */
 316 #define T_MSADIS                21      /* MSA disabled exception */
 317 #define T_WATCH                 23      /* Watch address reference */
 318 #define T_VCED                  31      /* Virtual coherency data */
 319
 320 /* Resume Flags */
 321 #define RESUME_FLAG_DR          (1<<0)  /* Reload guest nonvolatile state? */
 322 #define RESUME_FLAG_HOST        (1<<1)  /* Resume host? */
 323
 324 #define RESUME_GUEST            0
 325 #define RESUME_GUEST_DR         RESUME_FLAG_DR
 326 #define RESUME_HOST             RESUME_FLAG_HOST
 327
 328 enum emulation_result {
 329         EMULATE_DONE,           /* no further processing */
 330         EMULATE_DO_MMIO,        /* kvm_run filled with MMIO request */
 331         EMULATE_FAIL,           /* can't emulate this instruction */
 332         EMULATE_WAIT,           /* WAIT instruction */
 333         EMULATE_PRIV_FAIL,
 334 };
 335
 336 #define MIPS3_PG_G      0x00000001 /* Global; ignore ASID if in lo0 & lo1 */
 337 #define MIPS3_PG_V      0x00000002 /* Valid */
 338 #define MIPS3_PG_NV     0x00000000
 339 #define MIPS3_PG_D      0x00000004 /* Dirty */
 340
 341 #define mips3_paddr_to_tlbpfn(x) \
 342         (((unsigned long)(x) >> MIPS3_PG_SHIFT) & MIPS3_PG_FRAME)
 343 #define mips3_tlbpfn_to_paddr(x) \
 344         ((unsigned long)((x) & MIPS3_PG_FRAME) << MIPS3_PG_SHIFT)
 345
 346 #define MIPS3_PG_SHIFT          6
 347 #define MIPS3_PG_FRAME          0x3fffffc0
 348
 349 #define VPN2_MASK               0xffffe000
 350 #define TLB_IS_GLOBAL(x)        (((x).tlb_lo0 & MIPS3_PG_G) &&          \
 351                                  ((x).tlb_lo1 & MIPS3_PG_G))
 352 #define TLB_VPN2(x)             ((x).tlb_hi & VPN2_MASK)
 353 #define TLB_ASID(x)             ((x).tlb_hi & ASID_MASK)
 354 #define TLB_IS_VALID(x, va)     (((va) & (1 << PAGE_SHIFT))             \
 355                                  ? ((x).tlb_lo1 & MIPS3_PG_V)           \
 356                                  : ((x).tlb_lo0 & MIPS3_PG_V))
 357 #define TLB_HI_VPN2_HIT(x, y)   ((TLB_VPN2(x) & ~(x).tlb_mask) ==       \
 358                                  ((y) & VPN2_MASK & ~(x).tlb_mask))
 359 #define TLB_HI_ASID_HIT(x, y)   (TLB_IS_GLOBAL(x) ||                    \
 360                                  TLB_ASID(x) == ((y) & ASID_MASK))
 361
 362 struct kvm_mips_tlb {
 363         long tlb_mask;
 364         long tlb_hi;
 365         long tlb_lo0;
 366         long tlb_lo1;
 367 };
 368
 369 #define KVM_MIPS_FPU_FPU        0x1
 370 #define KVM_MIPS_FPU_MSA        0x2
 371
 372 #define KVM_MIPS_GUEST_TLB_SIZE 64
 373 struct kvm_vcpu_arch {
 374         void *host_ebase, *guest_ebase;
 375         int (*vcpu_run)(struct kvm_run *run, struct kvm_vcpu *vcpu);
 376         unsigned long host_stack;
 377         unsigned long host_gp;
 378
 379         /* Host CP0 registers used when handling exits from guest */
 380         unsigned long host_cp0_badvaddr;
 381         unsigned long host_cp0_cause;
 382         unsigned long host_cp0_epc;
 383         unsigned long host_cp0_entryhi;
 384         uint32_t guest_inst;
 385
 386         /* GPRS */
 387         unsigned long gprs[32];
 388         unsigned long hi;
 389         unsigned long lo;
 390         unsigned long pc;
 391
 392         /* FPU State */
 393         struct mips_fpu_struct fpu;
 394         /* Which FPU state is loaded (KVM_MIPS_FPU_*) */
 395         unsigned int fpu_inuse;
 396
 397         /* COP0 State */
 398         struct mips_coproc *cop0;
 399
 400         /* Host KSEG0 address of the EI/DI offset */
 401         void *kseg0_commpage;
 402
 403         /* Resume PC after MMIO completion */
 404         unsigned long io_pc;
 405         /* GPR used as IO source/target */
 406         u32 io_gpr;
 407
 408         struct hrtimer comparecount_timer;
 409         /* Count timer control KVM register */
 410         uint32_t count_ctl;
 411         /* Count bias from the raw time */
 412         uint32_t count_bias;
 413         /* Frequency of timer in Hz */
 414         uint32_t count_hz;
 415         /* Dynamic nanosecond bias (multiple of count_period) to avoid overflow */
 416         s64 count_dyn_bias;
 417         /* Resume time */
 418         ktime_t count_resume;
 419         /* Period of timer tick in ns */
 420         u64 count_period;
 421
 422         /* Bitmask of exceptions that are pending */
 423         unsigned long pending_exceptions;
 424
 425         /* Bitmask of pending exceptions to be cleared */
 426         unsigned long pending_exceptions_clr;
 427
 428         /* Save/Restore the entryhi register when are are preempted/scheduled back in */
 429         unsigned long preempt_entryhi;
 430
 431         /* S/W Based TLB for guest */
 432         struct kvm_mips_tlb guest_tlb[KVM_MIPS_GUEST_TLB_SIZE];
 433
 434         /* Cached guest kernel/user ASIDs */
 435         uint32_t guest_user_asid[NR_CPUS];
 436         uint32_t guest_kernel_asid[NR_CPUS];
 437         struct mm_struct guest_kernel_mm, guest_user_mm;
 438
 439         int last_sched_cpu;
 440
 441         /* WAIT executed */
 442         int wait;
 443
 444         u8 fpu_enabled;
 445         u8 msa_enabled;
 446 };
 447
 448
 449 #define kvm_read_c0_guest_index(cop0)           (cop0->reg[MIPS_CP0_TLB_INDEX][0])
 450 #define kvm_write_c0_guest_index(cop0, val)     (cop0->reg[MIPS_CP0_TLB_INDEX][0] = val)
 451 #define kvm_read_c0_guest_entrylo0(cop0)        (cop0->reg[MIPS_CP0_TLB_LO0][0])
 452 #define kvm_read_c0_guest_entrylo1(cop0)        (cop0->reg[MIPS_CP0_TLB_LO1][0])
 453 #define kvm_read_c0_guest_context(cop0)         (cop0->reg[MIPS_CP0_TLB_CONTEXT][0])
 454 #define kvm_write_c0_guest_context(cop0, val)   (cop0->reg[MIPS_CP0_TLB_CONTEXT][0] = (val))
 455 #define kvm_read_c0_guest_userlocal(cop0)       (cop0->reg[MIPS_CP0_TLB_CONTEXT][2])
 456 #define kvm_write_c0_guest_userlocal(cop0, val) (cop0->reg[MIPS_CP0_TLB_CONTEXT][2] = (val))
 457 #define kvm_read_c0_guest_pagemask(cop0)        (cop0->reg[MIPS_CP0_TLB_PG_MASK][0])
 458 #define kvm_write_c0_guest_pagemask(cop0, val)  (cop0->reg[MIPS_CP0_TLB_PG_MASK][0] = (val))
 459 #define kvm_read_c0_guest_wired(cop0)           (cop0->reg[MIPS_CP0_TLB_WIRED][0])
 460 #define kvm_write_c0_guest_wired(cop0, val)     (cop0->reg[MIPS_CP0_TLB_WIRED][0] = (val))
 461 #define kvm_read_c0_guest_hwrena(cop0)          (cop0->reg[MIPS_CP0_HWRENA][0])
 462 #define kvm_write_c0_guest_hwrena(cop0, val)    (cop0->reg[MIPS_CP0_HWRENA][0] = (val))
 463 #define kvm_read_c0_guest_badvaddr(cop0)        (cop0->reg[MIPS_CP0_BAD_VADDR][0])
 464 #define kvm_write_c0_guest_badvaddr(cop0, val)  (cop0->reg[MIPS_CP0_BAD_VADDR][0] = (val))
 465 #define kvm_read_c0_guest_count(cop0)           (cop0->reg[MIPS_CP0_COUNT][0])
 466 #define kvm_write_c0_guest_count(cop0, val)     (cop0->reg[MIPS_CP0_COUNT][0] = (val))
 467 #define kvm_read_c0_guest_entryhi(cop0)         (cop0->reg[MIPS_CP0_TLB_HI][0])
 468 #define kvm_write_c0_guest_entryhi(cop0, val)   (cop0->reg[MIPS_CP0_TLB_HI][0] = (val))
 469 #define kvm_read_c0_guest_compare(cop0)         (cop0->reg[MIPS_CP0_COMPARE][0])
 470 #define kvm_write_c0_guest_compare(cop0, val)   (cop0->reg[MIPS_CP0_COMPARE][0] = (val))
 471 #define kvm_read_c0_guest_status(cop0)          (cop0->reg[MIPS_CP0_STATUS][0])
 472 #define kvm_write_c0_guest_status(cop0, val)    (cop0->reg[MIPS_CP0_STATUS][0] = (val))
 473 #define kvm_read_c0_guest_intctl(cop0)          (cop0->reg[MIPS_CP0_STATUS][1])
 474 #define kvm_write_c0_guest_intctl(cop0, val)    (cop0->reg[MIPS_CP0_STATUS][1] = (val))
 475 #define kvm_read_c0_guest_cause(cop0)           (cop0->reg[MIPS_CP0_CAUSE][0])
 476 #define kvm_write_c0_guest_cause(cop0, val)     (cop0->reg[MIPS_CP0_CAUSE][0] = (val))
 477 #define kvm_read_c0_guest_epc(cop0)             (cop0->reg[MIPS_CP0_EXC_PC][0])
 478 #define kvm_write_c0_guest_epc(cop0, val)       (cop0->reg[MIPS_CP0_EXC_PC][0] = (val))
 479 #define kvm_read_c0_guest_prid(cop0)            (cop0->reg[MIPS_CP0_PRID][0])
 480 #define kvm_write_c0_guest_prid(cop0, val)      (cop0->reg[MIPS_CP0_PRID][0] = (val))
 481 #define kvm_read_c0_guest_ebase(cop0)           (cop0->reg[MIPS_CP0_PRID][1])
 482 #define kvm_write_c0_guest_ebase(cop0, val)     (cop0->reg[MIPS_CP0_PRID][1] = (val))
 483 #define kvm_read_c0_guest_config(cop0)          (cop0->reg[MIPS_CP0_CONFIG][0])
 484 #define kvm_read_c0_guest_config1(cop0)         (cop0->reg[MIPS_CP0_CONFIG][1])
 485 #define kvm_read_c0_guest_config2(cop0)         (cop0->reg[MIPS_CP0_CONFIG][2])
 486 #define kvm_read_c0_guest_config3(cop0)         (cop0->reg[MIPS_CP0_CONFIG][3])
 487 #define kvm_read_c0_guest_config4(cop0)         (cop0->reg[MIPS_CP0_CONFIG][4])
 488 #define kvm_read_c0_guest_config5(cop0)         (cop0->reg[MIPS_CP0_CONFIG][5])
 489 #define kvm_read_c0_guest_config7(cop0)         (cop0->reg[MIPS_CP0_CONFIG][7])
 490 #define kvm_write_c0_guest_config(cop0, val)    (cop0->reg[MIPS_CP0_CONFIG][0] = (val))
 491 #define kvm_write_c0_guest_config1(cop0, val)   (cop0->reg[MIPS_CP0_CONFIG][1] = (val))
 492 #define kvm_write_c0_guest_config2(cop0, val)   (cop0->reg[MIPS_CP0_CONFIG][2] = (val))
 493 #define kvm_write_c0_guest_config3(cop0, val)   (cop0->reg[MIPS_CP0_CONFIG][3] = (val))
 494 #define kvm_write_c0_guest_config4(cop0, val)   (cop0->reg[MIPS_CP0_CONFIG][4] = (val))
 495 #define kvm_write_c0_guest_config5(cop0, val)   (cop0->reg[MIPS_CP0_CONFIG][5] = (val))
 496 #define kvm_write_c0_guest_config7(cop0, val)   (cop0->reg[MIPS_CP0_CONFIG][7] = (val))
 497 #define kvm_read_c0_guest_errorepc(cop0)        (cop0->reg[MIPS_CP0_ERROR_PC][0])
 498 #define kvm_write_c0_guest_errorepc(cop0, val)  (cop0->reg[MIPS_CP0_ERROR_PC][0] = (val))
 499
 500 /*
 501  * Some of the guest registers may be modified asynchronously (e.g. from a
 502  * hrtimer callback in hard irq context) and therefore need stronger atomicity
 503  * guarantees than other registers.
 504  */
 505
 506 static inline void _kvm_atomic_set_c0_guest_reg(unsigned long *reg,
 507                                                 unsigned long val)
 508 {
 509         unsigned long temp;
 510         do {
 511                 __asm__ __volatile__(
 512                 "       .set    mips3                           \n"
 513                 "       " __LL "%0, %1                          \n"
 514                 "       or      %0, %2                          \n"
 515                 "       " __SC  "%0, %1                         \n"
 516                 "       .set    mips0                           \n"
 517                 : "=&r" (temp), "+m" (*reg)
 518                 : "r" (val));
 519         } while (unlikely(!temp));
 520 }
 521
 522 static inline void _kvm_atomic_clear_c0_guest_reg(unsigned long *reg,
 523                                                   unsigned long val)
 524 {
 525         unsigned long temp;
 526         do {
 527                 __asm__ __volatile__(
 528                 "       .set    mips3                           \n"
 529                 "       " __LL "%0, %1                          \n"
 530                 "       and     %0, %2                          \n"
 531                 "       " __SC  "%0, %1                         \n"
 532                 "       .set    mips0                           \n"
 533                 : "=&r" (temp), "+m" (*reg)
 534                 : "r" (~val));
 535         } while (unlikely(!temp));
 536 }
 537
 538 static inline void _kvm_atomic_change_c0_guest_reg(unsigned long *reg,
 539                                                    unsigned long change,
 540                                                    unsigned long val)
 541 {
 542         unsigned long temp;
 543         do {
 544                 __asm__ __volatile__(
 545                 "       .set    mips3                           \n"
 546                 "       " __LL "%0, %1                          \n"
 547                 "       and     %0, %2                          \n"
 548                 "       or      %0, %3                          \n"
 549                 "       " __SC  "%0, %1                         \n"
 550                 "       .set    mips0                           \n"
 551                 : "=&r" (temp), "+m" (*reg)
 552                 : "r" (~change), "r" (val & change));
 553         } while (unlikely(!temp));
 554 }
 555
 556 #define kvm_set_c0_guest_status(cop0, val)      (cop0->reg[MIPS_CP0_STATUS][0] |= (val))
 557 #define kvm_clear_c0_guest_status(cop0, val)    (cop0->reg[MIPS_CP0_STATUS][0] &= ~(val))
 558
 559 /* Cause can be modified asynchronously from hardirq hrtimer callback */
 560 #define kvm_set_c0_guest_cause(cop0, val)                               \
 561         _kvm_atomic_set_c0_guest_reg(&cop0->reg[MIPS_CP0_CAUSE][0], val)
 562 #define kvm_clear_c0_guest_cause(cop0, val)                             \
 563         _kvm_atomic_clear_c0_guest_reg(&cop0->reg[MIPS_CP0_CAUSE][0], val)
 564 #define kvm_change_c0_guest_cause(cop0, change, val)                    \
 565         _kvm_atomic_change_c0_guest_reg(&cop0->reg[MIPS_CP0_CAUSE][0],  \
 566                                         change, val)
 567
 568 #define kvm_set_c0_guest_ebase(cop0, val)       (cop0->reg[MIPS_CP0_PRID][1] |= (val))
 569 #define kvm_clear_c0_guest_ebase(cop0, val)     (cop0->reg[MIPS_CP0_PRID][1] &= ~(val))
 570 #define kvm_change_c0_guest_ebase(cop0, change, val)                    \
 571 {                                                                       \
 572         kvm_clear_c0_guest_ebase(cop0, change);                         \
 573         kvm_set_c0_guest_ebase(cop0, ((val) & (change)));               \
 574 }
 575
 576 /* Helpers */
 577
 578 static inline bool kvm_mips_guest_can_have_fpu(struct kvm_vcpu_arch *vcpu)
 579 {
 580         return (!__builtin_constant_p(cpu_has_fpu) || cpu_has_fpu) &&
 581                 vcpu->fpu_enabled;
 582 }
 583
 584 static inline bool kvm_mips_guest_has_fpu(struct kvm_vcpu_arch *vcpu)
 585 {
 586         return kvm_mips_guest_can_have_fpu(vcpu) &&
 587                 kvm_read_c0_guest_config1(vcpu->cop0) & MIPS_CONF1_FP;
 588 }
 589
 590 static inline bool kvm_mips_guest_can_have_msa(struct kvm_vcpu_arch *vcpu)
 591 {
 592         return (!__builtin_constant_p(cpu_has_msa) || cpu_has_msa) &&
 593                 vcpu->msa_enabled;
 594 }
 595
 596 static inline bool kvm_mips_guest_has_msa(struct kvm_vcpu_arch *vcpu)
 597 {
 598         return kvm_mips_guest_can_have_msa(vcpu) &&
 599                 kvm_read_c0_guest_config3(vcpu->cop0) & MIPS_CONF3_MSA;
 600 }
 601
 602 struct kvm_mips_callbacks {
 603         int (*handle_cop_unusable)(struct kvm_vcpu *vcpu);
 604         int (*handle_tlb_mod)(struct kvm_vcpu *vcpu);
 605         int (*handle_tlb_ld_miss)(struct kvm_vcpu *vcpu);
 606         int (*handle_tlb_st_miss)(struct kvm_vcpu *vcpu);
 607         int (*handle_addr_err_st)(struct kvm_vcpu *vcpu);
 608         int (*handle_addr_err_ld)(struct kvm_vcpu *vcpu);
 609         int (*handle_syscall)(struct kvm_vcpu *vcpu);
 610         int (*handle_res_inst)(struct kvm_vcpu *vcpu);
 611         int (*handle_break)(struct kvm_vcpu *vcpu);
 612         int (*handle_trap)(struct kvm_vcpu *vcpu);
 613         int (*handle_msa_fpe)(struct kvm_vcpu *vcpu);
 614         int (*handle_fpe)(struct kvm_vcpu *vcpu);
 615         int (*handle_msa_disabled)(struct kvm_vcpu *vcpu);
 616         int (*vm_init)(struct kvm *kvm);
 617         int (*vcpu_init)(struct kvm_vcpu *vcpu);
 618         int (*vcpu_setup)(struct kvm_vcpu *vcpu);
 619         gpa_t (*gva_to_gpa)(gva_t gva);
 620         void (*queue_timer_int)(struct kvm_vcpu *vcpu);
 621         void (*dequeue_timer_int)(struct kvm_vcpu *vcpu);
 622         void (*queue_io_int)(struct kvm_vcpu *vcpu,
 623                              struct kvm_mips_interrupt *irq);
 624         void (*dequeue_io_int)(struct kvm_vcpu *vcpu,
 625                                struct kvm_mips_interrupt *irq);
 626         int (*irq_deliver)(struct kvm_vcpu *vcpu, unsigned int priority,
 627                            uint32_t cause);
 628         int (*irq_clear)(struct kvm_vcpu *vcpu, unsigned int priority,
 629                          uint32_t cause);
 630         int (*get_one_reg)(struct kvm_vcpu *vcpu,
 631                            const struct kvm_one_reg *reg, s64 *v);
 632         int (*set_one_reg)(struct kvm_vcpu *vcpu,
 633                            const struct kvm_one_reg *reg, s64 v);
 634         int (*vcpu_get_regs)(struct kvm_vcpu *vcpu);
 635         int (*vcpu_set_regs)(struct kvm_vcpu *vcpu);
 636 };
 637 extern struct kvm_mips_callbacks *kvm_mips_callbacks;
 638 int kvm_mips_emulation_init(struct kvm_mips_callbacks **install_callbacks);
 639
 640 /* Debug: dump vcpu state */
 641 int kvm_arch_vcpu_dump_regs(struct kvm_vcpu *vcpu);
 642
 643 /* Trampoline ASM routine to start running in "Guest" context */
 644 extern int __kvm_mips_vcpu_run(struct kvm_run *run, struct kvm_vcpu *vcpu);
 645
 646 /* FPU/MSA context management */
 647 void __kvm_save_fpu(struct kvm_vcpu_arch *vcpu);
 648 void __kvm_restore_fpu(struct kvm_vcpu_arch *vcpu);
 649 void __kvm_restore_fcsr(struct kvm_vcpu_arch *vcpu);
 650 void __kvm_save_msa(struct kvm_vcpu_arch *vcpu);
 651 void __kvm_restore_msa(struct kvm_vcpu_arch *vcpu);
 652 void __kvm_restore_msa_upper(struct kvm_vcpu_arch *vcpu);
 653 void __kvm_restore_msacsr(struct kvm_vcpu_arch *vcpu);
 654 void kvm_own_fpu(struct kvm_vcpu *vcpu);
 655 void kvm_own_msa(struct kvm_vcpu *vcpu);
 656 void kvm_drop_fpu(struct kvm_vcpu *vcpu);
 657 void kvm_lose_fpu(struct kvm_vcpu *vcpu);
 658
 659 /* TLB handling */
 660 uint32_t kvm_get_kernel_asid(struct kvm_vcpu *vcpu);
 661
 662 uint32_t kvm_get_user_asid(struct kvm_vcpu *vcpu);
 663
 664 uint32_t kvm_get_commpage_asid (struct kvm_vcpu *vcpu);
 665
 666 extern int kvm_mips_handle_kseg0_tlb_fault(unsigned long badbaddr,
 667                                            struct kvm_vcpu *vcpu);
 668
 669 extern int kvm_mips_handle_commpage_tlb_fault(unsigned long badvaddr,
 670                                               struct kvm_vcpu *vcpu);
 671
 672 extern int kvm_mips_handle_mapped_seg_tlb_fault(struct kvm_vcpu *vcpu,
 673                                                 struct kvm_mips_tlb *tlb,
 674                                                 unsigned long *hpa0,
 675                                                 unsigned long *hpa1);
 676
 677 extern enum emulation_result kvm_mips_handle_tlbmiss(unsigned long cause,
 678                                                      uint32_t *opc,
 679                                                      struct kvm_run *run,
 680                                                      struct kvm_vcpu *vcpu);
 681
 682 extern enum emulation_result kvm_mips_handle_tlbmod(unsigned long cause,
 683                                                     uint32_t *opc,
 684                                                     struct kvm_run *run,
 685                                                     struct kvm_vcpu *vcpu);
 686
 687 extern void kvm_mips_dump_host_tlbs(void);
 688 extern void kvm_mips_dump_guest_tlbs(struct kvm_vcpu *vcpu);
 689 extern void kvm_mips_flush_host_tlb(int skip_kseg0);
 690 extern int kvm_mips_host_tlb_inv(struct kvm_vcpu *vcpu, unsigned long entryhi);
 691 extern int kvm_mips_host_tlb_inv_index(struct kvm_vcpu *vcpu, int index);
 692
 693 extern int kvm_mips_guest_tlb_lookup(struct kvm_vcpu *vcpu,
 694                                      unsigned long entryhi);
 695 extern int kvm_mips_host_tlb_lookup(struct kvm_vcpu *vcpu, unsigned long vaddr);
 696 extern unsigned long kvm_mips_translate_guest_kseg0_to_hpa(struct kvm_vcpu *vcpu,
 697                                                    unsigned long gva);
 698 extern void kvm_get_new_mmu_context(struct mm_struct *mm, unsigned long cpu,
 699                                     struct kvm_vcpu *vcpu);
 700 extern void kvm_local_flush_tlb_all(void);
 701 extern void kvm_mips_alloc_new_mmu_context(struct kvm_vcpu *vcpu);
 702 extern void kvm_mips_vcpu_load(struct kvm_vcpu *vcpu, int cpu);
 703 extern void kvm_mips_vcpu_put(struct kvm_vcpu *vcpu);
 704
 705 /* Emulation */
 706 uint32_t kvm_get_inst(uint32_t *opc, struct kvm_vcpu *vcpu);
 707 enum emulation_result update_pc(struct kvm_vcpu *vcpu, uint32_t cause);
 708
 709 extern enum emulation_result kvm_mips_emulate_inst(unsigned long cause,
 710                                                    uint32_t *opc,
 711                                                    struct kvm_run *run,
 712                                                    struct kvm_vcpu *vcpu);
 713
 714 extern enum emulation_result kvm_mips_emulate_syscall(unsigned long cause,
 715                                                       uint32_t *opc,
 716                                                       struct kvm_run *run,
 717                                                       struct kvm_vcpu *vcpu);
 718
 719 extern enum emulation_result kvm_mips_emulate_tlbmiss_ld(unsigned long cause,
 720                                                          uint32_t *opc,
 721                                                          struct kvm_run *run,
 722                                                          struct kvm_vcpu *vcpu);
 723
 724 extern enum emulation_result kvm_mips_emulate_tlbinv_ld(unsigned long cause,
 725                                                         uint32_t *opc,
 726                                                         struct kvm_run *run,
 727                                                         struct kvm_vcpu *vcpu);
 728
 729 extern enum emulation_result kvm_mips_emulate_tlbmiss_st(unsigned long cause,
 730                                                          uint32_t *opc,
 731                                                          struct kvm_run *run,
 732                                                          struct kvm_vcpu *vcpu);
 733
 734 extern enum emulation_result kvm_mips_emulate_tlbinv_st(unsigned long cause,
 735                                                         uint32_t *opc,
 736                                                         struct kvm_run *run,
 737                                                         struct kvm_vcpu *vcpu);
 738
 739 extern enum emulation_result kvm_mips_emulate_tlbmod(unsigned long cause,
 740                                                      uint32_t *opc,
 741                                                      struct kvm_run *run,
 742                                                      struct kvm_vcpu *vcpu);
 743
 744 extern enum emulation_result kvm_mips_emulate_fpu_exc(unsigned long cause,
 745                                                       uint32_t *opc,
 746                                                       struct kvm_run *run,
 747                                                       struct kvm_vcpu *vcpu);
 748
 749 extern enum emulation_result kvm_mips_handle_ri(unsigned long cause,
 750                                                 uint32_t *opc,
 751                                                 struct kvm_run *run,
 752                                                 struct kvm_vcpu *vcpu);
 753
 754 extern enum emulation_result kvm_mips_emulate_ri_exc(unsigned long cause,
 755                                                      uint32_t *opc,
 756                                                      struct kvm_run *run,
 757                                                      struct kvm_vcpu *vcpu);
 758
 759 extern enum emulation_result kvm_mips_emulate_bp_exc(unsigned long cause,
 760                                                      uint32_t *opc,
 761                                                      struct kvm_run *run,
 762                                                      struct kvm_vcpu *vcpu);
 763
 764 extern enum emulation_result kvm_mips_emulate_trap_exc(unsigned long cause,
 765                                                        uint32_t *opc,
 766                                                        struct kvm_run *run,
 767                                                        struct kvm_vcpu *vcpu);
 768
 769 extern enum emulation_result kvm_mips_emulate_msafpe_exc(unsigned long cause,
 770                                                          uint32_t *opc,
 771                                                          struct kvm_run *run,
 772                                                          struct kvm_vcpu *vcpu);
 773
 774 extern enum emulation_result kvm_mips_emulate_fpe_exc(unsigned long cause,
 775                                                       uint32_t *opc,
 776                                                       struct kvm_run *run,
 777                                                       struct kvm_vcpu *vcpu);
 778
 779 extern enum emulation_result kvm_mips_emulate_msadis_exc(unsigned long cause,
 780                                                          uint32_t *opc,
 781                                                          struct kvm_run *run,
 782                                                          struct kvm_vcpu *vcpu);
 783
 784 extern enum emulation_result kvm_mips_complete_mmio_load(struct kvm_vcpu *vcpu,
 785                                                          struct kvm_run *run);
 786
 787 uint32_t kvm_mips_read_count(struct kvm_vcpu *vcpu);
 788 void kvm_mips_write_count(struct kvm_vcpu *vcpu, uint32_t count);
 789 void kvm_mips_write_compare(struct kvm_vcpu *vcpu, uint32_t compare, bool ack);
 790 void kvm_mips_init_count(struct kvm_vcpu *vcpu);
 791 int kvm_mips_set_count_ctl(struct kvm_vcpu *vcpu, s64 count_ctl);
 792 int kvm_mips_set_count_resume(struct kvm_vcpu *vcpu, s64 count_resume);
 793 int kvm_mips_set_count_hz(struct kvm_vcpu *vcpu, s64 count_hz);
 794 void kvm_mips_count_enable_cause(struct kvm_vcpu *vcpu);
 795 void kvm_mips_count_disable_cause(struct kvm_vcpu *vcpu);
 796 enum hrtimer_restart kvm_mips_count_timeout(struct kvm_vcpu *vcpu);
 797
 798 enum emulation_result kvm_mips_check_privilege(unsigned long cause,
 799                                                uint32_t *opc,
 800                                                struct kvm_run *run,
 801                                                struct kvm_vcpu *vcpu);
 802
 803 enum emulation_result kvm_mips_emulate_cache(uint32_t inst,
 804                                              uint32_t *opc,
 805                                              uint32_t cause,
 806                                              struct kvm_run *run,
 807                                              struct kvm_vcpu *vcpu);
 808 enum emulation_result kvm_mips_emulate_CP0(uint32_t inst,
 809                                            uint32_t *opc,
 810                                            uint32_t cause,
 811                                            struct kvm_run *run,
 812                                            struct kvm_vcpu *vcpu);
 813 enum emulation_result kvm_mips_emulate_store(uint32_t inst,
 814                                              uint32_t cause,
 815                                              struct kvm_run *run,
 816                                              struct kvm_vcpu *vcpu);
 817 enum emulation_result kvm_mips_emulate_load(uint32_t inst,
 818                                             uint32_t cause,
 819                                             struct kvm_run *run,
 820                                             struct kvm_vcpu *vcpu);
 821
 822 unsigned int kvm_mips_config1_wrmask(struct kvm_vcpu *vcpu);
 823 unsigned int kvm_mips_config3_wrmask(struct kvm_vcpu *vcpu);
 824 unsigned int kvm_mips_config4_wrmask(struct kvm_vcpu *vcpu);
 825 unsigned int kvm_mips_config5_wrmask(struct kvm_vcpu *vcpu);
 826
 827 /* Dynamic binary translation */
 828 extern int kvm_mips_trans_cache_index(uint32_t inst, uint32_t *opc,
 829                                       struct kvm_vcpu *vcpu);
 830 extern int kvm_mips_trans_cache_va(uint32_t inst, uint32_t *opc,
 831                                    struct kvm_vcpu *vcpu);
 832 extern int kvm_mips_trans_mfc0(uint32_t inst, uint32_t *opc,
 833                                struct kvm_vcpu *vcpu);
 834 extern int kvm_mips_trans_mtc0(uint32_t inst, uint32_t *opc,
 835                                struct kvm_vcpu *vcpu);
 836
 837 /* Misc */
 838 extern void kvm_mips_dump_stats(struct kvm_vcpu *vcpu);
 839 extern unsigned long kvm_mips_get_ramsize(struct kvm *kvm);
 840
 841 static inline void kvm_arch_hardware_disable(void) {}
 842 static inline void kvm_arch_hardware_unsetup(void) {}
 843 static inline void kvm_arch_sync_events(struct kvm *kvm) {}
 844 static inline void kvm_arch_free_memslot(struct kvm *kvm,
 845                 struct kvm_memory_slot *free, struct kvm_memory_slot *dont) {}
 846 static inline void kvm_arch_memslots_updated(struct kvm *kvm, struct kvm_memslots *slots) {}
 847 static inline void kvm_arch_flush_shadow_all(struct kvm *kvm) {}
 848 static inline void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
 849                 struct kvm_memory_slot *slot) {}
 850 static inline void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu) {}
 851 static inline void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu) {}
 852 static inline void kvm_arch_vcpu_blocking(struct kvm_vcpu *vcpu) {}
 853 static inline void kvm_arch_vcpu_unblocking(struct kvm_vcpu *vcpu) {}
 854
 855 #endif /* __MIPS_KVM_HOST_H__ */