kernel/arch/mips/cavium-octeon/octeon-platform.c

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * Copyright (C) 2004-2011 Cavium Networks
   7  * Copyright (C) 2008 Wind River Systems
   8  */
   9
  10 #include <linux/delay.h>
  11 #include <linux/init.h>
  12 #include <linux/irq.h>
  13 #include <linux/i2c.h>
  14 #include <linux/usb.h>
  15 #include <linux/dma-mapping.h>
  16 #include <linux/module.h>
  17 #include <linux/mutex.h>
  18 #include <linux/slab.h>
  19 #include <linux/platform_device.h>
  20 #include <linux/of_platform.h>
  21 #include <linux/of_fdt.h>
  22 #include <linux/libfdt.h>
  23 #include <linux/usb/ehci_pdriver.h>
  24 #include <linux/usb/ohci_pdriver.h>
  25
  26 #include <asm/octeon/octeon.h>
  27 #include <asm/octeon/cvmx-rnm-defs.h>
  28 #include <asm/octeon/cvmx-helper.h>
  29 #include <asm/octeon/cvmx-helper-board.h>
  30 #include <asm/octeon/cvmx-uctlx-defs.h>
  31
  32 /* Octeon Random Number Generator.  */
  33 static int __init octeon_rng_device_init(void)
  34 {
  35         struct platform_device *pd;
  36         int ret = 0;
  37
  38         struct resource rng_resources[] = {
  39                 {
  40                         .flags  = IORESOURCE_MEM,
  41                         .start  = XKPHYS_TO_PHYS(CVMX_RNM_CTL_STATUS),
  42                         .end    = XKPHYS_TO_PHYS(CVMX_RNM_CTL_STATUS) + 0xf
  43                 }, {
  44                         .flags  = IORESOURCE_MEM,
  45                         .start  = cvmx_build_io_address(8, 0),
  46                         .end    = cvmx_build_io_address(8, 0) + 0x7
  47                 }
  48         };
  49
  50         pd = platform_device_alloc("octeon_rng", -1);
  51         if (!pd) {
  52                 ret = -ENOMEM;
  53                 goto out;
  54         }
  55
  56         ret = platform_device_add_resources(pd, rng_resources,
  57                                             ARRAY_SIZE(rng_resources));
  58         if (ret)
  59                 goto fail;
  60
  61         ret = platform_device_add(pd);
  62         if (ret)
  63                 goto fail;
  64
  65         return ret;
  66 fail:
  67         platform_device_put(pd);
  68
  69 out:
  70         return ret;
  71 }
  72 device_initcall(octeon_rng_device_init);
  73
  74 #ifdef CONFIG_USB
  75
  76 static DEFINE_MUTEX(octeon2_usb_clocks_mutex);
  77
  78 static int octeon2_usb_clock_start_cnt;
  79
  80 static void octeon2_usb_clocks_start(struct device *dev)
  81 {
  82         u64 div;
  83         union cvmx_uctlx_if_ena if_ena;
  84         union cvmx_uctlx_clk_rst_ctl clk_rst_ctl;
  85         union cvmx_uctlx_uphy_ctl_status uphy_ctl_status;
  86         union cvmx_uctlx_uphy_portx_ctl_status port_ctl_status;
  87         int i;
  88         unsigned long io_clk_64_to_ns;
  89         u32 clock_rate = 12000000;
  90         bool is_crystal_clock = false;
  91
  92
  93         mutex_lock(&octeon2_usb_clocks_mutex);
  94
  95         octeon2_usb_clock_start_cnt++;
  96         if (octeon2_usb_clock_start_cnt != 1)
  97                 goto exit;
  98
  99         io_clk_64_to_ns = 64000000000ull / octeon_get_io_clock_rate();
 100
 101         if (dev->of_node) {
 102                 struct device_node *uctl_node;
 103                 const char *clock_type;
 104
 105                 uctl_node = of_get_parent(dev->of_node);
 106                 if (!uctl_node) {
 107                         dev_err(dev, "No UCTL device node\n");
 108                         goto exit;
 109                 }
 110                 i = of_property_read_u32(uctl_node,
 111                                          "refclk-frequency", &clock_rate);
 112                 if (i) {
 113                         dev_err(dev, "No UCTL \"refclk-frequency\"\n");
 114                         goto exit;
 115                 }
 116                 i = of_property_read_string(uctl_node,
 117                                             "refclk-type", &clock_type);
 118
 119                 if (!i && strcmp("crystal", clock_type) == 0)
 120                         is_crystal_clock = true;
 121         }
 122
 123         /*
 124          * Step 1: Wait for voltages stable.  That surely happened
 125          * before starting the kernel.
 126          *
 127          * Step 2: Enable  SCLK of UCTL by writing UCTL0_IF_ENA[EN] = 1
 128          */
 129         if_ena.u64 = 0;
 130         if_ena.s.en = 1;
 131         cvmx_write_csr(CVMX_UCTLX_IF_ENA(0), if_ena.u64);
 132
 133         /* Step 3: Configure the reference clock, PHY, and HCLK */
 134         clk_rst_ctl.u64 = cvmx_read_csr(CVMX_UCTLX_CLK_RST_CTL(0));
 135
 136         /*
 137          * If the UCTL looks like it has already been started, skip
 138          * the initialization, otherwise bus errors are obtained.
 139          */
 140         if (clk_rst_ctl.s.hrst)
 141                 goto end_clock;
 142         /* 3a */
 143         clk_rst_ctl.s.p_por = 1;
 144         clk_rst_ctl.s.hrst = 0;
 145         clk_rst_ctl.s.p_prst = 0;
 146         clk_rst_ctl.s.h_clkdiv_rst = 0;
 147         clk_rst_ctl.s.o_clkdiv_rst = 0;
 148         clk_rst_ctl.s.h_clkdiv_en = 0;
 149         clk_rst_ctl.s.o_clkdiv_en = 0;
 150         cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64);
 151
 152         /* 3b */
 153         clk_rst_ctl.s.p_refclk_sel = is_crystal_clock ? 0 : 1;
 154         switch (clock_rate) {
 155         default:
 156                 pr_err("Invalid UCTL clock rate of %u, using 12000000 instead\n",
 157                         clock_rate);
 158                 /* Fall through */
 159         case 12000000:
 160                 clk_rst_ctl.s.p_refclk_div = 0;
 161                 break;
 162         case 24000000:
 163                 clk_rst_ctl.s.p_refclk_div = 1;
 164                 break;
 165         case 48000000:
 166                 clk_rst_ctl.s.p_refclk_div = 2;
 167                 break;
 168         }
 169         cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64);
 170
 171         /* 3c */
 172         div = octeon_get_io_clock_rate() / 130000000ull;
 173
 174         switch (div) {
 175         case 0:
 176                 div = 1;
 177                 break;
 178         case 1:
 179         case 2:
 180         case 3:
 181         case 4:
 182                 break;
 183         case 5:
 184                 div = 4;
 185                 break;
 186         case 6:
 187         case 7:
 188                 div = 6;
 189                 break;
 190         case 8:
 191         case 9:
 192         case 10:
 193         case 11:
 194                 div = 8;
 195                 break;
 196         default:
 197                 div = 12;
 198                 break;
 199         }
 200         clk_rst_ctl.s.h_div = div;
 201         cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64);
 202         /* Read it back, */
 203         clk_rst_ctl.u64 = cvmx_read_csr(CVMX_UCTLX_CLK_RST_CTL(0));
 204         clk_rst_ctl.s.h_clkdiv_en = 1;
 205         cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64);
 206         /* 3d */
 207         clk_rst_ctl.s.h_clkdiv_rst = 1;
 208         cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64);
 209
 210         /* 3e: delay 64 io clocks */
 211         ndelay(io_clk_64_to_ns);
 212
 213         /*
 214          * Step 4: Program the power-on reset field in the UCTL
 215          * clock-reset-control register.
 216          */
 217         clk_rst_ctl.s.p_por = 0;
 218         cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64);
 219
 220         /* Step 5:    Wait 1 ms for the PHY clock to start. */
 221         mdelay(1);
 222
 223         /*
 224          * Step 6: Program the reset input from automatic test
 225          * equipment field in the UPHY CSR
 226          */
 227         uphy_ctl_status.u64 = cvmx_read_csr(CVMX_UCTLX_UPHY_CTL_STATUS(0));
 228         uphy_ctl_status.s.ate_reset = 1;
 229         cvmx_write_csr(CVMX_UCTLX_UPHY_CTL_STATUS(0), uphy_ctl_status.u64);
 230
 231         /* Step 7: Wait for at least 10ns. */
 232         ndelay(10);
 233
 234         /* Step 8: Clear the ATE_RESET field in the UPHY CSR. */
 235         uphy_ctl_status.s.ate_reset = 0;
 236         cvmx_write_csr(CVMX_UCTLX_UPHY_CTL_STATUS(0), uphy_ctl_status.u64);
 237
 238         /*
 239          * Step 9: Wait for at least 20ns for UPHY to output PHY clock
 240          * signals and OHCI_CLK48
 241          */
 242         ndelay(20);
 243
 244         /* Step 10: Configure the OHCI_CLK48 and OHCI_CLK12 clocks. */
 245         /* 10a */
 246         clk_rst_ctl.s.o_clkdiv_rst = 1;
 247         cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64);
 248
 249         /* 10b */
 250         clk_rst_ctl.s.o_clkdiv_en = 1;
 251         cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64);
 252
 253         /* 10c */
 254         ndelay(io_clk_64_to_ns);
 255
 256         /*
 257          * Step 11: Program the PHY reset field:
 258          * UCTL0_CLK_RST_CTL[P_PRST] = 1
 259          */
 260         clk_rst_ctl.s.p_prst = 1;
 261         cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64);
 262
 263         /* Step 12: Wait 1 uS. */
 264         udelay(1);
 265
 266         /* Step 13: Program the HRESET_N field: UCTL0_CLK_RST_CTL[HRST] = 1 */
 267         clk_rst_ctl.s.hrst = 1;
 268         cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64);
 269
 270 end_clock:
 271         /* Now we can set some other registers.  */
 272
 273         for (i = 0; i <= 1; i++) {
 274                 port_ctl_status.u64 =
 275                         cvmx_read_csr(CVMX_UCTLX_UPHY_PORTX_CTL_STATUS(i, 0));
 276                 /* Set txvreftune to 15 to obtain compliant 'eye' diagram. */
 277                 port_ctl_status.s.txvreftune = 15;
 278                 port_ctl_status.s.txrisetune = 1;
 279                 port_ctl_status.s.txpreemphasistune = 1;
 280                 cvmx_write_csr(CVMX_UCTLX_UPHY_PORTX_CTL_STATUS(i, 0),
 281                                port_ctl_status.u64);
 282         }
 283
 284         /* Set uSOF cycle period to 60,000 bits. */
 285         cvmx_write_csr(CVMX_UCTLX_EHCI_FLA(0), 0x20ull);
 286 exit:
 287         mutex_unlock(&octeon2_usb_clocks_mutex);
 288 }
 289
 290 static void octeon2_usb_clocks_stop(void)
 291 {
 292         mutex_lock(&octeon2_usb_clocks_mutex);
 293         octeon2_usb_clock_start_cnt--;
 294         mutex_unlock(&octeon2_usb_clocks_mutex);
 295 }
 296
 297 static int octeon_ehci_power_on(struct platform_device *pdev)
 298 {
 299         octeon2_usb_clocks_start(&pdev->dev);
 300         return 0;
 301 }
 302
 303 static void octeon_ehci_power_off(struct platform_device *pdev)
 304 {
 305         octeon2_usb_clocks_stop();
 306 }
 307
 308 static struct usb_ehci_pdata octeon_ehci_pdata = {
 309         /* Octeon EHCI matches CPU endianness. */
 310 #ifdef __BIG_ENDIAN
 311         .big_endian_mmio        = 1,
 312 #endif
 313         .dma_mask_64    = 1,
 314         .power_on       = octeon_ehci_power_on,
 315         .power_off      = octeon_ehci_power_off,
 316 };
 317
 318 static void __init octeon_ehci_hw_start(struct device *dev)
 319 {
 320         union cvmx_uctlx_ehci_ctl ehci_ctl;
 321
 322         octeon2_usb_clocks_start(dev);
 323
 324         ehci_ctl.u64 = cvmx_read_csr(CVMX_UCTLX_EHCI_CTL(0));
 325         /* Use 64-bit addressing. */
 326         ehci_ctl.s.ehci_64b_addr_en = 1;
 327         ehci_ctl.s.l2c_addr_msb = 0;
 328 #ifdef __BIG_ENDIAN
 329         ehci_ctl.s.l2c_buff_emod = 1; /* Byte swapped. */
 330         ehci_ctl.s.l2c_desc_emod = 1; /* Byte swapped. */
 331 #else
 332         ehci_ctl.s.l2c_buff_emod = 0; /* not swapped. */
 333         ehci_ctl.s.l2c_desc_emod = 0; /* not swapped. */
 334         ehci_ctl.s.inv_reg_a2 = 1;
 335 #endif
 336         cvmx_write_csr(CVMX_UCTLX_EHCI_CTL(0), ehci_ctl.u64);
 337
 338         octeon2_usb_clocks_stop();
 339 }
 340
 341 static int __init octeon_ehci_device_init(void)
 342 {
 343         struct platform_device *pd;
 344         struct device_node *ehci_node;
 345         int ret = 0;
 346
 347         ehci_node = of_find_node_by_name(NULL, "ehci");
 348         if (!ehci_node)
 349                 return 0;
 350
 351         pd = of_find_device_by_node(ehci_node);
 352         if (!pd)
 353                 return 0;
 354
 355         pd->dev.platform_data = &octeon_ehci_pdata;
 356         octeon_ehci_hw_start(&pd->dev);
 357
 358         return ret;
 359 }
 360 device_initcall(octeon_ehci_device_init);
 361
 362 static int octeon_ohci_power_on(struct platform_device *pdev)
 363 {
 364         octeon2_usb_clocks_start(&pdev->dev);
 365         return 0;
 366 }
 367
 368 static void octeon_ohci_power_off(struct platform_device *pdev)
 369 {
 370         octeon2_usb_clocks_stop();
 371 }
 372
 373 static struct usb_ohci_pdata octeon_ohci_pdata = {
 374         /* Octeon OHCI matches CPU endianness. */
 375 #ifdef __BIG_ENDIAN
 376         .big_endian_mmio        = 1,
 377 #endif
 378         .power_on       = octeon_ohci_power_on,
 379         .power_off      = octeon_ohci_power_off,
 380 };
 381
 382 static void __init octeon_ohci_hw_start(struct device *dev)
 383 {
 384         union cvmx_uctlx_ohci_ctl ohci_ctl;
 385
 386         octeon2_usb_clocks_start(dev);
 387
 388         ohci_ctl.u64 = cvmx_read_csr(CVMX_UCTLX_OHCI_CTL(0));
 389         ohci_ctl.s.l2c_addr_msb = 0;
 390 #ifdef __BIG_ENDIAN
 391         ohci_ctl.s.l2c_buff_emod = 1; /* Byte swapped. */
 392         ohci_ctl.s.l2c_desc_emod = 1; /* Byte swapped. */
 393 #else
 394         ohci_ctl.s.l2c_buff_emod = 0; /* not swapped. */
 395         ohci_ctl.s.l2c_desc_emod = 0; /* not swapped. */
 396         ohci_ctl.s.inv_reg_a2 = 1;
 397 #endif
 398         cvmx_write_csr(CVMX_UCTLX_OHCI_CTL(0), ohci_ctl.u64);
 399
 400         octeon2_usb_clocks_stop();
 401 }
 402
 403 static int __init octeon_ohci_device_init(void)
 404 {
 405         struct platform_device *pd;
 406         struct device_node *ohci_node;
 407         int ret = 0;
 408
 409         ohci_node = of_find_node_by_name(NULL, "ohci");
 410         if (!ohci_node)
 411                 return 0;
 412
 413         pd = of_find_device_by_node(ohci_node);
 414         if (!pd)
 415                 return 0;
 416
 417         pd->dev.platform_data = &octeon_ohci_pdata;
 418         octeon_ohci_hw_start(&pd->dev);
 419
 420         return ret;
 421 }
 422 device_initcall(octeon_ohci_device_init);
 423
 424 #endif /* CONFIG_USB */
 425
 426
 427 static struct of_device_id __initdata octeon_ids[] = {
 428         { .compatible = "simple-bus", },
 429         { .compatible = "cavium,octeon-6335-uctl", },
 430         { .compatible = "cavium,octeon-5750-usbn", },
 431         { .compatible = "cavium,octeon-3860-bootbus", },
 432         { .compatible = "cavium,mdio-mux", },
 433         { .compatible = "gpio-leds", },
 434         {},
 435 };
 436
 437 static bool __init octeon_has_88e1145(void)
 438 {
 439         return !OCTEON_IS_MODEL(OCTEON_CN52XX) &&
 440                !OCTEON_IS_MODEL(OCTEON_CN6XXX) &&
 441                !OCTEON_IS_MODEL(OCTEON_CN56XX);
 442 }
 443
 444 static void __init octeon_fdt_set_phy(int eth, int phy_addr)
 445 {
 446         const __be32 *phy_handle;
 447         const __be32 *alt_phy_handle;
 448         const __be32 *reg;
 449         u32 phandle;
 450         int phy;
 451         int alt_phy;
 452         const char *p;
 453         int current_len;
 454         char new_name[20];
 455
 456         phy_handle = fdt_getprop(initial_boot_params, eth, "phy-handle", NULL);
 457         if (!phy_handle)
 458                 return;
 459
 460         phandle = be32_to_cpup(phy_handle);
 461         phy = fdt_node_offset_by_phandle(initial_boot_params, phandle);
 462
 463         alt_phy_handle = fdt_getprop(initial_boot_params, eth, "cavium,alt-phy-handle", NULL);
 464         if (alt_phy_handle) {
 465                 u32 alt_phandle = be32_to_cpup(alt_phy_handle);
 466                 alt_phy = fdt_node_offset_by_phandle(initial_boot_params, alt_phandle);
 467         } else {
 468                 alt_phy = -1;
 469         }
 470
 471         if (phy_addr < 0 || phy < 0) {
 472                 /* Delete the PHY things */
 473                 fdt_nop_property(initial_boot_params, eth, "phy-handle");
 474                 /* This one may fail */
 475                 fdt_nop_property(initial_boot_params, eth, "cavium,alt-phy-handle");
 476                 if (phy >= 0)
 477                         fdt_nop_node(initial_boot_params, phy);
 478                 if (alt_phy >= 0)
 479                         fdt_nop_node(initial_boot_params, alt_phy);
 480                 return;
 481         }
 482
 483         if (phy_addr >= 256 && alt_phy > 0) {
 484                 const struct fdt_property *phy_prop;
 485                 struct fdt_property *alt_prop;
 486                 u32 phy_handle_name;
 487
 488                 /* Use the alt phy node instead.*/
 489                 phy_prop = fdt_get_property(initial_boot_params, eth, "phy-handle", NULL);
 490                 phy_handle_name = phy_prop->nameoff;
 491                 fdt_nop_node(initial_boot_params, phy);
 492                 fdt_nop_property(initial_boot_params, eth, "phy-handle");
 493                 alt_prop = fdt_get_property_w(initial_boot_params, eth, "cavium,alt-phy-handle", NULL);
 494                 alt_prop->nameoff = phy_handle_name;
 495                 phy = alt_phy;
 496         }
 497
 498         phy_addr &= 0xff;
 499
 500         if (octeon_has_88e1145()) {
 501                 fdt_nop_property(initial_boot_params, phy, "marvell,reg-init");
 502                 memset(new_name, 0, sizeof(new_name));
 503                 strcpy(new_name, "marvell,88e1145");
 504                 p = fdt_getprop(initial_boot_params, phy, "compatible",
 505                                 &current_len);
 506                 if (p && current_len >= strlen(new_name))
 507                         fdt_setprop_inplace(initial_boot_params, phy,
 508                                         "compatible", new_name, current_len);
 509         }
 510
 511         reg = fdt_getprop(initial_boot_params, phy, "reg", NULL);
 512         if (phy_addr == be32_to_cpup(reg))
 513                 return;
 514
 515         fdt_setprop_inplace_cell(initial_boot_params, phy, "reg", phy_addr);
 516
 517         snprintf(new_name, sizeof(new_name), "ethernet-phy@%x", phy_addr);
 518
 519         p = fdt_get_name(initial_boot_params, phy, &current_len);
 520         if (p && current_len == strlen(new_name))
 521                 fdt_set_name(initial_boot_params, phy, new_name);
 522         else
 523                 pr_err("Error: could not rename ethernet phy: <%s>", p);
 524 }
 525
 526 static void __init octeon_fdt_set_mac_addr(int n, u64 *pmac)
 527 {
 528         u8 new_mac[6];
 529         u64 mac = *pmac;
 530         int r;
 531
 532         new_mac[0] = (mac >> 40) & 0xff;
 533         new_mac[1] = (mac >> 32) & 0xff;
 534         new_mac[2] = (mac >> 24) & 0xff;
 535         new_mac[3] = (mac >> 16) & 0xff;
 536         new_mac[4] = (mac >> 8) & 0xff;
 537         new_mac[5] = mac & 0xff;
 538
 539         r = fdt_setprop_inplace(initial_boot_params, n, "local-mac-address",
 540                                 new_mac, sizeof(new_mac));
 541
 542         if (r) {
 543                 pr_err("Setting \"local-mac-address\" failed %d", r);
 544                 return;
 545         }
 546         *pmac = mac + 1;
 547 }
 548
 549 static void __init octeon_fdt_rm_ethernet(int node)
 550 {
 551         const __be32 *phy_handle;
 552
 553         phy_handle = fdt_getprop(initial_boot_params, node, "phy-handle", NULL);
 554         if (phy_handle) {
 555                 u32 ph = be32_to_cpup(phy_handle);
 556                 int p = fdt_node_offset_by_phandle(initial_boot_params, ph);
 557                 if (p >= 0)
 558                         fdt_nop_node(initial_boot_params, p);
 559         }
 560         fdt_nop_node(initial_boot_params, node);
 561 }
 562
 563 static void __init octeon_fdt_pip_port(int iface, int i, int p, int max, u64 *pmac)
 564 {
 565         char name_buffer[20];
 566         int eth;
 567         int phy_addr;
 568         int ipd_port;
 569
 570         snprintf(name_buffer, sizeof(name_buffer), "ethernet@%x", p);
 571         eth = fdt_subnode_offset(initial_boot_params, iface, name_buffer);
 572         if (eth < 0)
 573                 return;
 574         if (p > max) {
 575                 pr_debug("Deleting port %x:%x\n", i, p);
 576                 octeon_fdt_rm_ethernet(eth);
 577                 return;
 578         }
 579         if (OCTEON_IS_MODEL(OCTEON_CN68XX))
 580                 ipd_port = (0x100 * i) + (0x10 * p) + 0x800;
 581         else
 582                 ipd_port = 16 * i + p;
 583
 584         phy_addr = cvmx_helper_board_get_mii_address(ipd_port);
 585         octeon_fdt_set_phy(eth, phy_addr);
 586         octeon_fdt_set_mac_addr(eth, pmac);
 587 }
 588
 589 static void __init octeon_fdt_pip_iface(int pip, int idx, u64 *pmac)
 590 {
 591         char name_buffer[20];
 592         int iface;
 593         int p;
 594         int count = 0;
 595
 596         snprintf(name_buffer, sizeof(name_buffer), "interface@%d", idx);
 597         iface = fdt_subnode_offset(initial_boot_params, pip, name_buffer);
 598         if (iface < 0)
 599                 return;
 600
 601         if (cvmx_helper_interface_enumerate(idx) == 0)
 602                 count = cvmx_helper_ports_on_interface(idx);
 603
 604         for (p = 0; p < 16; p++)
 605                 octeon_fdt_pip_port(iface, idx, p, count - 1, pmac);
 606 }
 607
 608 int __init octeon_prune_device_tree(void)
 609 {
 610         int i, max_port, uart_mask;
 611         const char *pip_path;
 612         const char *alias_prop;
 613         char name_buffer[20];
 614         int aliases;
 615         u64 mac_addr_base;
 616
 617         if (fdt_check_header(initial_boot_params))
 618                 panic("Corrupt Device Tree.");
 619
 620         aliases = fdt_path_offset(initial_boot_params, "/aliases");
 621         if (aliases < 0) {
 622                 pr_err("Error: No /aliases node in device tree.");
 623                 return -EINVAL;
 624         }
 625
 626
 627         mac_addr_base =
 628                 ((octeon_bootinfo->mac_addr_base[0] & 0xffull)) << 40 |
 629                 ((octeon_bootinfo->mac_addr_base[1] & 0xffull)) << 32 |
 630                 ((octeon_bootinfo->mac_addr_base[2] & 0xffull)) << 24 |
 631                 ((octeon_bootinfo->mac_addr_base[3] & 0xffull)) << 16 |
 632                 ((octeon_bootinfo->mac_addr_base[4] & 0xffull)) << 8 |
 633                 (octeon_bootinfo->mac_addr_base[5] & 0xffull);
 634
 635         if (OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN63XX))
 636                 max_port = 2;
 637         else if (OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN68XX))
 638                 max_port = 1;
 639         else
 640                 max_port = 0;
 641
 642         if (octeon_bootinfo->board_type == CVMX_BOARD_TYPE_NIC10E)
 643                 max_port = 0;
 644
 645         for (i = 0; i < 2; i++) {
 646                 int mgmt;
 647                 snprintf(name_buffer, sizeof(name_buffer),
 648                          "mix%d", i);
 649                 alias_prop = fdt_getprop(initial_boot_params, aliases,
 650                                         name_buffer, NULL);
 651                 if (alias_prop) {
 652                         mgmt = fdt_path_offset(initial_boot_params, alias_prop);
 653                         if (mgmt < 0)
 654                                 continue;
 655                         if (i >= max_port) {
 656                                 pr_debug("Deleting mix%d\n", i);
 657                                 octeon_fdt_rm_ethernet(mgmt);
 658                                 fdt_nop_property(initial_boot_params, aliases,
 659                                                  name_buffer);
 660                         } else {
 661                                 int phy_addr = cvmx_helper_board_get_mii_address(CVMX_HELPER_BOARD_MGMT_IPD_PORT + i);
 662                                 octeon_fdt_set_phy(mgmt, phy_addr);
 663                                 octeon_fdt_set_mac_addr(mgmt, &mac_addr_base);
 664                         }
 665                 }
 666         }
 667
 668         pip_path = fdt_getprop(initial_boot_params, aliases, "pip", NULL);
 669         if (pip_path) {
 670                 int pip = fdt_path_offset(initial_boot_params, pip_path);
 671                 if (pip  >= 0)
 672                         for (i = 0; i <= 4; i++)
 673                                 octeon_fdt_pip_iface(pip, i, &mac_addr_base);
 674         }
 675
 676         /* I2C */
 677         if (OCTEON_IS_MODEL(OCTEON_CN52XX) ||
 678             OCTEON_IS_MODEL(OCTEON_CN63XX) ||
 679             OCTEON_IS_MODEL(OCTEON_CN68XX) ||
 680             OCTEON_IS_MODEL(OCTEON_CN56XX))
 681                 max_port = 2;
 682         else
 683                 max_port = 1;
 684
 685         for (i = 0; i < 2; i++) {
 686                 int i2c;
 687                 snprintf(name_buffer, sizeof(name_buffer),
 688                          "twsi%d", i);
 689                 alias_prop = fdt_getprop(initial_boot_params, aliases,
 690                                         name_buffer, NULL);
 691
 692                 if (alias_prop) {
 693                         i2c = fdt_path_offset(initial_boot_params, alias_prop);
 694                         if (i2c < 0)
 695                                 continue;
 696                         if (i >= max_port) {
 697                                 pr_debug("Deleting twsi%d\n", i);
 698                                 fdt_nop_node(initial_boot_params, i2c);
 699                                 fdt_nop_property(initial_boot_params, aliases,
 700                                                  name_buffer);
 701                         }
 702                 }
 703         }
 704
 705         /* SMI/MDIO */
 706         if (OCTEON_IS_MODEL(OCTEON_CN68XX))
 707                 max_port = 4;
 708         else if (OCTEON_IS_MODEL(OCTEON_CN52XX) ||
 709                  OCTEON_IS_MODEL(OCTEON_CN63XX) ||
 710                  OCTEON_IS_MODEL(OCTEON_CN56XX))
 711                 max_port = 2;
 712         else
 713                 max_port = 1;
 714
 715         for (i = 0; i < 2; i++) {
 716                 int i2c;
 717                 snprintf(name_buffer, sizeof(name_buffer),
 718                          "smi%d", i);
 719                 alias_prop = fdt_getprop(initial_boot_params, aliases,
 720                                         name_buffer, NULL);
 721
 722                 if (alias_prop) {
 723                         i2c = fdt_path_offset(initial_boot_params, alias_prop);
 724                         if (i2c < 0)
 725                                 continue;
 726                         if (i >= max_port) {
 727                                 pr_debug("Deleting smi%d\n", i);
 728                                 fdt_nop_node(initial_boot_params, i2c);
 729                                 fdt_nop_property(initial_boot_params, aliases,
 730                                                  name_buffer);
 731                         }
 732                 }
 733         }
 734
 735         /* Serial */
 736         uart_mask = 3;
 737
 738         /* Right now CN52XX is the only chip with a third uart */
 739         if (OCTEON_IS_MODEL(OCTEON_CN52XX))
 740                 uart_mask |= 4; /* uart2 */
 741
 742         for (i = 0; i < 3; i++) {
 743                 int uart;
 744                 snprintf(name_buffer, sizeof(name_buffer),
 745                          "uart%d", i);
 746                 alias_prop = fdt_getprop(initial_boot_params, aliases,
 747                                         name_buffer, NULL);
 748
 749                 if (alias_prop) {
 750                         uart = fdt_path_offset(initial_boot_params, alias_prop);
 751                         if (uart_mask & (1 << i)) {
 752                                 __be32 f;
 753
 754                                 f = cpu_to_be32(octeon_get_io_clock_rate());
 755                                 fdt_setprop_inplace(initial_boot_params,
 756                                                     uart, "clock-frequency",
 757                                                     &f, sizeof(f));
 758                                 continue;
 759                         }
 760                         pr_debug("Deleting uart%d\n", i);
 761                         fdt_nop_node(initial_boot_params, uart);
 762                         fdt_nop_property(initial_boot_params, aliases,
 763                                          name_buffer);
 764                 }
 765         }
 766
 767         /* Compact Flash */
 768         alias_prop = fdt_getprop(initial_boot_params, aliases,
 769                                  "cf0", NULL);
 770         if (alias_prop) {
 771                 union cvmx_mio_boot_reg_cfgx mio_boot_reg_cfg;
 772                 unsigned long base_ptr, region_base, region_size;
 773                 unsigned long region1_base = 0;
 774                 unsigned long region1_size = 0;
 775                 int cs, bootbus;
 776                 bool is_16bit = false;
 777                 bool is_true_ide = false;
 778                 __be32 new_reg[6];
 779                 __be32 *ranges;
 780                 int len;
 781
 782                 int cf = fdt_path_offset(initial_boot_params, alias_prop);
 783                 base_ptr = 0;
 784                 if (octeon_bootinfo->major_version == 1
 785                         && octeon_bootinfo->minor_version >= 1) {
 786                         if (octeon_bootinfo->compact_flash_common_base_addr)
 787                                 base_ptr = octeon_bootinfo->compact_flash_common_base_addr;
 788                 } else {
 789                         base_ptr = 0x1d000800;
 790                 }
 791
 792                 if (!base_ptr)
 793                         goto no_cf;
 794
 795                 /* Find CS0 region. */
 796                 for (cs = 0; cs < 8; cs++) {
 797                         mio_boot_reg_cfg.u64 = cvmx_read_csr(CVMX_MIO_BOOT_REG_CFGX(cs));
 798                         region_base = mio_boot_reg_cfg.s.base << 16;
 799                         region_size = (mio_boot_reg_cfg.s.size + 1) << 16;
 800                         if (mio_boot_reg_cfg.s.en && base_ptr >= region_base
 801                                 && base_ptr < region_base + region_size) {
 802                                 is_16bit = mio_boot_reg_cfg.s.width;
 803                                 break;
 804                         }
 805                 }
 806                 if (cs >= 7) {
 807                         /* cs and cs + 1 are CS0 and CS1, both must be less than 8. */
 808                         goto no_cf;
 809                 }
 810
 811                 if (!(base_ptr & 0xfffful)) {
 812                         /*
 813                          * Boot loader signals availability of DMA (true_ide
 814                          * mode) by setting low order bits of base_ptr to
 815                          * zero.
 816                          */
 817
 818                         /* Asume that CS1 immediately follows. */
 819                         mio_boot_reg_cfg.u64 =
 820                                 cvmx_read_csr(CVMX_MIO_BOOT_REG_CFGX(cs + 1));
 821                         region1_base = mio_boot_reg_cfg.s.base << 16;
 822                         region1_size = (mio_boot_reg_cfg.s.size + 1) << 16;
 823                         if (!mio_boot_reg_cfg.s.en)
 824                                 goto no_cf;
 825                         is_true_ide = true;
 826
 827                 } else {
 828                         fdt_nop_property(initial_boot_params, cf, "cavium,true-ide");
 829                         fdt_nop_property(initial_boot_params, cf, "cavium,dma-engine-handle");
 830                         if (!is_16bit) {
 831                                 __be32 width = cpu_to_be32(8);
 832                                 fdt_setprop_inplace(initial_boot_params, cf,
 833                                                 "cavium,bus-width", &width, sizeof(width));
 834                         }
 835                 }
 836                 new_reg[0] = cpu_to_be32(cs);
 837                 new_reg[1] = cpu_to_be32(0);
 838                 new_reg[2] = cpu_to_be32(0x10000);
 839                 new_reg[3] = cpu_to_be32(cs + 1);
 840                 new_reg[4] = cpu_to_be32(0);
 841                 new_reg[5] = cpu_to_be32(0x10000);
 842                 fdt_setprop_inplace(initial_boot_params, cf,
 843                                     "reg",  new_reg, sizeof(new_reg));
 844
 845                 bootbus = fdt_parent_offset(initial_boot_params, cf);
 846                 if (bootbus < 0)
 847                         goto no_cf;
 848                 ranges = fdt_getprop_w(initial_boot_params, bootbus, "ranges", &len);
 849                 if (!ranges || len < (5 * 8 * sizeof(__be32)))
 850                         goto no_cf;
 851
 852                 ranges[(cs * 5) + 2] = cpu_to_be32(region_base >> 32);
 853                 ranges[(cs * 5) + 3] = cpu_to_be32(region_base & 0xffffffff);
 854                 ranges[(cs * 5) + 4] = cpu_to_be32(region_size);
 855                 if (is_true_ide) {
 856                         cs++;
 857                         ranges[(cs * 5) + 2] = cpu_to_be32(region1_base >> 32);
 858                         ranges[(cs * 5) + 3] = cpu_to_be32(region1_base & 0xffffffff);
 859                         ranges[(cs * 5) + 4] = cpu_to_be32(region1_size);
 860                 }
 861                 goto end_cf;
 862 no_cf:
 863                 fdt_nop_node(initial_boot_params, cf);
 864
 865 end_cf:
 866                 ;
 867         }
 868
 869         /* 8 char LED */
 870         alias_prop = fdt_getprop(initial_boot_params, aliases,
 871                                  "led0", NULL);
 872         if (alias_prop) {
 873                 union cvmx_mio_boot_reg_cfgx mio_boot_reg_cfg;
 874                 unsigned long base_ptr, region_base, region_size;
 875                 int cs, bootbus;
 876                 __be32 new_reg[6];
 877                 __be32 *ranges;
 878                 int len;
 879                 int led = fdt_path_offset(initial_boot_params, alias_prop);
 880
 881                 base_ptr = octeon_bootinfo->led_display_base_addr;
 882                 if (base_ptr == 0)
 883                         goto no_led;
 884                 /* Find CS0 region. */
 885                 for (cs = 0; cs < 8; cs++) {
 886                         mio_boot_reg_cfg.u64 = cvmx_read_csr(CVMX_MIO_BOOT_REG_CFGX(cs));
 887                         region_base = mio_boot_reg_cfg.s.base << 16;
 888                         region_size = (mio_boot_reg_cfg.s.size + 1) << 16;
 889                         if (mio_boot_reg_cfg.s.en && base_ptr >= region_base
 890                                 && base_ptr < region_base + region_size)
 891                                 break;
 892                 }
 893
 894                 if (cs > 7)
 895                         goto no_led;
 896
 897                 new_reg[0] = cpu_to_be32(cs);
 898                 new_reg[1] = cpu_to_be32(0x20);
 899                 new_reg[2] = cpu_to_be32(0x20);
 900                 new_reg[3] = cpu_to_be32(cs);
 901                 new_reg[4] = cpu_to_be32(0);
 902                 new_reg[5] = cpu_to_be32(0x20);
 903                 fdt_setprop_inplace(initial_boot_params, led,
 904                                     "reg",  new_reg, sizeof(new_reg));
 905
 906                 bootbus = fdt_parent_offset(initial_boot_params, led);
 907                 if (bootbus < 0)
 908                         goto no_led;
 909                 ranges = fdt_getprop_w(initial_boot_params, bootbus, "ranges", &len);
 910                 if (!ranges || len < (5 * 8 * sizeof(__be32)))
 911                         goto no_led;
 912
 913                 ranges[(cs * 5) + 2] = cpu_to_be32(region_base >> 32);
 914                 ranges[(cs * 5) + 3] = cpu_to_be32(region_base & 0xffffffff);
 915                 ranges[(cs * 5) + 4] = cpu_to_be32(region_size);
 916                 goto end_led;
 917
 918 no_led:
 919                 fdt_nop_node(initial_boot_params, led);
 920 end_led:
 921                 ;
 922         }
 923
 924         /* OHCI/UHCI USB */
 925         alias_prop = fdt_getprop(initial_boot_params, aliases,
 926                                  "uctl", NULL);
 927         if (alias_prop) {
 928                 int uctl = fdt_path_offset(initial_boot_params, alias_prop);
 929
 930                 if (uctl >= 0 && (!OCTEON_IS_MODEL(OCTEON_CN6XXX) ||
 931                                   octeon_bootinfo->board_type == CVMX_BOARD_TYPE_NIC2E)) {
 932                         pr_debug("Deleting uctl\n");
 933                         fdt_nop_node(initial_boot_params, uctl);
 934                         fdt_nop_property(initial_boot_params, aliases, "uctl");
 935                 } else if (octeon_bootinfo->board_type == CVMX_BOARD_TYPE_NIC10E ||
 936                            octeon_bootinfo->board_type == CVMX_BOARD_TYPE_NIC4E) {
 937                         /* Missing "refclk-type" defaults to crystal. */
 938                         fdt_nop_property(initial_boot_params, uctl, "refclk-type");
 939                 }
 940         }
 941
 942         /* DWC2 USB */
 943         alias_prop = fdt_getprop(initial_boot_params, aliases,
 944                                  "usbn", NULL);
 945         if (alias_prop) {
 946                 int usbn = fdt_path_offset(initial_boot_params, alias_prop);
 947
 948                 if (usbn >= 0 && (current_cpu_type() == CPU_CAVIUM_OCTEON2 ||
 949                                   !octeon_has_feature(OCTEON_FEATURE_USB))) {
 950                         pr_debug("Deleting usbn\n");
 951                         fdt_nop_node(initial_boot_params, usbn);
 952                         fdt_nop_property(initial_boot_params, aliases, "usbn");
 953                 } else  {
 954                         __be32 new_f[1];
 955                         enum cvmx_helper_board_usb_clock_types c;
 956                         c = __cvmx_helper_board_usb_get_clock_type();
 957                         switch (c) {
 958                         case USB_CLOCK_TYPE_REF_48:
 959                                 new_f[0] = cpu_to_be32(48000000);
 960                                 fdt_setprop_inplace(initial_boot_params, usbn,
 961                                                     "refclk-frequency",  new_f, sizeof(new_f));
 962                                 /* Fall through ...*/
 963                         case USB_CLOCK_TYPE_REF_12:
 964                                 /* Missing "refclk-type" defaults to external. */
 965                                 fdt_nop_property(initial_boot_params, usbn, "refclk-type");
 966                                 break;
 967                         default:
 968                                 break;
 969                         }
 970                 }
 971         }
 972
 973         if (octeon_bootinfo->board_type != CVMX_BOARD_TYPE_CUST_DSR1000N) {
 974                 int dsr1000n_leds = fdt_path_offset(initial_boot_params,
 975                                                     "/dsr1000n-leds");
 976                 if (dsr1000n_leds >= 0)
 977                         fdt_nop_node(initial_boot_params, dsr1000n_leds);
 978         }
 979
 980         return 0;
 981 }
 982
 983 static int __init octeon_publish_devices(void)
 984 {
 985         return of_platform_bus_probe(NULL, octeon_ids, NULL);
 986 }
 987 device_initcall(octeon_publish_devices);
 988
 989 MODULE_AUTHOR("David Daney <ddaney@caviumnetworks.com>");
 990 MODULE_LICENSE("GPL");
 991 MODULE_DESCRIPTION("Platform driver for Octeon SOC");