Add the rt linux 4.1.3-rt3 as base
[kvmfornfv.git] / kernel / arch / m32r / platforms / mappi / setup.c
1 /*
2  *  linux/arch/m32r/platforms/mappi/setup.c
3  *
4  *  Setup routines for Renesas MAPPI Board
5  *
6  *  Copyright (c) 2001-2005  Hiroyuki Kondo, Hirokazu Takata,
7  *                           Hitoshi Yamamoto
8  */
9
10 #include <linux/irq.h>
11 #include <linux/kernel.h>
12 #include <linux/init.h>
13 #include <linux/platform_device.h>
14
15 #include <asm/m32r.h>
16 #include <asm/io.h>
17
18 #define irq2port(x) (M32R_ICU_CR1_PORTL + ((x - 1) * sizeof(unsigned long)))
19
20 icu_data_t icu_data[NR_IRQS];
21
22 static void disable_mappi_irq(unsigned int irq)
23 {
24         unsigned long port, data;
25
26         port = irq2port(irq);
27         data = icu_data[irq].icucr|M32R_ICUCR_ILEVEL7;
28         outl(data, port);
29 }
30
31 static void enable_mappi_irq(unsigned int irq)
32 {
33         unsigned long port, data;
34
35         port = irq2port(irq);
36         data = icu_data[irq].icucr|M32R_ICUCR_IEN|M32R_ICUCR_ILEVEL6;
37         outl(data, port);
38 }
39
40 static void mask_mappi(struct irq_data *data)
41 {
42         disable_mappi_irq(data->irq);
43 }
44
45 static void unmask_mappi(struct irq_data *data)
46 {
47         enable_mappi_irq(data->irq);
48 }
49
50 static void shutdown_mappi(struct irq_data *data)
51 {
52         unsigned long port;
53
54         port = irq2port(data->irq);
55         outl(M32R_ICUCR_ILEVEL7, port);
56 }
57
58 static struct irq_chip mappi_irq_type =
59 {
60         .name           = "MAPPI-IRQ",
61         .irq_shutdown   = shutdown_mappi,
62         .irq_mask       = mask_mappi,
63         .irq_unmask     = unmask_mappi,
64 };
65
66 void __init init_IRQ(void)
67 {
68         static int once = 0;
69
70         if (once)
71                 return;
72         else
73                 once++;
74
75 #ifdef CONFIG_NE2000
76         /* INT0 : LAN controller (RTL8019AS) */
77         irq_set_chip_and_handler(M32R_IRQ_INT0, &mappi_irq_type,
78                                  handle_level_irq);
79         icu_data[M32R_IRQ_INT0].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD11;
80         disable_mappi_irq(M32R_IRQ_INT0);
81 #endif /* CONFIG_M32R_NE2000 */
82
83         /* MFT2 : system timer */
84         irq_set_chip_and_handler(M32R_IRQ_MFT2, &mappi_irq_type,
85                                  handle_level_irq);
86         icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN;
87         disable_mappi_irq(M32R_IRQ_MFT2);
88
89 #ifdef CONFIG_SERIAL_M32R_SIO
90         /* SIO0_R : uart receive data */
91         irq_set_chip_and_handler(M32R_IRQ_SIO0_R, &mappi_irq_type,
92                                  handle_level_irq);
93         icu_data[M32R_IRQ_SIO0_R].icucr = 0;
94         disable_mappi_irq(M32R_IRQ_SIO0_R);
95
96         /* SIO0_S : uart send data */
97         irq_set_chip_and_handler(M32R_IRQ_SIO0_S, &mappi_irq_type,
98                                  handle_level_irq);
99         icu_data[M32R_IRQ_SIO0_S].icucr = 0;
100         disable_mappi_irq(M32R_IRQ_SIO0_S);
101
102         /* SIO1_R : uart receive data */
103         irq_set_chip_and_handler(M32R_IRQ_SIO1_R, &mappi_irq_type,
104                                  handle_level_irq);
105         icu_data[M32R_IRQ_SIO1_R].icucr = 0;
106         disable_mappi_irq(M32R_IRQ_SIO1_R);
107
108         /* SIO1_S : uart send data */
109         irq_set_chip_and_handler(M32R_IRQ_SIO1_S, &mappi_irq_type,
110                                  handle_level_irq);
111         icu_data[M32R_IRQ_SIO1_S].icucr = 0;
112         disable_mappi_irq(M32R_IRQ_SIO1_S);
113 #endif /* CONFIG_SERIAL_M32R_SIO */
114
115 #if defined(CONFIG_M32R_PCC)
116         /* INT1 : pccard0 interrupt */
117         irq_set_chip_and_handler(M32R_IRQ_INT1, &mappi_irq_type,
118                                  handle_level_irq);
119         icu_data[M32R_IRQ_INT1].icucr = M32R_ICUCR_IEN | M32R_ICUCR_ISMOD00;
120         disable_mappi_irq(M32R_IRQ_INT1);
121
122         /* INT2 : pccard1 interrupt */
123         irq_set_chip_and_handler(M32R_IRQ_INT2, &mappi_irq_type,
124                                  handle_level_irq);
125         icu_data[M32R_IRQ_INT2].icucr = M32R_ICUCR_IEN | M32R_ICUCR_ISMOD00;
126         disable_mappi_irq(M32R_IRQ_INT2);
127 #endif /* CONFIG_M32RPCC */
128 }
129
130 #if defined(CONFIG_FB_S1D13XXX)
131
132 #include <video/s1d13xxxfb.h>
133 #include <asm/s1d13806.h>
134
135 static struct s1d13xxxfb_pdata s1d13xxxfb_data = {
136         .initregs               = s1d13xxxfb_initregs,
137         .initregssize           = ARRAY_SIZE(s1d13xxxfb_initregs),
138         .platform_init_video    = NULL,
139 #ifdef CONFIG_PM
140         .platform_suspend_video = NULL,
141         .platform_resume_video  = NULL,
142 #endif
143 };
144
145 static struct resource s1d13xxxfb_resources[] = {
146         [0] = {
147                 .start  = 0x10200000UL,
148                 .end    = 0x1033FFFFUL,
149                 .flags  = IORESOURCE_MEM,
150         },
151         [1] = {
152                 .start  = 0x10000000UL,
153                 .end    = 0x100001FFUL,
154                 .flags  = IORESOURCE_MEM,
155         }
156 };
157
158 static struct platform_device s1d13xxxfb_device = {
159         .name           = S1D_DEVICENAME,
160         .id             = 0,
161         .dev            = {
162                 .platform_data  = &s1d13xxxfb_data,
163         },
164         .num_resources  = ARRAY_SIZE(s1d13xxxfb_resources),
165         .resource       = s1d13xxxfb_resources,
166 };
167
168 static int __init platform_init(void)
169 {
170         platform_device_register(&s1d13xxxfb_device);
171         return 0;
172 }
173 arch_initcall(platform_init);
174 #endif