kernel/arch/arm64/boot/dts/apm/apm-storm.dtsi

   1 /*
   2  * dts file for AppliedMicro (APM) X-Gene Storm SOC
   3  *
   4  * Copyright (C) 2013, Applied Micro Circuits Corporation
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License as
   8  * published by the Free Software Foundation; either version 2 of
   9  * the License, or (at your option) any later version.
  10  */
  11
  12 / {
  13         compatible = "apm,xgene-storm";
  14         interrupt-parent = <&gic>;
  15         #address-cells = <2>;
  16         #size-cells = <2>;
  17
  18         cpus {
  19                 #address-cells = <2>;
  20                 #size-cells = <0>;
  21
  22                 cpu@000 {
  23                         device_type = "cpu";
  24                         compatible = "apm,potenza", "arm,armv8";
  25                         reg = <0x0 0x000>;
  26                         enable-method = "spin-table";
  27                         cpu-release-addr = <0x1 0x0000fff8>;
  28                 };
  29                 cpu@001 {
  30                         device_type = "cpu";
  31                         compatible = "apm,potenza", "arm,armv8";
  32                         reg = <0x0 0x001>;
  33                         enable-method = "spin-table";
  34                         cpu-release-addr = <0x1 0x0000fff8>;
  35                 };
  36                 cpu@100 {
  37                         device_type = "cpu";
  38                         compatible = "apm,potenza", "arm,armv8";
  39                         reg = <0x0 0x100>;
  40                         enable-method = "spin-table";
  41                         cpu-release-addr = <0x1 0x0000fff8>;
  42                 };
  43                 cpu@101 {
  44                         device_type = "cpu";
  45                         compatible = "apm,potenza", "arm,armv8";
  46                         reg = <0x0 0x101>;
  47                         enable-method = "spin-table";
  48                         cpu-release-addr = <0x1 0x0000fff8>;
  49                 };
  50                 cpu@200 {
  51                         device_type = "cpu";
  52                         compatible = "apm,potenza", "arm,armv8";
  53                         reg = <0x0 0x200>;
  54                         enable-method = "spin-table";
  55                         cpu-release-addr = <0x1 0x0000fff8>;
  56                 };
  57                 cpu@201 {
  58                         device_type = "cpu";
  59                         compatible = "apm,potenza", "arm,armv8";
  60                         reg = <0x0 0x201>;
  61                         enable-method = "spin-table";
  62                         cpu-release-addr = <0x1 0x0000fff8>;
  63                 };
  64                 cpu@300 {
  65                         device_type = "cpu";
  66                         compatible = "apm,potenza", "arm,armv8";
  67                         reg = <0x0 0x300>;
  68                         enable-method = "spin-table";
  69                         cpu-release-addr = <0x1 0x0000fff8>;
  70                 };
  71                 cpu@301 {
  72                         device_type = "cpu";
  73                         compatible = "apm,potenza", "arm,armv8";
  74                         reg = <0x0 0x301>;
  75                         enable-method = "spin-table";
  76                         cpu-release-addr = <0x1 0x0000fff8>;
  77                 };
  78         };
  79
  80         gic: interrupt-controller@78010000 {
  81                 compatible = "arm,cortex-a15-gic";
  82                 #interrupt-cells = <3>;
  83                 interrupt-controller;
  84                 reg = <0x0 0x78010000 0x0 0x1000>,      /* GIC Dist */
  85                       <0x0 0x78020000 0x0 0x1000>,      /* GIC CPU */
  86                       <0x0 0x78040000 0x0 0x2000>,      /* GIC VCPU Control */
  87                       <0x0 0x78060000 0x0 0x2000>;      /* GIC VCPU */
  88                 interrupts = <1 9 0xf04>;       /* GIC Maintenence IRQ */
  89         };
  90
  91         timer {
  92                 compatible = "arm,armv8-timer";
  93                 interrupts = <1 0 0xff01>,      /* Secure Phys IRQ */
  94                              <1 13 0xff01>,     /* Non-secure Phys IRQ */
  95                              <1 14 0xff01>,     /* Virt IRQ */
  96                              <1 15 0xff01>;     /* Hyp IRQ */
  97                 clock-frequency = <50000000>;
  98         };
  99
 100         soc {
 101                 compatible = "simple-bus";
 102                 #address-cells = <2>;
 103                 #size-cells = <2>;
 104                 ranges;
 105                 dma-ranges = <0x0 0x0 0x0 0x0 0x400 0x0>;
 106
 107                 clocks {
 108                         #address-cells = <2>;
 109                         #size-cells = <2>;
 110                         ranges;
 111                         refclk: refclk {
 112                                 compatible = "fixed-clock";
 113                                 #clock-cells = <1>;
 114                                 clock-frequency = <100000000>;
 115                                 clock-output-names = "refclk";
 116                         };
 117
 118                         pcppll: pcppll@17000100 {
 119                                 compatible = "apm,xgene-pcppll-clock";
 120                                 #clock-cells = <1>;
 121                                 clocks = <&refclk 0>;
 122                                 clock-names = "pcppll";
 123                                 reg = <0x0 0x17000100 0x0 0x1000>;
 124                                 clock-output-names = "pcppll";
 125                                 type = <0>;
 126                         };
 127
 128                         socpll: socpll@17000120 {
 129                                 compatible = "apm,xgene-socpll-clock";
 130                                 #clock-cells = <1>;
 131                                 clocks = <&refclk 0>;
 132                                 clock-names = "socpll";
 133                                 reg = <0x0 0x17000120 0x0 0x1000>;
 134                                 clock-output-names = "socpll";
 135                                 type = <1>;
 136                         };
 137
 138                         socplldiv2: socplldiv2  {
 139                                 compatible = "fixed-factor-clock";
 140                                 #clock-cells = <1>;
 141                                 clocks = <&socpll 0>;
 142                                 clock-names = "socplldiv2";
 143                                 clock-mult = <1>;
 144                                 clock-div = <2>;
 145                                 clock-output-names = "socplldiv2";
 146                         };
 147
 148                         qmlclk: qmlclk {
 149                                 compatible = "apm,xgene-device-clock";
 150                                 #clock-cells = <1>;
 151                                 clocks = <&socplldiv2 0>;
 152                                 clock-names = "qmlclk";
 153                                 reg = <0x0 0x1703C000 0x0 0x1000>;
 154                                 reg-names = "csr-reg";
 155                                 clock-output-names = "qmlclk";
 156                         };
 157
 158                         ethclk: ethclk {
 159                                 compatible = "apm,xgene-device-clock";
 160                                 #clock-cells = <1>;
 161                                 clocks = <&socplldiv2 0>;
 162                                 clock-names = "ethclk";
 163                                 reg = <0x0 0x17000000 0x0 0x1000>;
 164                                 reg-names = "div-reg";
 165                                 divider-offset = <0x238>;
 166                                 divider-width = <0x9>;
 167                                 divider-shift = <0x0>;
 168                                 clock-output-names = "ethclk";
 169                         };
 170
 171                         menetclk: menetclk {
 172                                 compatible = "apm,xgene-device-clock";
 173                                 #clock-cells = <1>;
 174                                 clocks = <&ethclk 0>;
 175                                 reg = <0x0 0x1702C000 0x0 0x1000>;
 176                                 reg-names = "csr-reg";
 177                                 clock-output-names = "menetclk";
 178                         };
 179
 180                         sge0clk: sge0clk@1f21c000 {
 181                                 compatible = "apm,xgene-device-clock";
 182                                 #clock-cells = <1>;
 183                                 clocks = <&socplldiv2 0>;
 184                                 reg = <0x0 0x1f21c000 0x0 0x1000>;
 185                                 reg-names = "csr-reg";
 186                                 csr-mask = <0x3>;
 187                                 clock-output-names = "sge0clk";
 188                         };
 189
 190                         sge1clk: sge1clk@1f21c000 {
 191                                 compatible = "apm,xgene-device-clock";
 192                                 #clock-cells = <1>;
 193                                 clocks = <&socplldiv2 0>;
 194                                 reg = <0x0 0x1f21c000 0x0 0x1000>;
 195                                 reg-names = "csr-reg";
 196                                 csr-mask = <0xc>;
 197                                 clock-output-names = "sge1clk";
 198                         };
 199
 200                         xge0clk: xge0clk@1f61c000 {
 201                                 compatible = "apm,xgene-device-clock";
 202                                 #clock-cells = <1>;
 203                                 clocks = <&socplldiv2 0>;
 204                                 reg = <0x0 0x1f61c000 0x0 0x1000>;
 205                                 reg-names = "csr-reg";
 206                                 csr-mask = <0x3>;
 207                                 clock-output-names = "xge0clk";
 208                         };
 209
 210                         sataphy1clk: sataphy1clk@1f21c000 {
 211                                 compatible = "apm,xgene-device-clock";
 212                                 #clock-cells = <1>;
 213                                 clocks = <&socplldiv2 0>;
 214                                 reg = <0x0 0x1f21c000 0x0 0x1000>;
 215                                 reg-names = "csr-reg";
 216                                 clock-output-names = "sataphy1clk";
 217                                 status = "disabled";
 218                                 csr-offset = <0x4>;
 219                                 csr-mask = <0x00>;
 220                                 enable-offset = <0x0>;
 221                                 enable-mask = <0x06>;
 222                         };
 223
 224                         sataphy2clk: sataphy1clk@1f22c000 {
 225                                 compatible = "apm,xgene-device-clock";
 226                                 #clock-cells = <1>;
 227                                 clocks = <&socplldiv2 0>;
 228                                 reg = <0x0 0x1f22c000 0x0 0x1000>;
 229                                 reg-names = "csr-reg";
 230                                 clock-output-names = "sataphy2clk";
 231                                 status = "ok";
 232                                 csr-offset = <0x4>;
 233                                 csr-mask = <0x3a>;
 234                                 enable-offset = <0x0>;
 235                                 enable-mask = <0x06>;
 236                         };
 237
 238                         sataphy3clk: sataphy1clk@1f23c000 {
 239                                 compatible = "apm,xgene-device-clock";
 240                                 #clock-cells = <1>;
 241                                 clocks = <&socplldiv2 0>;
 242                                 reg = <0x0 0x1f23c000 0x0 0x1000>;
 243                                 reg-names = "csr-reg";
 244                                 clock-output-names = "sataphy3clk";
 245                                 status = "ok";
 246                                 csr-offset = <0x4>;
 247                                 csr-mask = <0x3a>;
 248                                 enable-offset = <0x0>;
 249                                 enable-mask = <0x06>;
 250                         };
 251
 252                         sata01clk: sata01clk@1f21c000 {
 253                                 compatible = "apm,xgene-device-clock";
 254                                 #clock-cells = <1>;
 255                                 clocks = <&socplldiv2 0>;
 256                                 reg = <0x0 0x1f21c000 0x0 0x1000>;
 257                                 reg-names = "csr-reg";
 258                                 clock-output-names = "sata01clk";
 259                                 csr-offset = <0x4>;
 260                                 csr-mask = <0x05>;
 261                                 enable-offset = <0x0>;
 262                                 enable-mask = <0x39>;
 263                         };
 264
 265                         sata23clk: sata23clk@1f22c000 {
 266                                 compatible = "apm,xgene-device-clock";
 267                                 #clock-cells = <1>;
 268                                 clocks = <&socplldiv2 0>;
 269                                 reg = <0x0 0x1f22c000 0x0 0x1000>;
 270                                 reg-names = "csr-reg";
 271                                 clock-output-names = "sata23clk";
 272                                 csr-offset = <0x4>;
 273                                 csr-mask = <0x05>;
 274                                 enable-offset = <0x0>;
 275                                 enable-mask = <0x39>;
 276                         };
 277
 278                         sata45clk: sata45clk@1f23c000 {
 279                                 compatible = "apm,xgene-device-clock";
 280                                 #clock-cells = <1>;
 281                                 clocks = <&socplldiv2 0>;
 282                                 reg = <0x0 0x1f23c000 0x0 0x1000>;
 283                                 reg-names = "csr-reg";
 284                                 clock-output-names = "sata45clk";
 285                                 csr-offset = <0x4>;
 286                                 csr-mask = <0x05>;
 287                                 enable-offset = <0x0>;
 288                                 enable-mask = <0x39>;
 289                         };
 290
 291                         rtcclk: rtcclk@17000000 {
 292                                 compatible = "apm,xgene-device-clock";
 293                                 #clock-cells = <1>;
 294                                 clocks = <&socplldiv2 0>;
 295                                 reg = <0x0 0x17000000 0x0 0x2000>;
 296                                 reg-names = "csr-reg";
 297                                 csr-offset = <0xc>;
 298                                 csr-mask = <0x2>;
 299                                 enable-offset = <0x10>;
 300                                 enable-mask = <0x2>;
 301                                 clock-output-names = "rtcclk";
 302                         };
 303
 304                         rngpkaclk: rngpkaclk@17000000 {
 305                                 compatible = "apm,xgene-device-clock";
 306                                 #clock-cells = <1>;
 307                                 clocks = <&socplldiv2 0>;
 308                                 reg = <0x0 0x17000000 0x0 0x2000>;
 309                                 reg-names = "csr-reg";
 310                                 csr-offset = <0xc>;
 311                                 csr-mask = <0x10>;
 312                                 enable-offset = <0x10>;
 313                                 enable-mask = <0x10>;
 314                                 clock-output-names = "rngpkaclk";
 315                         };
 316
 317                         pcie0clk: pcie0clk@1f2bc000 {
 318                                 status = "disabled";
 319                                 compatible = "apm,xgene-device-clock";
 320                                 #clock-cells = <1>;
 321                                 clocks = <&socplldiv2 0>;
 322                                 reg = <0x0 0x1f2bc000 0x0 0x1000>;
 323                                 reg-names = "csr-reg";
 324                                 clock-output-names = "pcie0clk";
 325                         };
 326
 327                         pcie1clk: pcie1clk@1f2cc000 {
 328                                 status = "disabled";
 329                                 compatible = "apm,xgene-device-clock";
 330                                 #clock-cells = <1>;
 331                                 clocks = <&socplldiv2 0>;
 332                                 reg = <0x0 0x1f2cc000 0x0 0x1000>;
 333                                 reg-names = "csr-reg";
 334                                 clock-output-names = "pcie1clk";
 335                         };
 336
 337                         pcie2clk: pcie2clk@1f2dc000 {
 338                                 status = "disabled";
 339                                 compatible = "apm,xgene-device-clock";
 340                                 #clock-cells = <1>;
 341                                 clocks = <&socplldiv2 0>;
 342                                 reg = <0x0 0x1f2dc000 0x0 0x1000>;
 343                                 reg-names = "csr-reg";
 344                                 clock-output-names = "pcie2clk";
 345                         };
 346
 347                         pcie3clk: pcie3clk@1f50c000 {
 348                                 status = "disabled";
 349                                 compatible = "apm,xgene-device-clock";
 350                                 #clock-cells = <1>;
 351                                 clocks = <&socplldiv2 0>;
 352                                 reg = <0x0 0x1f50c000 0x0 0x1000>;
 353                                 reg-names = "csr-reg";
 354                                 clock-output-names = "pcie3clk";
 355                         };
 356
 357                         pcie4clk: pcie4clk@1f51c000 {
 358                                 status = "disabled";
 359                                 compatible = "apm,xgene-device-clock";
 360                                 #clock-cells = <1>;
 361                                 clocks = <&socplldiv2 0>;
 362                                 reg = <0x0 0x1f51c000 0x0 0x1000>;
 363                                 reg-names = "csr-reg";
 364                                 clock-output-names = "pcie4clk";
 365                         };
 366
 367                         dmaclk: dmaclk@1f27c000 {
 368                                 compatible = "apm,xgene-device-clock";
 369                                 #clock-cells = <1>;
 370                                 clocks = <&socplldiv2 0>;
 371                                 reg = <0x0 0x1f27c000 0x0 0x1000>;
 372                                 reg-names = "csr-reg";
 373                                 clock-output-names = "dmaclk";
 374                         };
 375                 };
 376
 377                 pcie0: pcie@1f2b0000 {
 378                         status = "disabled";
 379                         device_type = "pci";
 380                         compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie";
 381                         #interrupt-cells = <1>;
 382                         #size-cells = <2>;
 383                         #address-cells = <3>;
 384                         reg = < 0x00 0x1f2b0000 0x0 0x00010000   /* Controller registers */
 385                                 0xe0 0xd0000000 0x0 0x00040000>; /* PCI config space */
 386                         reg-names = "csr", "cfg";
 387                         ranges = <0x01000000 0x00 0x00000000 0xe0 0x10000000 0x00 0x00010000   /* io */
 388                                   0x02000000 0x00 0x80000000 0xe1 0x80000000 0x00 0x80000000>; /* mem */
 389                         dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
 390                                       0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
 391                         interrupt-map-mask = <0x0 0x0 0x0 0x7>;
 392                         interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xc2 0x1
 393                                          0x0 0x0 0x0 0x2 &gic 0x0 0xc3 0x1
 394                                          0x0 0x0 0x0 0x3 &gic 0x0 0xc4 0x1
 395                                          0x0 0x0 0x0 0x4 &gic 0x0 0xc5 0x1>;
 396                         dma-coherent;
 397                         clocks = <&pcie0clk 0>;
 398                 };
 399
 400                 pcie1: pcie@1f2c0000 {
 401                         status = "disabled";
 402                         device_type = "pci";
 403                         compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie";
 404                         #interrupt-cells = <1>;
 405                         #size-cells = <2>;
 406                         #address-cells = <3>;
 407                         reg = < 0x00 0x1f2c0000 0x0 0x00010000   /* Controller registers */
 408                                 0xd0 0xd0000000 0x0 0x00040000>; /* PCI config space */
 409                         reg-names = "csr", "cfg";
 410                         ranges = <0x01000000 0x0 0x00000000 0xd0 0x10000000 0x00 0x00010000   /* io  */
 411                                   0x02000000 0x0 0x80000000 0xd1 0x80000000 0x00 0x80000000>; /* mem */
 412                         dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
 413                                       0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
 414                         interrupt-map-mask = <0x0 0x0 0x0 0x7>;
 415                         interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xc8 0x1
 416                                          0x0 0x0 0x0 0x2 &gic 0x0 0xc9 0x1
 417                                          0x0 0x0 0x0 0x3 &gic 0x0 0xca 0x1
 418                                          0x0 0x0 0x0 0x4 &gic 0x0 0xcb 0x1>;
 419                         dma-coherent;
 420                         clocks = <&pcie1clk 0>;
 421                 };
 422
 423                 pcie2: pcie@1f2d0000 {
 424                         status = "disabled";
 425                         device_type = "pci";
 426                         compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie";
 427                         #interrupt-cells = <1>;
 428                         #size-cells = <2>;
 429                         #address-cells = <3>;
 430                         reg =  < 0x00 0x1f2d0000 0x0 0x00010000   /* Controller registers */
 431                                  0x90 0xd0000000 0x0 0x00040000>; /* PCI config space */
 432                         reg-names = "csr", "cfg";
 433                         ranges = <0x01000000 0x0 0x00000000 0x90 0x10000000 0x0 0x00010000   /* io  */
 434                                   0x02000000 0x0 0x80000000 0x91 0x80000000 0x0 0x80000000>; /* mem */
 435                         dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
 436                                       0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
 437                         interrupt-map-mask = <0x0 0x0 0x0 0x7>;
 438                         interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xce 0x1
 439                                          0x0 0x0 0x0 0x2 &gic 0x0 0xcf 0x1
 440                                          0x0 0x0 0x0 0x3 &gic 0x0 0xd0 0x1
 441                                          0x0 0x0 0x0 0x4 &gic 0x0 0xd1 0x1>;
 442                         dma-coherent;
 443                         clocks = <&pcie2clk 0>;
 444                 };
 445
 446                 pcie3: pcie@1f500000 {
 447                         status = "disabled";
 448                         device_type = "pci";
 449                         compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie";
 450                         #interrupt-cells = <1>;
 451                         #size-cells = <2>;
 452                         #address-cells = <3>;
 453                         reg = < 0x00 0x1f500000 0x0 0x00010000   /* Controller registers */
 454                                 0xa0 0xd0000000 0x0 0x00040000>; /* PCI config space */
 455                         reg-names = "csr", "cfg";
 456                         ranges = <0x01000000 0x0 0x00000000 0xa0 0x10000000 0x0 0x00010000   /* io   */
 457                                   0x02000000 0x0 0x80000000 0xa1 0x80000000 0x0 0x80000000>; /* mem  */
 458                         dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
 459                                       0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
 460                         interrupt-map-mask = <0x0 0x0 0x0 0x7>;
 461                         interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xd4 0x1
 462                                          0x0 0x0 0x0 0x2 &gic 0x0 0xd5 0x1
 463                                          0x0 0x0 0x0 0x3 &gic 0x0 0xd6 0x1
 464                                          0x0 0x0 0x0 0x4 &gic 0x0 0xd7 0x1>;
 465                         dma-coherent;
 466                         clocks = <&pcie3clk 0>;
 467                 };
 468
 469                 pcie4: pcie@1f510000 {
 470                         status = "disabled";
 471                         device_type = "pci";
 472                         compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie";
 473                         #interrupt-cells = <1>;
 474                         #size-cells = <2>;
 475                         #address-cells = <3>;
 476                         reg = < 0x00 0x1f510000 0x0 0x00010000   /* Controller registers */
 477                                 0xc0 0xd0000000 0x0 0x00200000>; /* PCI config space */
 478                         reg-names = "csr", "cfg";
 479                         ranges = <0x01000000 0x0 0x00000000 0xc0 0x10000000 0x0 0x00010000   /* io  */
 480                                   0x02000000 0x0 0x80000000 0xc1 0x80000000 0x0 0x80000000>; /* mem */
 481                         dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
 482                                       0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
 483                         interrupt-map-mask = <0x0 0x0 0x0 0x7>;
 484                         interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xda 0x1
 485                                          0x0 0x0 0x0 0x2 &gic 0x0 0xdb 0x1
 486                                          0x0 0x0 0x0 0x3 &gic 0x0 0xdc 0x1
 487                                          0x0 0x0 0x0 0x4 &gic 0x0 0xdd 0x1>;
 488                         dma-coherent;
 489                         clocks = <&pcie4clk 0>;
 490                 };
 491
 492                 serial0: serial@1c020000 {
 493                         status = "disabled";
 494                         device_type = "serial";
 495                         compatible = "ns16550a";
 496                         reg = <0 0x1c020000 0x0 0x1000>;
 497                         reg-shift = <2>;
 498                         clock-frequency = <10000000>; /* Updated by bootloader */
 499                         interrupt-parent = <&gic>;
 500                         interrupts = <0x0 0x4c 0x4>;
 501                 };
 502
 503                 serial1: serial@1c021000 {
 504                         status = "disabled";
 505                         device_type = "serial";
 506                         compatible = "ns16550a";
 507                         reg = <0 0x1c021000 0x0 0x1000>;
 508                         reg-shift = <2>;
 509                         clock-frequency = <10000000>; /* Updated by bootloader */
 510                         interrupt-parent = <&gic>;
 511                         interrupts = <0x0 0x4d 0x4>;
 512                 };
 513
 514                 serial2: serial@1c022000 {
 515                         status = "disabled";
 516                         device_type = "serial";
 517                         compatible = "ns16550a";
 518                         reg = <0 0x1c022000 0x0 0x1000>;
 519                         reg-shift = <2>;
 520                         clock-frequency = <10000000>; /* Updated by bootloader */
 521                         interrupt-parent = <&gic>;
 522                         interrupts = <0x0 0x4e 0x4>;
 523                 };
 524
 525                 serial3: serial@1c023000 {
 526                         status = "disabled";
 527                         device_type = "serial";
 528                         compatible = "ns16550a";
 529                         reg = <0 0x1c023000 0x0 0x1000>;
 530                         reg-shift = <2>;
 531                         clock-frequency = <10000000>; /* Updated by bootloader */
 532                         interrupt-parent = <&gic>;
 533                         interrupts = <0x0 0x4f 0x4>;
 534                 };
 535
 536                 phy1: phy@1f21a000 {
 537                         compatible = "apm,xgene-phy";
 538                         reg = <0x0 0x1f21a000 0x0 0x100>;
 539                         #phy-cells = <1>;
 540                         clocks = <&sataphy1clk 0>;
 541                         status = "disabled";
 542                         apm,tx-boost-gain = <30 30 30 30 30 30>;
 543                         apm,tx-eye-tuning = <2 10 10 2 10 10>;
 544                 };
 545
 546                 phy2: phy@1f22a000 {
 547                         compatible = "apm,xgene-phy";
 548                         reg = <0x0 0x1f22a000 0x0 0x100>;
 549                         #phy-cells = <1>;
 550                         clocks = <&sataphy2clk 0>;
 551                         status = "ok";
 552                         apm,tx-boost-gain = <30 30 30 30 30 30>;
 553                         apm,tx-eye-tuning = <1 10 10 2 10 10>;
 554                 };
 555
 556                 phy3: phy@1f23a000 {
 557                         compatible = "apm,xgene-phy";
 558                         reg = <0x0 0x1f23a000 0x0 0x100>;
 559                         #phy-cells = <1>;
 560                         clocks = <&sataphy3clk 0>;
 561                         status = "ok";
 562                         apm,tx-boost-gain = <31 31 31 31 31 31>;
 563                         apm,tx-eye-tuning = <2 10 10 2 10 10>;
 564                 };
 565
 566                 sata1: sata@1a000000 {
 567                         compatible = "apm,xgene-ahci";
 568                         reg = <0x0 0x1a000000 0x0 0x1000>,
 569                               <0x0 0x1f210000 0x0 0x1000>,
 570                               <0x0 0x1f21d000 0x0 0x1000>,
 571                               <0x0 0x1f21e000 0x0 0x1000>,
 572                               <0x0 0x1f217000 0x0 0x1000>;
 573                         interrupts = <0x0 0x86 0x4>;
 574                         dma-coherent;
 575                         status = "disabled";
 576                         clocks = <&sata01clk 0>;
 577                         phys = <&phy1 0>;
 578                         phy-names = "sata-phy";
 579                 };
 580
 581                 sata2: sata@1a400000 {
 582                         compatible = "apm,xgene-ahci";
 583                         reg = <0x0 0x1a400000 0x0 0x1000>,
 584                               <0x0 0x1f220000 0x0 0x1000>,
 585                               <0x0 0x1f22d000 0x0 0x1000>,
 586                               <0x0 0x1f22e000 0x0 0x1000>,
 587                               <0x0 0x1f227000 0x0 0x1000>;
 588                         interrupts = <0x0 0x87 0x4>;
 589                         dma-coherent;
 590                         status = "ok";
 591                         clocks = <&sata23clk 0>;
 592                         phys = <&phy2 0>;
 593                         phy-names = "sata-phy";
 594                 };
 595
 596                 sata3: sata@1a800000 {
 597                         compatible = "apm,xgene-ahci";
 598                         reg = <0x0 0x1a800000 0x0 0x1000>,
 599                               <0x0 0x1f230000 0x0 0x1000>,
 600                               <0x0 0x1f23d000 0x0 0x1000>,
 601                               <0x0 0x1f23e000 0x0 0x1000>;
 602                         interrupts = <0x0 0x88 0x4>;
 603                         dma-coherent;
 604                         status = "ok";
 605                         clocks = <&sata45clk 0>;
 606                         phys = <&phy3 0>;
 607                         phy-names = "sata-phy";
 608                 };
 609
 610                 rtc: rtc@10510000 {
 611                         compatible = "apm,xgene-rtc";
 612                         reg = <0x0 0x10510000 0x0 0x400>;
 613                         interrupts = <0x0 0x46 0x4>;
 614                         #clock-cells = <1>;
 615                         clocks = <&rtcclk 0>;
 616                 };
 617
 618                 menet: ethernet@17020000 {
 619                         compatible = "apm,xgene-enet";
 620                         status = "disabled";
 621                         reg = <0x0 0x17020000 0x0 0xd100>,
 622                               <0x0 0X17030000 0x0 0Xc300>,
 623                               <0x0 0X10000000 0x0 0X200>;
 624                         reg-names = "enet_csr", "ring_csr", "ring_cmd";
 625                         interrupts = <0x0 0x3c 0x4>;
 626                         dma-coherent;
 627                         clocks = <&menetclk 0>;
 628                         /* mac address will be overwritten by the bootloader */
 629                         local-mac-address = [00 00 00 00 00 00];
 630                         phy-connection-type = "rgmii";
 631                         phy-handle = <&menetphy>;
 632                         mdio {
 633                                 compatible = "apm,xgene-mdio";
 634                                 #address-cells = <1>;
 635                                 #size-cells = <0>;
 636                                 menetphy: menetphy@3 {
 637                                         compatible = "ethernet-phy-id001c.c915";
 638                                         reg = <0x3>;
 639                                 };
 640
 641                         };
 642                 };
 643
 644                 sgenet0: ethernet@1f210000 {
 645                         compatible = "apm,xgene1-sgenet";
 646                         status = "disabled";
 647                         reg = <0x0 0x1f210000 0x0 0xd100>,
 648                               <0x0 0x1f200000 0x0 0Xc300>,
 649                               <0x0 0x1B000000 0x0 0X200>;
 650                         reg-names = "enet_csr", "ring_csr", "ring_cmd";
 651                         interrupts = <0x0 0xA0 0x4>,
 652                                      <0x0 0xA1 0x4>;
 653                         dma-coherent;
 654                         clocks = <&sge0clk 0>;
 655                         local-mac-address = [00 00 00 00 00 00];
 656                         phy-connection-type = "sgmii";
 657                 };
 658
 659                 sgenet1: ethernet@1f210030 {
 660                         compatible = "apm,xgene1-sgenet";
 661                         status = "disabled";
 662                         reg = <0x0 0x1f210030 0x0 0xd100>,
 663                               <0x0 0x1f200000 0x0 0Xc300>,
 664                               <0x0 0x1B000000 0x0 0X8000>;
 665                         reg-names = "enet_csr", "ring_csr", "ring_cmd";
 666                         interrupts = <0x0 0xAC 0x4>,
 667                                      <0x0 0xAD 0x4>;
 668                         port-id = <1>;
 669                         dma-coherent;
 670                         clocks = <&sge1clk 0>;
 671                         local-mac-address = [00 00 00 00 00 00];
 672                         phy-connection-type = "sgmii";
 673                 };
 674
 675                 xgenet: ethernet@1f610000 {
 676                         compatible = "apm,xgene1-xgenet";
 677                         status = "disabled";
 678                         reg = <0x0 0x1f610000 0x0 0xd100>,
 679                               <0x0 0x1f600000 0x0 0Xc300>,
 680                               <0x0 0x18000000 0x0 0X200>;
 681                         reg-names = "enet_csr", "ring_csr", "ring_cmd";
 682                         interrupts = <0x0 0x60 0x4>,
 683                                      <0x0 0x61 0x4>;
 684                         dma-coherent;
 685                         clocks = <&xge0clk 0>;
 686                         /* mac address will be overwritten by the bootloader */
 687                         local-mac-address = [00 00 00 00 00 00];
 688                         phy-connection-type = "xgmii";
 689                 };
 690
 691                 rng: rng@10520000 {
 692                         compatible = "apm,xgene-rng";
 693                         reg = <0x0 0x10520000 0x0 0x100>;
 694                         interrupts = <0x0 0x41 0x4>;
 695                         clocks = <&rngpkaclk 0>;
 696                 };
 697
 698                 dma: dma@1f270000 {
 699                         compatible = "apm,xgene-storm-dma";
 700                         device_type = "dma";
 701                         reg = <0x0 0x1f270000 0x0 0x10000>,
 702                               <0x0 0x1f200000 0x0 0x10000>,
 703                               <0x0 0x1b008000 0x0 0x2000>,
 704                               <0x0 0x1054a000 0x0 0x100>;
 705                         interrupts = <0x0 0x82 0x4>,
 706                                      <0x0 0xb8 0x4>,
 707                                      <0x0 0xb9 0x4>,
 708                                      <0x0 0xba 0x4>,
 709                                      <0x0 0xbb 0x4>;
 710                         dma-coherent;
 711                         clocks = <&dmaclk 0>;
 712                 };
 713         };
 714 };