kernel/arch/arm/plat-omap/dma.c

   1 /*
   2  * linux/arch/arm/plat-omap/dma.c
   3  *
   4  * Copyright (C) 2003 - 2008 Nokia Corporation
   5  * Author: Juha Yrjölä <juha.yrjola@nokia.com>
   6  * DMA channel linking for 1610 by Samuel Ortiz <samuel.ortiz@nokia.com>
   7  * Graphics DMA and LCD DMA graphics tranformations
   8  * by Imre Deak <imre.deak@nokia.com>
   9  * OMAP2/3 support Copyright (C) 2004-2007 Texas Instruments, Inc.
  10  * Merged to support both OMAP1 and OMAP2 by Tony Lindgren <tony@atomide.com>
  11  * Some functions based on earlier dma-omap.c Copyright (C) 2001 RidgeRun, Inc.
  12  *
  13  * Copyright (C) 2009 Texas Instruments
  14  * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
  15  *
  16  * Support functions for the OMAP internal DMA channels.
  17  *
  18  * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
  19  * Converted DMA library into DMA platform driver.
  20  *      - G, Manjunath Kondaiah <manjugk@ti.com>
  21  *
  22  * This program is free software; you can redistribute it and/or modify
  23  * it under the terms of the GNU General Public License version 2 as
  24  * published by the Free Software Foundation.
  25  *
  26  */
  27
  28 #include <linux/module.h>
  29 #include <linux/init.h>
  30 #include <linux/sched.h>
  31 #include <linux/spinlock.h>
  32 #include <linux/errno.h>
  33 #include <linux/interrupt.h>
  34 #include <linux/irq.h>
  35 #include <linux/io.h>
  36 #include <linux/slab.h>
  37 #include <linux/delay.h>
  38
  39 #include <linux/omap-dma.h>
  40
  41 /*
  42  * MAX_LOGICAL_DMA_CH_COUNT: the maximum number of logical DMA
  43  * channels that an instance of the SDMA IP block can support.  Used
  44  * to size arrays.  (The actual maximum on a particular SoC may be less
  45  * than this -- for example, OMAP1 SDMA instances only support 17 logical
  46  * DMA channels.)
  47  */
  48 #define MAX_LOGICAL_DMA_CH_COUNT                32
  49
  50 #undef DEBUG
  51
  52 #ifndef CONFIG_ARCH_OMAP1
  53 enum { DMA_CH_ALLOC_DONE, DMA_CH_PARAMS_SET_DONE, DMA_CH_STARTED,
  54         DMA_CH_QUEUED, DMA_CH_NOTSTARTED, DMA_CH_PAUSED, DMA_CH_LINK_ENABLED
  55 };
  56
  57 enum { DMA_CHAIN_STARTED, DMA_CHAIN_NOTSTARTED };
  58 #endif
  59
  60 #define OMAP_DMA_ACTIVE                 0x01
  61 #define OMAP2_DMA_CSR_CLEAR_MASK        0xffffffff
  62
  63 #define OMAP_FUNC_MUX_ARM_BASE          (0xfffe1000 + 0xec)
  64
  65 static struct omap_system_dma_plat_info *p;
  66 static struct omap_dma_dev_attr *d;
  67 static void omap_clear_dma(int lch);
  68 static int omap_dma_set_prio_lch(int lch, unsigned char read_prio,
  69                                  unsigned char write_prio);
  70 static int enable_1510_mode;
  71 static u32 errata;
  72
  73 static struct omap_dma_global_context_registers {
  74         u32 dma_irqenable_l0;
  75         u32 dma_irqenable_l1;
  76         u32 dma_ocp_sysconfig;
  77         u32 dma_gcr;
  78 } omap_dma_global_context;
  79
  80 struct dma_link_info {
  81         int *linked_dmach_q;
  82         int no_of_lchs_linked;
  83
  84         int q_count;
  85         int q_tail;
  86         int q_head;
  87
  88         int chain_state;
  89         int chain_mode;
  90
  91 };
  92
  93 static struct dma_link_info *dma_linked_lch;
  94
  95 #ifndef CONFIG_ARCH_OMAP1
  96
  97 /* Chain handling macros */
  98 #define OMAP_DMA_CHAIN_QINIT(chain_id)                                  \
  99         do {                                                            \
 100                 dma_linked_lch[chain_id].q_head =                       \
 101                 dma_linked_lch[chain_id].q_tail =                       \
 102                 dma_linked_lch[chain_id].q_count = 0;                   \
 103         } while (0)
 104 #define OMAP_DMA_CHAIN_QFULL(chain_id)                                  \
 105                 (dma_linked_lch[chain_id].no_of_lchs_linked ==          \
 106                 dma_linked_lch[chain_id].q_count)
 107 #define OMAP_DMA_CHAIN_QLAST(chain_id)                                  \
 108         do {                                                            \
 109                 ((dma_linked_lch[chain_id].no_of_lchs_linked-1) ==      \
 110                 dma_linked_lch[chain_id].q_count)                       \
 111         } while (0)
 112 #define OMAP_DMA_CHAIN_QEMPTY(chain_id)                                 \
 113                 (0 == dma_linked_lch[chain_id].q_count)
 114 #define __OMAP_DMA_CHAIN_INCQ(end)                                      \
 115         ((end) = ((end)+1) % dma_linked_lch[chain_id].no_of_lchs_linked)
 116 #define OMAP_DMA_CHAIN_INCQHEAD(chain_id)                               \
 117         do {                                                            \
 118                 __OMAP_DMA_CHAIN_INCQ(dma_linked_lch[chain_id].q_head); \
 119                 dma_linked_lch[chain_id].q_count--;                     \
 120         } while (0)
 121
 122 #define OMAP_DMA_CHAIN_INCQTAIL(chain_id)                               \
 123         do {                                                            \
 124                 __OMAP_DMA_CHAIN_INCQ(dma_linked_lch[chain_id].q_tail); \
 125                 dma_linked_lch[chain_id].q_count++; \
 126         } while (0)
 127 #endif
 128
 129 static int dma_lch_count;
 130 static int dma_chan_count;
 131 static int omap_dma_reserve_channels;
 132
 133 static spinlock_t dma_chan_lock;
 134 static struct omap_dma_lch *dma_chan;
 135
 136 static inline void disable_lnk(int lch);
 137 static void omap_disable_channel_irq(int lch);
 138 static inline void omap_enable_channel_irq(int lch);
 139
 140 #define REVISIT_24XX()          printk(KERN_ERR "FIXME: no %s on 24xx\n", \
 141                                                 __func__);
 142
 143 #ifdef CONFIG_ARCH_OMAP15XX
 144 /* Returns 1 if the DMA module is in OMAP1510-compatible mode, 0 otherwise */
 145 static int omap_dma_in_1510_mode(void)
 146 {
 147         return enable_1510_mode;
 148 }
 149 #else
 150 #define omap_dma_in_1510_mode()         0
 151 #endif
 152
 153 #ifdef CONFIG_ARCH_OMAP1
 154 static inline void set_gdma_dev(int req, int dev)
 155 {
 156         u32 reg = OMAP_FUNC_MUX_ARM_BASE + ((req - 1) / 5) * 4;
 157         int shift = ((req - 1) % 5) * 6;
 158         u32 l;
 159
 160         l = omap_readl(reg);
 161         l &= ~(0x3f << shift);
 162         l |= (dev - 1) << shift;
 163         omap_writel(l, reg);
 164 }
 165 #else
 166 #define set_gdma_dev(req, dev)  do {} while (0)
 167 #define omap_readl(reg)         0
 168 #define omap_writel(val, reg)   do {} while (0)
 169 #endif
 170
 171 #ifdef CONFIG_ARCH_OMAP1
 172 void omap_set_dma_priority(int lch, int dst_port, int priority)
 173 {
 174         unsigned long reg;
 175         u32 l;
 176
 177         if (dma_omap1()) {
 178                 switch (dst_port) {
 179                 case OMAP_DMA_PORT_OCP_T1:      /* FFFECC00 */
 180                         reg = OMAP_TC_OCPT1_PRIOR;
 181                         break;
 182                 case OMAP_DMA_PORT_OCP_T2:      /* FFFECCD0 */
 183                         reg = OMAP_TC_OCPT2_PRIOR;
 184                         break;
 185                 case OMAP_DMA_PORT_EMIFF:       /* FFFECC08 */
 186                         reg = OMAP_TC_EMIFF_PRIOR;
 187                         break;
 188                 case OMAP_DMA_PORT_EMIFS:       /* FFFECC04 */
 189                         reg = OMAP_TC_EMIFS_PRIOR;
 190                         break;
 191                 default:
 192                         BUG();
 193                         return;
 194                 }
 195                 l = omap_readl(reg);
 196                 l &= ~(0xf << 8);
 197                 l |= (priority & 0xf) << 8;
 198                 omap_writel(l, reg);
 199         }
 200 }
 201 #endif
 202
 203 #ifdef CONFIG_ARCH_OMAP2PLUS
 204 void omap_set_dma_priority(int lch, int dst_port, int priority)
 205 {
 206         u32 ccr;
 207
 208         ccr = p->dma_read(CCR, lch);
 209         if (priority)
 210                 ccr |= (1 << 6);
 211         else
 212                 ccr &= ~(1 << 6);
 213         p->dma_write(ccr, CCR, lch);
 214 }
 215 #endif
 216 EXPORT_SYMBOL(omap_set_dma_priority);
 217
 218 void omap_set_dma_transfer_params(int lch, int data_type, int elem_count,
 219                                   int frame_count, int sync_mode,
 220                                   int dma_trigger, int src_or_dst_synch)
 221 {
 222         u32 l;
 223
 224         l = p->dma_read(CSDP, lch);
 225         l &= ~0x03;
 226         l |= data_type;
 227         p->dma_write(l, CSDP, lch);
 228
 229         if (dma_omap1()) {
 230                 u16 ccr;
 231
 232                 ccr = p->dma_read(CCR, lch);
 233                 ccr &= ~(1 << 5);
 234                 if (sync_mode == OMAP_DMA_SYNC_FRAME)
 235                         ccr |= 1 << 5;
 236                 p->dma_write(ccr, CCR, lch);
 237
 238                 ccr = p->dma_read(CCR2, lch);
 239                 ccr &= ~(1 << 2);
 240                 if (sync_mode == OMAP_DMA_SYNC_BLOCK)
 241                         ccr |= 1 << 2;
 242                 p->dma_write(ccr, CCR2, lch);
 243         }
 244
 245         if (dma_omap2plus() && dma_trigger) {
 246                 u32 val;
 247
 248                 val = p->dma_read(CCR, lch);
 249
 250                 /* DMA_SYNCHRO_CONTROL_UPPER depends on the channel number */
 251                 val &= ~((1 << 23) | (3 << 19) | 0x1f);
 252                 val |= (dma_trigger & ~0x1f) << 14;
 253                 val |= dma_trigger & 0x1f;
 254
 255                 if (sync_mode & OMAP_DMA_SYNC_FRAME)
 256                         val |= 1 << 5;
 257                 else
 258                         val &= ~(1 << 5);
 259
 260                 if (sync_mode & OMAP_DMA_SYNC_BLOCK)
 261                         val |= 1 << 18;
 262                 else
 263                         val &= ~(1 << 18);
 264
 265                 if (src_or_dst_synch == OMAP_DMA_DST_SYNC_PREFETCH) {
 266                         val &= ~(1 << 24);      /* dest synch */
 267                         val |= (1 << 23);       /* Prefetch */
 268                 } else if (src_or_dst_synch) {
 269                         val |= 1 << 24;         /* source synch */
 270                 } else {
 271                         val &= ~(1 << 24);      /* dest synch */
 272                 }
 273                 p->dma_write(val, CCR, lch);
 274         }
 275
 276         p->dma_write(elem_count, CEN, lch);
 277         p->dma_write(frame_count, CFN, lch);
 278 }
 279 EXPORT_SYMBOL(omap_set_dma_transfer_params);
 280
 281 void omap_set_dma_write_mode(int lch, enum omap_dma_write_mode mode)
 282 {
 283         if (dma_omap2plus()) {
 284                 u32 csdp;
 285
 286                 csdp = p->dma_read(CSDP, lch);
 287                 csdp &= ~(0x3 << 16);
 288                 csdp |= (mode << 16);
 289                 p->dma_write(csdp, CSDP, lch);
 290         }
 291 }
 292 EXPORT_SYMBOL(omap_set_dma_write_mode);
 293
 294 void omap_set_dma_channel_mode(int lch, enum omap_dma_channel_mode mode)
 295 {
 296         if (dma_omap1() && !dma_omap15xx()) {
 297                 u32 l;
 298
 299                 l = p->dma_read(LCH_CTRL, lch);
 300                 l &= ~0x7;
 301                 l |= mode;
 302                 p->dma_write(l, LCH_CTRL, lch);
 303         }
 304 }
 305 EXPORT_SYMBOL(omap_set_dma_channel_mode);
 306
 307 /* Note that src_port is only for omap1 */
 308 void omap_set_dma_src_params(int lch, int src_port, int src_amode,
 309                              unsigned long src_start,
 310                              int src_ei, int src_fi)
 311 {
 312         u32 l;
 313
 314         if (dma_omap1()) {
 315                 u16 w;
 316
 317                 w = p->dma_read(CSDP, lch);
 318                 w &= ~(0x1f << 2);
 319                 w |= src_port << 2;
 320                 p->dma_write(w, CSDP, lch);
 321         }
 322
 323         l = p->dma_read(CCR, lch);
 324         l &= ~(0x03 << 12);
 325         l |= src_amode << 12;
 326         p->dma_write(l, CCR, lch);
 327
 328         p->dma_write(src_start, CSSA, lch);
 329
 330         p->dma_write(src_ei, CSEI, lch);
 331         p->dma_write(src_fi, CSFI, lch);
 332 }
 333 EXPORT_SYMBOL(omap_set_dma_src_params);
 334
 335 void omap_set_dma_params(int lch, struct omap_dma_channel_params *params)
 336 {
 337         omap_set_dma_transfer_params(lch, params->data_type,
 338                                      params->elem_count, params->frame_count,
 339                                      params->sync_mode, params->trigger,
 340                                      params->src_or_dst_synch);
 341         omap_set_dma_src_params(lch, params->src_port,
 342                                 params->src_amode, params->src_start,
 343                                 params->src_ei, params->src_fi);
 344
 345         omap_set_dma_dest_params(lch, params->dst_port,
 346                                  params->dst_amode, params->dst_start,
 347                                  params->dst_ei, params->dst_fi);
 348         if (params->read_prio || params->write_prio)
 349                 omap_dma_set_prio_lch(lch, params->read_prio,
 350                                       params->write_prio);
 351 }
 352 EXPORT_SYMBOL(omap_set_dma_params);
 353
 354 void omap_set_dma_src_data_pack(int lch, int enable)
 355 {
 356         u32 l;
 357
 358         l = p->dma_read(CSDP, lch);
 359         l &= ~(1 << 6);
 360         if (enable)
 361                 l |= (1 << 6);
 362         p->dma_write(l, CSDP, lch);
 363 }
 364 EXPORT_SYMBOL(omap_set_dma_src_data_pack);
 365
 366 void omap_set_dma_src_burst_mode(int lch, enum omap_dma_burst_mode burst_mode)
 367 {
 368         unsigned int burst = 0;
 369         u32 l;
 370
 371         l = p->dma_read(CSDP, lch);
 372         l &= ~(0x03 << 7);
 373
 374         switch (burst_mode) {
 375         case OMAP_DMA_DATA_BURST_DIS:
 376                 break;
 377         case OMAP_DMA_DATA_BURST_4:
 378                 if (dma_omap2plus())
 379                         burst = 0x1;
 380                 else
 381                         burst = 0x2;
 382                 break;
 383         case OMAP_DMA_DATA_BURST_8:
 384                 if (dma_omap2plus()) {
 385                         burst = 0x2;
 386                         break;
 387                 }
 388                 /*
 389                  * not supported by current hardware on OMAP1
 390                  * w |= (0x03 << 7);
 391                  * fall through
 392                  */
 393         case OMAP_DMA_DATA_BURST_16:
 394                 if (dma_omap2plus()) {
 395                         burst = 0x3;
 396                         break;
 397                 }
 398                 /*
 399                  * OMAP1 don't support burst 16
 400                  * fall through
 401                  */
 402         default:
 403                 BUG();
 404         }
 405
 406         l |= (burst << 7);
 407         p->dma_write(l, CSDP, lch);
 408 }
 409 EXPORT_SYMBOL(omap_set_dma_src_burst_mode);
 410
 411 /* Note that dest_port is only for OMAP1 */
 412 void omap_set_dma_dest_params(int lch, int dest_port, int dest_amode,
 413                               unsigned long dest_start,
 414                               int dst_ei, int dst_fi)
 415 {
 416         u32 l;
 417
 418         if (dma_omap1()) {
 419                 l = p->dma_read(CSDP, lch);
 420                 l &= ~(0x1f << 9);
 421                 l |= dest_port << 9;
 422                 p->dma_write(l, CSDP, lch);
 423         }
 424
 425         l = p->dma_read(CCR, lch);
 426         l &= ~(0x03 << 14);
 427         l |= dest_amode << 14;
 428         p->dma_write(l, CCR, lch);
 429
 430         p->dma_write(dest_start, CDSA, lch);
 431
 432         p->dma_write(dst_ei, CDEI, lch);
 433         p->dma_write(dst_fi, CDFI, lch);
 434 }
 435 EXPORT_SYMBOL(omap_set_dma_dest_params);
 436
 437 void omap_set_dma_dest_data_pack(int lch, int enable)
 438 {
 439         u32 l;
 440
 441         l = p->dma_read(CSDP, lch);
 442         l &= ~(1 << 13);
 443         if (enable)
 444                 l |= 1 << 13;
 445         p->dma_write(l, CSDP, lch);
 446 }
 447 EXPORT_SYMBOL(omap_set_dma_dest_data_pack);
 448
 449 void omap_set_dma_dest_burst_mode(int lch, enum omap_dma_burst_mode burst_mode)
 450 {
 451         unsigned int burst = 0;
 452         u32 l;
 453
 454         l = p->dma_read(CSDP, lch);
 455         l &= ~(0x03 << 14);
 456
 457         switch (burst_mode) {
 458         case OMAP_DMA_DATA_BURST_DIS:
 459                 break;
 460         case OMAP_DMA_DATA_BURST_4:
 461                 if (dma_omap2plus())
 462                         burst = 0x1;
 463                 else
 464                         burst = 0x2;
 465                 break;
 466         case OMAP_DMA_DATA_BURST_8:
 467                 if (dma_omap2plus())
 468                         burst = 0x2;
 469                 else
 470                         burst = 0x3;
 471                 break;
 472         case OMAP_DMA_DATA_BURST_16:
 473                 if (dma_omap2plus()) {
 474                         burst = 0x3;
 475                         break;
 476                 }
 477                 /*
 478                  * OMAP1 don't support burst 16
 479                  * fall through
 480                  */
 481         default:
 482                 printk(KERN_ERR "Invalid DMA burst mode\n");
 483                 BUG();
 484                 return;
 485         }
 486         l |= (burst << 14);
 487         p->dma_write(l, CSDP, lch);
 488 }
 489 EXPORT_SYMBOL(omap_set_dma_dest_burst_mode);
 490
 491 static inline void omap_enable_channel_irq(int lch)
 492 {
 493         /* Clear CSR */
 494         if (dma_omap1())
 495                 p->dma_read(CSR, lch);
 496         else
 497                 p->dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR, lch);
 498
 499         /* Enable some nice interrupts. */
 500         p->dma_write(dma_chan[lch].enabled_irqs, CICR, lch);
 501 }
 502
 503 static inline void omap_disable_channel_irq(int lch)
 504 {
 505         /* disable channel interrupts */
 506         p->dma_write(0, CICR, lch);
 507         /* Clear CSR */
 508         if (dma_omap1())
 509                 p->dma_read(CSR, lch);
 510         else
 511                 p->dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR, lch);
 512 }
 513
 514 void omap_enable_dma_irq(int lch, u16 bits)
 515 {
 516         dma_chan[lch].enabled_irqs |= bits;
 517 }
 518 EXPORT_SYMBOL(omap_enable_dma_irq);
 519
 520 void omap_disable_dma_irq(int lch, u16 bits)
 521 {
 522         dma_chan[lch].enabled_irqs &= ~bits;
 523 }
 524 EXPORT_SYMBOL(omap_disable_dma_irq);
 525
 526 static inline void enable_lnk(int lch)
 527 {
 528         u32 l;
 529
 530         l = p->dma_read(CLNK_CTRL, lch);
 531
 532         if (dma_omap1())
 533                 l &= ~(1 << 14);
 534
 535         /* Set the ENABLE_LNK bits */
 536         if (dma_chan[lch].next_lch != -1)
 537                 l = dma_chan[lch].next_lch | (1 << 15);
 538
 539 #ifndef CONFIG_ARCH_OMAP1
 540         if (dma_omap2plus())
 541                 if (dma_chan[lch].next_linked_ch != -1)
 542                         l = dma_chan[lch].next_linked_ch | (1 << 15);
 543 #endif
 544
 545         p->dma_write(l, CLNK_CTRL, lch);
 546 }
 547
 548 static inline void disable_lnk(int lch)
 549 {
 550         u32 l;
 551
 552         l = p->dma_read(CLNK_CTRL, lch);
 553
 554         /* Disable interrupts */
 555         omap_disable_channel_irq(lch);
 556
 557         if (dma_omap1()) {
 558                 /* Set the STOP_LNK bit */
 559                 l |= 1 << 14;
 560         }
 561
 562         if (dma_omap2plus()) {
 563                 /* Clear the ENABLE_LNK bit */
 564                 l &= ~(1 << 15);
 565         }
 566
 567         p->dma_write(l, CLNK_CTRL, lch);
 568         dma_chan[lch].flags &= ~OMAP_DMA_ACTIVE;
 569 }
 570
 571 static inline void omap2_enable_irq_lch(int lch)
 572 {
 573         u32 val;
 574         unsigned long flags;
 575
 576         if (dma_omap1())
 577                 return;
 578
 579         spin_lock_irqsave(&dma_chan_lock, flags);
 580         /* clear IRQ STATUS */
 581         p->dma_write(1 << lch, IRQSTATUS_L0, lch);
 582         /* Enable interrupt */
 583         val = p->dma_read(IRQENABLE_L0, lch);
 584         val |= 1 << lch;
 585         p->dma_write(val, IRQENABLE_L0, lch);
 586         spin_unlock_irqrestore(&dma_chan_lock, flags);
 587 }
 588
 589 static inline void omap2_disable_irq_lch(int lch)
 590 {
 591         u32 val;
 592         unsigned long flags;
 593
 594         if (dma_omap1())
 595                 return;
 596
 597         spin_lock_irqsave(&dma_chan_lock, flags);
 598         /* Disable interrupt */
 599         val = p->dma_read(IRQENABLE_L0, lch);
 600         val &= ~(1 << lch);
 601         p->dma_write(val, IRQENABLE_L0, lch);
 602         /* clear IRQ STATUS */
 603         p->dma_write(1 << lch, IRQSTATUS_L0, lch);
 604         spin_unlock_irqrestore(&dma_chan_lock, flags);
 605 }
 606
 607 int omap_request_dma(int dev_id, const char *dev_name,
 608                      void (*callback)(int lch, u16 ch_status, void *data),
 609                      void *data, int *dma_ch_out)
 610 {
 611         int ch, free_ch = -1;
 612         unsigned long flags;
 613         struct omap_dma_lch *chan;
 614
 615         WARN(strcmp(dev_name, "DMA engine"), "Using deprecated platform DMA API - please update to DMA engine");
 616
 617         spin_lock_irqsave(&dma_chan_lock, flags);
 618         for (ch = 0; ch < dma_chan_count; ch++) {
 619                 if (free_ch == -1 && dma_chan[ch].dev_id == -1) {
 620                         free_ch = ch;
 621                         /* Exit after first free channel found */
 622                         break;
 623                 }
 624         }
 625         if (free_ch == -1) {
 626                 spin_unlock_irqrestore(&dma_chan_lock, flags);
 627                 return -EBUSY;
 628         }
 629         chan = dma_chan + free_ch;
 630         chan->dev_id = dev_id;
 631
 632         if (p->clear_lch_regs)
 633                 p->clear_lch_regs(free_ch);
 634
 635         if (dma_omap2plus())
 636                 omap_clear_dma(free_ch);
 637
 638         spin_unlock_irqrestore(&dma_chan_lock, flags);
 639
 640         chan->dev_name = dev_name;
 641         chan->callback = callback;
 642         chan->data = data;
 643         chan->flags = 0;
 644
 645 #ifndef CONFIG_ARCH_OMAP1
 646         if (dma_omap2plus()) {
 647                 chan->chain_id = -1;
 648                 chan->next_linked_ch = -1;
 649         }
 650 #endif
 651
 652         chan->enabled_irqs = OMAP_DMA_DROP_IRQ | OMAP_DMA_BLOCK_IRQ;
 653
 654         if (dma_omap1())
 655                 chan->enabled_irqs |= OMAP1_DMA_TOUT_IRQ;
 656         else if (dma_omap2plus())
 657                 chan->enabled_irqs |= OMAP2_DMA_MISALIGNED_ERR_IRQ |
 658                         OMAP2_DMA_TRANS_ERR_IRQ;
 659
 660         if (dma_omap16xx()) {
 661                 /* If the sync device is set, configure it dynamically. */
 662                 if (dev_id != 0) {
 663                         set_gdma_dev(free_ch + 1, dev_id);
 664                         dev_id = free_ch + 1;
 665                 }
 666                 /*
 667                  * Disable the 1510 compatibility mode and set the sync device
 668                  * id.
 669                  */
 670                 p->dma_write(dev_id | (1 << 10), CCR, free_ch);
 671         } else if (dma_omap1()) {
 672                 p->dma_write(dev_id, CCR, free_ch);
 673         }
 674
 675         if (dma_omap2plus()) {
 676                 omap_enable_channel_irq(free_ch);
 677                 omap2_enable_irq_lch(free_ch);
 678         }
 679
 680         *dma_ch_out = free_ch;
 681
 682         return 0;
 683 }
 684 EXPORT_SYMBOL(omap_request_dma);
 685
 686 void omap_free_dma(int lch)
 687 {
 688         unsigned long flags;
 689
 690         if (dma_chan[lch].dev_id == -1) {
 691                 pr_err("omap_dma: trying to free unallocated DMA channel %d\n",
 692                        lch);
 693                 return;
 694         }
 695
 696         /* Disable interrupt for logical channel */
 697         if (dma_omap2plus())
 698                 omap2_disable_irq_lch(lch);
 699
 700         /* Disable all DMA interrupts for the channel. */
 701         omap_disable_channel_irq(lch);
 702
 703         /* Make sure the DMA transfer is stopped. */
 704         p->dma_write(0, CCR, lch);
 705
 706         /* Clear registers */
 707         if (dma_omap2plus())
 708                 omap_clear_dma(lch);
 709
 710         spin_lock_irqsave(&dma_chan_lock, flags);
 711         dma_chan[lch].dev_id = -1;
 712         dma_chan[lch].next_lch = -1;
 713         dma_chan[lch].callback = NULL;
 714         spin_unlock_irqrestore(&dma_chan_lock, flags);
 715 }
 716 EXPORT_SYMBOL(omap_free_dma);
 717
 718 /**
 719  * @brief omap_dma_set_global_params : Set global priority settings for dma
 720  *
 721  * @param arb_rate
 722  * @param max_fifo_depth
 723  * @param tparams - Number of threads to reserve : DMA_THREAD_RESERVE_NORM
 724  *                                                 DMA_THREAD_RESERVE_ONET
 725  *                                                 DMA_THREAD_RESERVE_TWOT
 726  *                                                 DMA_THREAD_RESERVE_THREET
 727  */
 728 void
 729 omap_dma_set_global_params(int arb_rate, int max_fifo_depth, int tparams)
 730 {
 731         u32 reg;
 732
 733         if (dma_omap1()) {
 734                 printk(KERN_ERR "FIXME: no %s on 15xx/16xx\n", __func__);
 735                 return;
 736         }
 737
 738         if (max_fifo_depth == 0)
 739                 max_fifo_depth = 1;
 740         if (arb_rate == 0)
 741                 arb_rate = 1;
 742
 743         reg = 0xff & max_fifo_depth;
 744         reg |= (0x3 & tparams) << 12;
 745         reg |= (arb_rate & 0xff) << 16;
 746
 747         p->dma_write(reg, GCR, 0);
 748 }
 749 EXPORT_SYMBOL(omap_dma_set_global_params);
 750
 751 /**
 752  * @brief omap_dma_set_prio_lch : Set channel wise priority settings
 753  *
 754  * @param lch
 755  * @param read_prio - Read priority
 756  * @param write_prio - Write priority
 757  * Both of the above can be set with one of the following values :
 758  *      DMA_CH_PRIO_HIGH/DMA_CH_PRIO_LOW
 759  */
 760 static int
 761 omap_dma_set_prio_lch(int lch, unsigned char read_prio,
 762                       unsigned char write_prio)
 763 {
 764         u32 l;
 765
 766         if (unlikely((lch < 0 || lch >= dma_lch_count))) {
 767                 printk(KERN_ERR "Invalid channel id\n");
 768                 return -EINVAL;
 769         }
 770         l = p->dma_read(CCR, lch);
 771         l &= ~((1 << 6) | (1 << 26));
 772         if (d->dev_caps & IS_RW_PRIORITY)
 773                 l |= ((read_prio & 0x1) << 6) | ((write_prio & 0x1) << 26);
 774         else
 775                 l |= ((read_prio & 0x1) << 6);
 776
 777         p->dma_write(l, CCR, lch);
 778
 779         return 0;
 780 }
 781
 782
 783 /*
 784  * Clears any DMA state so the DMA engine is ready to restart with new buffers
 785  * through omap_start_dma(). Any buffers in flight are discarded.
 786  */
 787 static void omap_clear_dma(int lch)
 788 {
 789         unsigned long flags;
 790
 791         local_irq_save(flags);
 792         p->clear_dma(lch);
 793         local_irq_restore(flags);
 794 }
 795
 796 void omap_start_dma(int lch)
 797 {
 798         u32 l;
 799
 800         /*
 801          * The CPC/CDAC register needs to be initialized to zero
 802          * before starting dma transfer.
 803          */
 804         if (dma_omap15xx())
 805                 p->dma_write(0, CPC, lch);
 806         else
 807                 p->dma_write(0, CDAC, lch);
 808
 809         if (!omap_dma_in_1510_mode() && dma_chan[lch].next_lch != -1) {
 810                 int next_lch, cur_lch;
 811                 char dma_chan_link_map[MAX_LOGICAL_DMA_CH_COUNT];
 812
 813                 /* Set the link register of the first channel */
 814                 enable_lnk(lch);
 815
 816                 memset(dma_chan_link_map, 0, sizeof(dma_chan_link_map));
 817                 dma_chan_link_map[lch] = 1;
 818
 819                 cur_lch = dma_chan[lch].next_lch;
 820                 do {
 821                         next_lch = dma_chan[cur_lch].next_lch;
 822
 823                         /* The loop case: we've been here already */
 824                         if (dma_chan_link_map[cur_lch])
 825                                 break;
 826                         /* Mark the current channel */
 827                         dma_chan_link_map[cur_lch] = 1;
 828
 829                         enable_lnk(cur_lch);
 830                         omap_enable_channel_irq(cur_lch);
 831
 832                         cur_lch = next_lch;
 833                 } while (next_lch != -1);
 834         } else if (IS_DMA_ERRATA(DMA_ERRATA_PARALLEL_CHANNELS))
 835                 p->dma_write(lch, CLNK_CTRL, lch);
 836
 837         omap_enable_channel_irq(lch);
 838
 839         l = p->dma_read(CCR, lch);
 840
 841         if (IS_DMA_ERRATA(DMA_ERRATA_IFRAME_BUFFERING))
 842                         l |= OMAP_DMA_CCR_BUFFERING_DISABLE;
 843         l |= OMAP_DMA_CCR_EN;
 844
 845         /*
 846          * As dma_write() uses IO accessors which are weakly ordered, there
 847          * is no guarantee that data in coherent DMA memory will be visible
 848          * to the DMA device.  Add a memory barrier here to ensure that any
 849          * such data is visible prior to enabling DMA.
 850          */
 851         mb();
 852         p->dma_write(l, CCR, lch);
 853
 854         dma_chan[lch].flags |= OMAP_DMA_ACTIVE;
 855 }
 856 EXPORT_SYMBOL(omap_start_dma);
 857
 858 void omap_stop_dma(int lch)
 859 {
 860         u32 l;
 861
 862         /* Disable all interrupts on the channel */
 863         omap_disable_channel_irq(lch);
 864
 865         l = p->dma_read(CCR, lch);
 866         if (IS_DMA_ERRATA(DMA_ERRATA_i541) &&
 867                         (l & OMAP_DMA_CCR_SEL_SRC_DST_SYNC)) {
 868                 int i = 0;
 869                 u32 sys_cf;
 870
 871                 /* Configure No-Standby */
 872                 l = p->dma_read(OCP_SYSCONFIG, lch);
 873                 sys_cf = l;
 874                 l &= ~DMA_SYSCONFIG_MIDLEMODE_MASK;
 875                 l |= DMA_SYSCONFIG_MIDLEMODE(DMA_IDLEMODE_NO_IDLE);
 876                 p->dma_write(l , OCP_SYSCONFIG, 0);
 877
 878                 l = p->dma_read(CCR, lch);
 879                 l &= ~OMAP_DMA_CCR_EN;
 880                 p->dma_write(l, CCR, lch);
 881
 882                 /* Wait for sDMA FIFO drain */
 883                 l = p->dma_read(CCR, lch);
 884                 while (i < 100 && (l & (OMAP_DMA_CCR_RD_ACTIVE |
 885                                         OMAP_DMA_CCR_WR_ACTIVE))) {
 886                         udelay(5);
 887                         i++;
 888                         l = p->dma_read(CCR, lch);
 889                 }
 890                 if (i >= 100)
 891                         pr_err("DMA drain did not complete on lch %d\n", lch);
 892                 /* Restore OCP_SYSCONFIG */
 893                 p->dma_write(sys_cf, OCP_SYSCONFIG, lch);
 894         } else {
 895                 l &= ~OMAP_DMA_CCR_EN;
 896                 p->dma_write(l, CCR, lch);
 897         }
 898
 899         /*
 900          * Ensure that data transferred by DMA is visible to any access
 901          * after DMA has been disabled.  This is important for coherent
 902          * DMA regions.
 903          */
 904         mb();
 905
 906         if (!omap_dma_in_1510_mode() && dma_chan[lch].next_lch != -1) {
 907                 int next_lch, cur_lch = lch;
 908                 char dma_chan_link_map[MAX_LOGICAL_DMA_CH_COUNT];
 909
 910                 memset(dma_chan_link_map, 0, sizeof(dma_chan_link_map));
 911                 do {
 912                         /* The loop case: we've been here already */
 913                         if (dma_chan_link_map[cur_lch])
 914                                 break;
 915                         /* Mark the current channel */
 916                         dma_chan_link_map[cur_lch] = 1;
 917
 918                         disable_lnk(cur_lch);
 919
 920                         next_lch = dma_chan[cur_lch].next_lch;
 921                         cur_lch = next_lch;
 922                 } while (next_lch != -1);
 923         }
 924
 925         dma_chan[lch].flags &= ~OMAP_DMA_ACTIVE;
 926 }
 927 EXPORT_SYMBOL(omap_stop_dma);
 928
 929 /*
 930  * Allows changing the DMA callback function or data. This may be needed if
 931  * the driver shares a single DMA channel for multiple dma triggers.
 932  */
 933 int omap_set_dma_callback(int lch,
 934                           void (*callback)(int lch, u16 ch_status, void *data),
 935                           void *data)
 936 {
 937         unsigned long flags;
 938
 939         if (lch < 0)
 940                 return -ENODEV;
 941
 942         spin_lock_irqsave(&dma_chan_lock, flags);
 943         if (dma_chan[lch].dev_id == -1) {
 944                 printk(KERN_ERR "DMA callback for not set for free channel\n");
 945                 spin_unlock_irqrestore(&dma_chan_lock, flags);
 946                 return -EINVAL;
 947         }
 948         dma_chan[lch].callback = callback;
 949         dma_chan[lch].data = data;
 950         spin_unlock_irqrestore(&dma_chan_lock, flags);
 951
 952         return 0;
 953 }
 954 EXPORT_SYMBOL(omap_set_dma_callback);
 955
 956 /*
 957  * Returns current physical source address for the given DMA channel.
 958  * If the channel is running the caller must disable interrupts prior calling
 959  * this function and process the returned value before re-enabling interrupt to
 960  * prevent races with the interrupt handler. Note that in continuous mode there
 961  * is a chance for CSSA_L register overflow between the two reads resulting
 962  * in incorrect return value.
 963  */
 964 dma_addr_t omap_get_dma_src_pos(int lch)
 965 {
 966         dma_addr_t offset = 0;
 967
 968         if (dma_omap15xx())
 969                 offset = p->dma_read(CPC, lch);
 970         else
 971                 offset = p->dma_read(CSAC, lch);
 972
 973         if (IS_DMA_ERRATA(DMA_ERRATA_3_3) && offset == 0)
 974                 offset = p->dma_read(CSAC, lch);
 975
 976         if (!dma_omap15xx()) {
 977                 /*
 978                  * CDAC == 0 indicates that the DMA transfer on the channel has
 979                  * not been started (no data has been transferred so far).
 980                  * Return the programmed source start address in this case.
 981                  */
 982                 if (likely(p->dma_read(CDAC, lch)))
 983                         offset = p->dma_read(CSAC, lch);
 984                 else
 985                         offset = p->dma_read(CSSA, lch);
 986         }
 987
 988         if (dma_omap1())
 989                 offset |= (p->dma_read(CSSA, lch) & 0xFFFF0000);
 990
 991         return offset;
 992 }
 993 EXPORT_SYMBOL(omap_get_dma_src_pos);
 994
 995 /*
 996  * Returns current physical destination address for the given DMA channel.
 997  * If the channel is running the caller must disable interrupts prior calling
 998  * this function and process the returned value before re-enabling interrupt to
 999  * prevent races with the interrupt handler. Note that in continuous mode there
1000  * is a chance for CDSA_L register overflow between the two reads resulting
1001  * in incorrect return value.
1002  */
1003 dma_addr_t omap_get_dma_dst_pos(int lch)
1004 {
1005         dma_addr_t offset = 0;
1006
1007         if (dma_omap15xx())
1008                 offset = p->dma_read(CPC, lch);
1009         else
1010                 offset = p->dma_read(CDAC, lch);
1011
1012         /*
1013          * omap 3.2/3.3 erratum: sometimes 0 is returned if CSAC/CDAC is
1014          * read before the DMA controller finished disabling the channel.
1015          */
1016         if (!dma_omap15xx() && offset == 0) {
1017                 offset = p->dma_read(CDAC, lch);
1018                 /*
1019                  * CDAC == 0 indicates that the DMA transfer on the channel has
1020                  * not been started (no data has been transferred so far).
1021                  * Return the programmed destination start address in this case.
1022                  */
1023                 if (unlikely(!offset))
1024                         offset = p->dma_read(CDSA, lch);
1025         }
1026
1027         if (dma_omap1())
1028                 offset |= (p->dma_read(CDSA, lch) & 0xFFFF0000);
1029
1030         return offset;
1031 }
1032 EXPORT_SYMBOL(omap_get_dma_dst_pos);
1033
1034 int omap_get_dma_active_status(int lch)
1035 {
1036         return (p->dma_read(CCR, lch) & OMAP_DMA_CCR_EN) != 0;
1037 }
1038 EXPORT_SYMBOL(omap_get_dma_active_status);
1039
1040 int omap_dma_running(void)
1041 {
1042         int lch;
1043
1044         if (dma_omap1())
1045                 if (omap_lcd_dma_running())
1046                         return 1;
1047
1048         for (lch = 0; lch < dma_chan_count; lch++)
1049                 if (p->dma_read(CCR, lch) & OMAP_DMA_CCR_EN)
1050                         return 1;
1051
1052         return 0;
1053 }
1054
1055 /*
1056  * lch_queue DMA will start right after lch_head one is finished.
1057  * For this DMA link to start, you still need to start (see omap_start_dma)
1058  * the first one. That will fire up the entire queue.
1059  */
1060 void omap_dma_link_lch(int lch_head, int lch_queue)
1061 {
1062         if (omap_dma_in_1510_mode()) {
1063                 if (lch_head == lch_queue) {
1064                         p->dma_write(p->dma_read(CCR, lch_head) | (3 << 8),
1065                                                                 CCR, lch_head);
1066                         return;
1067                 }
1068                 printk(KERN_ERR "DMA linking is not supported in 1510 mode\n");
1069                 BUG();
1070                 return;
1071         }
1072
1073         if ((dma_chan[lch_head].dev_id == -1) ||
1074             (dma_chan[lch_queue].dev_id == -1)) {
1075                 pr_err("omap_dma: trying to link non requested channels\n");
1076                 dump_stack();
1077         }
1078
1079         dma_chan[lch_head].next_lch = lch_queue;
1080 }
1081 EXPORT_SYMBOL(omap_dma_link_lch);
1082
1083 /*----------------------------------------------------------------------------*/
1084
1085 #ifdef CONFIG_ARCH_OMAP1
1086
1087 static int omap1_dma_handle_ch(int ch)
1088 {
1089         u32 csr;
1090
1091         if (enable_1510_mode && ch >= 6) {
1092                 csr = dma_chan[ch].saved_csr;
1093                 dma_chan[ch].saved_csr = 0;
1094         } else
1095                 csr = p->dma_read(CSR, ch);
1096         if (enable_1510_mode && ch <= 2 && (csr >> 7) != 0) {
1097                 dma_chan[ch + 6].saved_csr = csr >> 7;
1098                 csr &= 0x7f;
1099         }
1100         if ((csr & 0x3f) == 0)
1101                 return 0;
1102         if (unlikely(dma_chan[ch].dev_id == -1)) {
1103                 pr_warn("Spurious interrupt from DMA channel %d (CSR %04x)\n",
1104                         ch, csr);
1105                 return 0;
1106         }
1107         if (unlikely(csr & OMAP1_DMA_TOUT_IRQ))
1108                 pr_warn("DMA timeout with device %d\n", dma_chan[ch].dev_id);
1109         if (unlikely(csr & OMAP_DMA_DROP_IRQ))
1110                 pr_warn("DMA synchronization event drop occurred with device %d\n",
1111                         dma_chan[ch].dev_id);
1112         if (likely(csr & OMAP_DMA_BLOCK_IRQ))
1113                 dma_chan[ch].flags &= ~OMAP_DMA_ACTIVE;
1114         if (likely(dma_chan[ch].callback != NULL))
1115                 dma_chan[ch].callback(ch, csr, dma_chan[ch].data);
1116
1117         return 1;
1118 }
1119
1120 static irqreturn_t omap1_dma_irq_handler(int irq, void *dev_id)
1121 {
1122         int ch = ((int) dev_id) - 1;
1123         int handled = 0;
1124
1125         for (;;) {
1126                 int handled_now = 0;
1127
1128                 handled_now += omap1_dma_handle_ch(ch);
1129                 if (enable_1510_mode && dma_chan[ch + 6].saved_csr)
1130                         handled_now += omap1_dma_handle_ch(ch + 6);
1131                 if (!handled_now)
1132                         break;
1133                 handled += handled_now;
1134         }
1135
1136         return handled ? IRQ_HANDLED : IRQ_NONE;
1137 }
1138
1139 #else
1140 #define omap1_dma_irq_handler   NULL
1141 #endif
1142
1143 #ifdef CONFIG_ARCH_OMAP2PLUS
1144
1145 static int omap2_dma_handle_ch(int ch)
1146 {
1147         u32 status = p->dma_read(CSR, ch);
1148
1149         if (!status) {
1150                 if (printk_ratelimit())
1151                         pr_warn("Spurious DMA IRQ for lch %d\n", ch);
1152                 p->dma_write(1 << ch, IRQSTATUS_L0, ch);
1153                 return 0;
1154         }
1155         if (unlikely(dma_chan[ch].dev_id == -1)) {
1156                 if (printk_ratelimit())
1157                         pr_warn("IRQ %04x for non-allocated DMA channel %d\n",
1158                                 status, ch);
1159                 return 0;
1160         }
1161         if (unlikely(status & OMAP_DMA_DROP_IRQ))
1162                 pr_info("DMA synchronization event drop occurred with device %d\n",
1163                         dma_chan[ch].dev_id);
1164         if (unlikely(status & OMAP2_DMA_TRANS_ERR_IRQ)) {
1165                 printk(KERN_INFO "DMA transaction error with device %d\n",
1166                        dma_chan[ch].dev_id);
1167                 if (IS_DMA_ERRATA(DMA_ERRATA_i378)) {
1168                         u32 ccr;
1169
1170                         ccr = p->dma_read(CCR, ch);
1171                         ccr &= ~OMAP_DMA_CCR_EN;
1172                         p->dma_write(ccr, CCR, ch);
1173                         dma_chan[ch].flags &= ~OMAP_DMA_ACTIVE;
1174                 }
1175         }
1176         if (unlikely(status & OMAP2_DMA_SECURE_ERR_IRQ))
1177                 printk(KERN_INFO "DMA secure error with device %d\n",
1178                        dma_chan[ch].dev_id);
1179         if (unlikely(status & OMAP2_DMA_MISALIGNED_ERR_IRQ))
1180                 printk(KERN_INFO "DMA misaligned error with device %d\n",
1181                        dma_chan[ch].dev_id);
1182
1183         p->dma_write(status, CSR, ch);
1184         p->dma_write(1 << ch, IRQSTATUS_L0, ch);
1185         /* read back the register to flush the write */
1186         p->dma_read(IRQSTATUS_L0, ch);
1187
1188         /* If the ch is not chained then chain_id will be -1 */
1189         if (dma_chan[ch].chain_id != -1) {
1190                 int chain_id = dma_chan[ch].chain_id;
1191                 dma_chan[ch].state = DMA_CH_NOTSTARTED;
1192                 if (p->dma_read(CLNK_CTRL, ch) & (1 << 15))
1193                         dma_chan[dma_chan[ch].next_linked_ch].state =
1194                                                         DMA_CH_STARTED;
1195                 if (dma_linked_lch[chain_id].chain_mode ==
1196                                                 OMAP_DMA_DYNAMIC_CHAIN)
1197                         disable_lnk(ch);
1198
1199                 if (!OMAP_DMA_CHAIN_QEMPTY(chain_id))
1200                         OMAP_DMA_CHAIN_INCQHEAD(chain_id);
1201
1202                 status = p->dma_read(CSR, ch);
1203                 p->dma_write(status, CSR, ch);
1204         }
1205
1206         if (likely(dma_chan[ch].callback != NULL))
1207                 dma_chan[ch].callback(ch, status, dma_chan[ch].data);
1208
1209         return 0;
1210 }
1211
1212 /* STATUS register count is from 1-32 while our is 0-31 */
1213 static irqreturn_t omap2_dma_irq_handler(int irq, void *dev_id)
1214 {
1215         u32 val, enable_reg;
1216         int i;
1217
1218         val = p->dma_read(IRQSTATUS_L0, 0);
1219         if (val == 0) {
1220                 if (printk_ratelimit())
1221                         printk(KERN_WARNING "Spurious DMA IRQ\n");
1222                 return IRQ_HANDLED;
1223         }
1224         enable_reg = p->dma_read(IRQENABLE_L0, 0);
1225         val &= enable_reg; /* Dispatch only relevant interrupts */
1226         for (i = 0; i < dma_lch_count && val != 0; i++) {
1227                 if (val & 1)
1228                         omap2_dma_handle_ch(i);
1229                 val >>= 1;
1230         }
1231
1232         return IRQ_HANDLED;
1233 }
1234
1235 static struct irqaction omap24xx_dma_irq = {
1236         .name = "DMA",
1237         .handler = omap2_dma_irq_handler,
1238 };
1239
1240 #else
1241 static struct irqaction omap24xx_dma_irq;
1242 #endif
1243
1244 /*----------------------------------------------------------------------------*/
1245
1246 /*
1247  * Note that we are currently using only IRQENABLE_L0 and L1.
1248  * As the DSP may be using IRQENABLE_L2 and L3, let's not
1249  * touch those for now.
1250  */
1251 void omap_dma_global_context_save(void)
1252 {
1253         omap_dma_global_context.dma_irqenable_l0 =
1254                 p->dma_read(IRQENABLE_L0, 0);
1255         omap_dma_global_context.dma_irqenable_l1 =
1256                 p->dma_read(IRQENABLE_L1, 0);
1257         omap_dma_global_context.dma_ocp_sysconfig =
1258                 p->dma_read(OCP_SYSCONFIG, 0);
1259         omap_dma_global_context.dma_gcr = p->dma_read(GCR, 0);
1260 }
1261
1262 void omap_dma_global_context_restore(void)
1263 {
1264         int ch;
1265
1266         p->dma_write(omap_dma_global_context.dma_gcr, GCR, 0);
1267         p->dma_write(omap_dma_global_context.dma_ocp_sysconfig,
1268                 OCP_SYSCONFIG, 0);
1269         p->dma_write(omap_dma_global_context.dma_irqenable_l0,
1270                 IRQENABLE_L0, 0);
1271         p->dma_write(omap_dma_global_context.dma_irqenable_l1,
1272                 IRQENABLE_L1, 0);
1273
1274         if (IS_DMA_ERRATA(DMA_ROMCODE_BUG))
1275                 p->dma_write(0x3 , IRQSTATUS_L0, 0);
1276
1277         for (ch = 0; ch < dma_chan_count; ch++)
1278                 if (dma_chan[ch].dev_id != -1)
1279                         omap_clear_dma(ch);
1280 }
1281
1282 struct omap_system_dma_plat_info *omap_get_plat_info(void)
1283 {
1284         return p;
1285 }
1286 EXPORT_SYMBOL_GPL(omap_get_plat_info);
1287
1288 static int omap_system_dma_probe(struct platform_device *pdev)
1289 {
1290         int ch, ret = 0;
1291         int dma_irq;
1292         char irq_name[4];
1293         int irq_rel;
1294
1295         p = pdev->dev.platform_data;
1296         if (!p) {
1297                 dev_err(&pdev->dev,
1298                         "%s: System DMA initialized without platform data\n",
1299                         __func__);
1300                 return -EINVAL;
1301         }
1302
1303         d                       = p->dma_attr;
1304         errata                  = p->errata;
1305
1306         if ((d->dev_caps & RESERVE_CHANNEL) && omap_dma_reserve_channels
1307                         && (omap_dma_reserve_channels < d->lch_count))
1308                 d->lch_count    = omap_dma_reserve_channels;
1309
1310         dma_lch_count           = d->lch_count;
1311         dma_chan_count          = dma_lch_count;
1312         enable_1510_mode        = d->dev_caps & ENABLE_1510_MODE;
1313
1314         dma_chan = devm_kcalloc(&pdev->dev, dma_lch_count,
1315                                 sizeof(struct omap_dma_lch), GFP_KERNEL);
1316         if (!dma_chan) {
1317                 dev_err(&pdev->dev, "%s: kzalloc fail\n", __func__);
1318                 return -ENOMEM;
1319         }
1320
1321
1322         if (dma_omap2plus()) {
1323                 dma_linked_lch = kzalloc(sizeof(struct dma_link_info) *
1324                                                 dma_lch_count, GFP_KERNEL);
1325                 if (!dma_linked_lch) {
1326                         ret = -ENOMEM;
1327                         goto exit_dma_lch_fail;
1328                 }
1329         }
1330
1331         spin_lock_init(&dma_chan_lock);
1332         for (ch = 0; ch < dma_chan_count; ch++) {
1333                 omap_clear_dma(ch);
1334                 if (dma_omap2plus())
1335                         omap2_disable_irq_lch(ch);
1336
1337                 dma_chan[ch].dev_id = -1;
1338                 dma_chan[ch].next_lch = -1;
1339
1340                 if (ch >= 6 && enable_1510_mode)
1341                         continue;
1342
1343                 if (dma_omap1()) {
1344                         /*
1345                          * request_irq() doesn't like dev_id (ie. ch) being
1346                          * zero, so we have to kludge around this.
1347                          */
1348                         sprintf(&irq_name[0], "%d", ch);
1349                         dma_irq = platform_get_irq_byname(pdev, irq_name);
1350
1351                         if (dma_irq < 0) {
1352                                 ret = dma_irq;
1353                                 goto exit_dma_irq_fail;
1354                         }
1355
1356                         /* INT_DMA_LCD is handled in lcd_dma.c */
1357                         if (dma_irq == INT_DMA_LCD)
1358                                 continue;
1359
1360                         ret = request_irq(dma_irq,
1361                                         omap1_dma_irq_handler, 0, "DMA",
1362                                         (void *) (ch + 1));
1363                         if (ret != 0)
1364                                 goto exit_dma_irq_fail;
1365                 }
1366         }
1367
1368         if (d->dev_caps & IS_RW_PRIORITY)
1369                 omap_dma_set_global_params(DMA_DEFAULT_ARB_RATE,
1370                                 DMA_DEFAULT_FIFO_DEPTH, 0);
1371
1372         if (dma_omap2plus() && !(d->dev_caps & DMA_ENGINE_HANDLE_IRQ)) {
1373                 strcpy(irq_name, "0");
1374                 dma_irq = platform_get_irq_byname(pdev, irq_name);
1375                 if (dma_irq < 0) {
1376                         dev_err(&pdev->dev, "failed: request IRQ %d", dma_irq);
1377                         ret = dma_irq;
1378                         goto exit_dma_lch_fail;
1379                 }
1380                 ret = setup_irq(dma_irq, &omap24xx_dma_irq);
1381                 if (ret) {
1382                         dev_err(&pdev->dev, "set_up failed for IRQ %d for DMA (error %d)\n",
1383                                 dma_irq, ret);
1384                         goto exit_dma_lch_fail;
1385                 }
1386         }
1387
1388         /* reserve dma channels 0 and 1 in high security devices on 34xx */
1389         if (d->dev_caps & HS_CHANNELS_RESERVED) {
1390                 pr_info("Reserving DMA channels 0 and 1 for HS ROM code\n");
1391                 dma_chan[0].dev_id = 0;
1392                 dma_chan[1].dev_id = 1;
1393         }
1394         p->show_dma_caps();
1395         return 0;
1396
1397 exit_dma_irq_fail:
1398         dev_err(&pdev->dev, "unable to request IRQ %d for DMA (error %d)\n",
1399                 dma_irq, ret);
1400         for (irq_rel = 0; irq_rel < ch; irq_rel++) {
1401                 dma_irq = platform_get_irq(pdev, irq_rel);
1402                 free_irq(dma_irq, (void *)(irq_rel + 1));
1403         }
1404
1405 exit_dma_lch_fail:
1406         return ret;
1407 }
1408
1409 static int omap_system_dma_remove(struct platform_device *pdev)
1410 {
1411         int dma_irq;
1412
1413         if (dma_omap2plus()) {
1414                 char irq_name[4];
1415                 strcpy(irq_name, "0");
1416                 dma_irq = platform_get_irq_byname(pdev, irq_name);
1417                 if (dma_irq >= 0)
1418                         remove_irq(dma_irq, &omap24xx_dma_irq);
1419         } else {
1420                 int irq_rel = 0;
1421                 for ( ; irq_rel < dma_chan_count; irq_rel++) {
1422                         dma_irq = platform_get_irq(pdev, irq_rel);
1423                         free_irq(dma_irq, (void *)(irq_rel + 1));
1424                 }
1425         }
1426         return 0;
1427 }
1428
1429 static struct platform_driver omap_system_dma_driver = {
1430         .probe          = omap_system_dma_probe,
1431         .remove         = omap_system_dma_remove,
1432         .driver         = {
1433                 .name   = "omap_dma_system"
1434         },
1435 };
1436
1437 static int __init omap_system_dma_init(void)
1438 {
1439         return platform_driver_register(&omap_system_dma_driver);
1440 }
1441 arch_initcall(omap_system_dma_init);
1442
1443 static void __exit omap_system_dma_exit(void)
1444 {
1445         platform_driver_unregister(&omap_system_dma_driver);
1446 }
1447
1448 MODULE_DESCRIPTION("OMAP SYSTEM DMA DRIVER");
1449 MODULE_LICENSE("GPL");
1450 MODULE_ALIAS("platform:" DRIVER_NAME);
1451 MODULE_AUTHOR("Texas Instruments Inc");
1452
1453 /*
1454  * Reserve the omap SDMA channels using cmdline bootarg
1455  * "omap_dma_reserve_ch=". The valid range is 1 to 32
1456  */
1457 static int __init omap_dma_cmdline_reserve_ch(char *str)
1458 {
1459         if (get_option(&str, &omap_dma_reserve_channels) != 1)
1460                 omap_dma_reserve_channels = 0;
1461         return 1;
1462 }
1463
1464 __setup("omap_dma_reserve_ch=", omap_dma_cmdline_reserve_ch);
1465
1466