2 * sh73a0 processor support
4 * Copyright (C) 2010 Takashi Yoshii
5 * Copyright (C) 2010 Magnus Damm
6 * Copyright (C) 2008 Yoshihiro Shimoda
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; version 2 of the License.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 #include <linux/kernel.h>
18 #include <linux/init.h>
19 #include <linux/interrupt.h>
20 #include <linux/irq.h>
21 #include <linux/platform_device.h>
22 #include <linux/of_platform.h>
23 #include <linux/delay.h>
24 #include <linux/input.h>
25 #include <linux/i2c/i2c-sh_mobile.h>
27 #include <linux/serial_sci.h>
28 #include <linux/sh_dma.h>
29 #include <linux/sh_timer.h>
30 #include <linux/platform_data/sh_ipmmu.h>
31 #include <linux/platform_data/irq-renesas-intc-irqpin.h>
33 #include <asm/hardware/cache-l2x0.h>
34 #include <asm/mach-types.h>
35 #include <asm/mach/map.h>
36 #include <asm/mach/arch.h>
37 #include <asm/mach/time.h>
40 #include "dma-register.h"
45 static struct map_desc sh73a0_io_desc[] __initdata = {
46 /* create a 1:1 identity mapping for 0xe6xxxxxx
47 * used by CPGA, INTC and PFC.
50 .virtual = 0xe6000000,
51 .pfn = __phys_to_pfn(0xe6000000),
53 .type = MT_DEVICE_NONSHARED
57 void __init sh73a0_map_io(void)
60 iotable_init(sh73a0_io_desc, ARRAY_SIZE(sh73a0_io_desc));
64 static struct resource pfc_resources[] __initdata = {
65 DEFINE_RES_MEM(0xe6050000, 0x8000),
66 DEFINE_RES_MEM(0xe605801c, 0x000c),
69 void __init sh73a0_pinmux_init(void)
71 platform_device_register_simple("pfc-sh73a0", -1, pfc_resources,
72 ARRAY_SIZE(pfc_resources));
76 #define SH73A0_SCIF(scif_type, index, baseaddr, irq) \
77 static struct plat_sci_port scif##index##_platform_data = { \
79 .flags = UPF_BOOT_AUTOCONF, \
80 .scscr = SCSCR_RE | SCSCR_TE, \
83 static struct resource scif##index##_resources[] = { \
84 DEFINE_RES_MEM(baseaddr, 0x100), \
85 DEFINE_RES_IRQ(irq), \
88 static struct platform_device scif##index##_device = { \
91 .resource = scif##index##_resources, \
92 .num_resources = ARRAY_SIZE(scif##index##_resources), \
94 .platform_data = &scif##index##_platform_data, \
98 SH73A0_SCIF(PORT_SCIFA, 0, 0xe6c40000, gic_spi(72));
99 SH73A0_SCIF(PORT_SCIFA, 1, 0xe6c50000, gic_spi(73));
100 SH73A0_SCIF(PORT_SCIFA, 2, 0xe6c60000, gic_spi(74));
101 SH73A0_SCIF(PORT_SCIFA, 3, 0xe6c70000, gic_spi(75));
102 SH73A0_SCIF(PORT_SCIFA, 4, 0xe6c80000, gic_spi(78));
103 SH73A0_SCIF(PORT_SCIFA, 5, 0xe6cb0000, gic_spi(79));
104 SH73A0_SCIF(PORT_SCIFA, 6, 0xe6cc0000, gic_spi(156));
105 SH73A0_SCIF(PORT_SCIFA, 7, 0xe6cd0000, gic_spi(143));
106 SH73A0_SCIF(PORT_SCIFB, 8, 0xe6c30000, gic_spi(80));
108 static struct sh_timer_config cmt1_platform_data = {
109 .channels_mask = 0x3f,
112 static struct resource cmt1_resources[] = {
113 DEFINE_RES_MEM(0xe6138000, 0x200),
114 DEFINE_RES_IRQ(gic_spi(65)),
117 static struct platform_device cmt1_device = {
121 .platform_data = &cmt1_platform_data,
123 .resource = cmt1_resources,
124 .num_resources = ARRAY_SIZE(cmt1_resources),
128 static struct sh_timer_config tmu0_platform_data = {
132 static struct resource tmu0_resources[] = {
133 DEFINE_RES_MEM(0xfff60000, 0x2c),
134 DEFINE_RES_IRQ(intcs_evt2irq(0xe80)),
135 DEFINE_RES_IRQ(intcs_evt2irq(0xea0)),
136 DEFINE_RES_IRQ(intcs_evt2irq(0xec0)),
139 static struct platform_device tmu0_device = {
143 .platform_data = &tmu0_platform_data,
145 .resource = tmu0_resources,
146 .num_resources = ARRAY_SIZE(tmu0_resources),
149 static struct resource i2c0_resources[] = {
150 [0] = DEFINE_RES_MEM(0xe6820000, 0x426),
152 .start = gic_spi(167),
154 .flags = IORESOURCE_IRQ,
158 static struct resource i2c1_resources[] = {
159 [0] = DEFINE_RES_MEM(0xe6822000, 0x426),
161 .start = gic_spi(51),
163 .flags = IORESOURCE_IRQ,
167 static struct resource i2c2_resources[] = {
168 [0] = DEFINE_RES_MEM(0xe6824000, 0x426),
170 .start = gic_spi(171),
172 .flags = IORESOURCE_IRQ,
176 static struct resource i2c3_resources[] = {
177 [0] = DEFINE_RES_MEM(0xe6826000, 0x426),
179 .start = gic_spi(183),
181 .flags = IORESOURCE_IRQ,
185 static struct resource i2c4_resources[] = {
186 [0] = DEFINE_RES_MEM(0xe6828000, 0x426),
188 .start = gic_spi(187),
190 .flags = IORESOURCE_IRQ,
194 static struct i2c_sh_mobile_platform_data i2c_platform_data = {
198 static struct platform_device i2c0_device = {
199 .name = "i2c-sh_mobile",
201 .resource = i2c0_resources,
202 .num_resources = ARRAY_SIZE(i2c0_resources),
204 .platform_data = &i2c_platform_data,
208 static struct platform_device i2c1_device = {
209 .name = "i2c-sh_mobile",
211 .resource = i2c1_resources,
212 .num_resources = ARRAY_SIZE(i2c1_resources),
214 .platform_data = &i2c_platform_data,
218 static struct platform_device i2c2_device = {
219 .name = "i2c-sh_mobile",
221 .resource = i2c2_resources,
222 .num_resources = ARRAY_SIZE(i2c2_resources),
224 .platform_data = &i2c_platform_data,
228 static struct platform_device i2c3_device = {
229 .name = "i2c-sh_mobile",
231 .resource = i2c3_resources,
232 .num_resources = ARRAY_SIZE(i2c3_resources),
234 .platform_data = &i2c_platform_data,
238 static struct platform_device i2c4_device = {
239 .name = "i2c-sh_mobile",
241 .resource = i2c4_resources,
242 .num_resources = ARRAY_SIZE(i2c4_resources),
244 .platform_data = &i2c_platform_data,
248 static const struct sh_dmae_slave_config sh73a0_dmae_slaves[] = {
250 .slave_id = SHDMA_SLAVE_SCIF0_TX,
252 .chcr = CHCR_TX(XMIT_SZ_8BIT),
255 .slave_id = SHDMA_SLAVE_SCIF0_RX,
257 .chcr = CHCR_RX(XMIT_SZ_8BIT),
260 .slave_id = SHDMA_SLAVE_SCIF1_TX,
262 .chcr = CHCR_TX(XMIT_SZ_8BIT),
265 .slave_id = SHDMA_SLAVE_SCIF1_RX,
267 .chcr = CHCR_RX(XMIT_SZ_8BIT),
270 .slave_id = SHDMA_SLAVE_SCIF2_TX,
272 .chcr = CHCR_TX(XMIT_SZ_8BIT),
275 .slave_id = SHDMA_SLAVE_SCIF2_RX,
277 .chcr = CHCR_RX(XMIT_SZ_8BIT),
280 .slave_id = SHDMA_SLAVE_SCIF3_TX,
282 .chcr = CHCR_TX(XMIT_SZ_8BIT),
285 .slave_id = SHDMA_SLAVE_SCIF3_RX,
287 .chcr = CHCR_RX(XMIT_SZ_8BIT),
290 .slave_id = SHDMA_SLAVE_SCIF4_TX,
292 .chcr = CHCR_TX(XMIT_SZ_8BIT),
295 .slave_id = SHDMA_SLAVE_SCIF4_RX,
297 .chcr = CHCR_RX(XMIT_SZ_8BIT),
300 .slave_id = SHDMA_SLAVE_SCIF5_TX,
302 .chcr = CHCR_TX(XMIT_SZ_8BIT),
305 .slave_id = SHDMA_SLAVE_SCIF5_RX,
307 .chcr = CHCR_RX(XMIT_SZ_8BIT),
310 .slave_id = SHDMA_SLAVE_SCIF6_TX,
312 .chcr = CHCR_TX(XMIT_SZ_8BIT),
315 .slave_id = SHDMA_SLAVE_SCIF6_RX,
317 .chcr = CHCR_RX(XMIT_SZ_8BIT),
320 .slave_id = SHDMA_SLAVE_SCIF7_TX,
322 .chcr = CHCR_TX(XMIT_SZ_8BIT),
325 .slave_id = SHDMA_SLAVE_SCIF7_RX,
327 .chcr = CHCR_RX(XMIT_SZ_8BIT),
330 .slave_id = SHDMA_SLAVE_SCIF8_TX,
332 .chcr = CHCR_TX(XMIT_SZ_8BIT),
335 .slave_id = SHDMA_SLAVE_SCIF8_RX,
337 .chcr = CHCR_RX(XMIT_SZ_8BIT),
340 .slave_id = SHDMA_SLAVE_SDHI0_TX,
342 .chcr = CHCR_TX(XMIT_SZ_16BIT),
345 .slave_id = SHDMA_SLAVE_SDHI0_RX,
347 .chcr = CHCR_RX(XMIT_SZ_16BIT),
350 .slave_id = SHDMA_SLAVE_SDHI1_TX,
352 .chcr = CHCR_TX(XMIT_SZ_16BIT),
355 .slave_id = SHDMA_SLAVE_SDHI1_RX,
357 .chcr = CHCR_RX(XMIT_SZ_16BIT),
360 .slave_id = SHDMA_SLAVE_SDHI2_TX,
362 .chcr = CHCR_TX(XMIT_SZ_16BIT),
365 .slave_id = SHDMA_SLAVE_SDHI2_RX,
367 .chcr = CHCR_RX(XMIT_SZ_16BIT),
370 .slave_id = SHDMA_SLAVE_MMCIF_TX,
372 .chcr = CHCR_TX(XMIT_SZ_32BIT),
375 .slave_id = SHDMA_SLAVE_MMCIF_RX,
377 .chcr = CHCR_RX(XMIT_SZ_32BIT),
382 #define DMAE_CHANNEL(_offset) \
384 .offset = _offset - 0x20, \
385 .dmars = _offset - 0x20 + 0x40, \
388 static const struct sh_dmae_channel sh73a0_dmae_channels[] = {
389 DMAE_CHANNEL(0x8000),
390 DMAE_CHANNEL(0x8080),
391 DMAE_CHANNEL(0x8100),
392 DMAE_CHANNEL(0x8180),
393 DMAE_CHANNEL(0x8200),
394 DMAE_CHANNEL(0x8280),
395 DMAE_CHANNEL(0x8300),
396 DMAE_CHANNEL(0x8380),
397 DMAE_CHANNEL(0x8400),
398 DMAE_CHANNEL(0x8480),
399 DMAE_CHANNEL(0x8500),
400 DMAE_CHANNEL(0x8580),
401 DMAE_CHANNEL(0x8600),
402 DMAE_CHANNEL(0x8680),
403 DMAE_CHANNEL(0x8700),
404 DMAE_CHANNEL(0x8780),
405 DMAE_CHANNEL(0x8800),
406 DMAE_CHANNEL(0x8880),
407 DMAE_CHANNEL(0x8900),
408 DMAE_CHANNEL(0x8980),
411 static struct sh_dmae_pdata sh73a0_dmae_platform_data = {
412 .slave = sh73a0_dmae_slaves,
413 .slave_num = ARRAY_SIZE(sh73a0_dmae_slaves),
414 .channel = sh73a0_dmae_channels,
415 .channel_num = ARRAY_SIZE(sh73a0_dmae_channels),
416 .ts_low_shift = TS_LOW_SHIFT,
417 .ts_low_mask = TS_LOW_BIT << TS_LOW_SHIFT,
418 .ts_high_shift = TS_HI_SHIFT,
419 .ts_high_mask = TS_HI_BIT << TS_HI_SHIFT,
420 .ts_shift = dma_ts_shift,
421 .ts_shift_num = ARRAY_SIZE(dma_ts_shift),
422 .dmaor_init = DMAOR_DME,
425 static struct resource sh73a0_dmae_resources[] = {
426 DEFINE_RES_MEM(0xfe000020, 0x89e0),
429 .start = gic_spi(129),
431 .flags = IORESOURCE_IRQ,
434 /* IRQ for channels 0-19 */
435 .start = gic_spi(109),
437 .flags = IORESOURCE_IRQ,
441 static struct platform_device dma0_device = {
442 .name = "sh-dma-engine",
444 .resource = sh73a0_dmae_resources,
445 .num_resources = ARRAY_SIZE(sh73a0_dmae_resources),
447 .platform_data = &sh73a0_dmae_platform_data,
452 static const struct sh_dmae_slave_config sh73a0_mpdma_slaves[] = {
454 .slave_id = SHDMA_SLAVE_FSI2A_RX,
456 .chcr = CHCR_RX(XMIT_SZ_32BIT),
457 .mid_rid = 0xd6, /* CHECK ME */
459 .slave_id = SHDMA_SLAVE_FSI2A_TX,
461 .chcr = CHCR_TX(XMIT_SZ_32BIT),
462 .mid_rid = 0xd5, /* CHECK ME */
464 .slave_id = SHDMA_SLAVE_FSI2C_RX,
466 .chcr = CHCR_RX(XMIT_SZ_32BIT),
467 .mid_rid = 0xda, /* CHECK ME */
469 .slave_id = SHDMA_SLAVE_FSI2C_TX,
471 .chcr = CHCR_TX(XMIT_SZ_32BIT),
472 .mid_rid = 0xd9, /* CHECK ME */
474 .slave_id = SHDMA_SLAVE_FSI2B_RX,
476 .chcr = CHCR_RX(XMIT_SZ_32BIT),
477 .mid_rid = 0x8e, /* CHECK ME */
479 .slave_id = SHDMA_SLAVE_FSI2B_TX,
481 .chcr = CHCR_RX(XMIT_SZ_32BIT),
482 .mid_rid = 0x8d, /* CHECK ME */
484 .slave_id = SHDMA_SLAVE_FSI2D_RX,
486 .chcr = CHCR_RX(XMIT_SZ_32BIT),
487 .mid_rid = 0x9a, /* CHECK ME */
491 #define MPDMA_CHANNEL(a, b, c) \
496 .chclr_offset = (0x220 - 0x20) + a \
499 static const struct sh_dmae_channel sh73a0_mpdma_channels[] = {
500 MPDMA_CHANNEL(0x00, 0, 0),
501 MPDMA_CHANNEL(0x10, 0, 8),
502 MPDMA_CHANNEL(0x20, 4, 0),
503 MPDMA_CHANNEL(0x30, 4, 8),
504 MPDMA_CHANNEL(0x50, 8, 0),
505 MPDMA_CHANNEL(0x70, 8, 8),
508 static struct sh_dmae_pdata sh73a0_mpdma_platform_data = {
509 .slave = sh73a0_mpdma_slaves,
510 .slave_num = ARRAY_SIZE(sh73a0_mpdma_slaves),
511 .channel = sh73a0_mpdma_channels,
512 .channel_num = ARRAY_SIZE(sh73a0_mpdma_channels),
513 .ts_low_shift = TS_LOW_SHIFT,
514 .ts_low_mask = TS_LOW_BIT << TS_LOW_SHIFT,
515 .ts_high_shift = TS_HI_SHIFT,
516 .ts_high_mask = TS_HI_BIT << TS_HI_SHIFT,
517 .ts_shift = dma_ts_shift,
518 .ts_shift_num = ARRAY_SIZE(dma_ts_shift),
519 .dmaor_init = DMAOR_DME,
523 /* Resource order important! */
524 static struct resource sh73a0_mpdma_resources[] = {
525 /* Channel registers and DMAOR */
526 DEFINE_RES_MEM(0xec618020, 0x270),
528 DEFINE_RES_MEM(0xec619000, 0xc),
531 .start = gic_spi(181),
533 .flags = IORESOURCE_IRQ,
536 /* IRQ for channels 0-5 */
537 .start = gic_spi(175),
539 .flags = IORESOURCE_IRQ,
543 static struct platform_device mpdma0_device = {
544 .name = "sh-dma-engine",
546 .resource = sh73a0_mpdma_resources,
547 .num_resources = ARRAY_SIZE(sh73a0_mpdma_resources),
549 .platform_data = &sh73a0_mpdma_platform_data,
553 static struct resource pmu_resources[] = {
555 .start = gic_spi(55),
557 .flags = IORESOURCE_IRQ,
560 .start = gic_spi(56),
562 .flags = IORESOURCE_IRQ,
566 static struct platform_device pmu_device = {
569 .num_resources = ARRAY_SIZE(pmu_resources),
570 .resource = pmu_resources,
573 /* an IPMMU module for ICB */
574 static struct resource ipmmu_resources[] = {
575 DEFINE_RES_MEM(0xfe951000, 0x100),
578 static const char * const ipmmu_dev_names[] = {
579 "sh_mobile_lcdc_fb.0",
582 static struct shmobile_ipmmu_platform_data ipmmu_platform_data = {
583 .dev_names = ipmmu_dev_names,
584 .num_dev_names = ARRAY_SIZE(ipmmu_dev_names),
587 static struct platform_device ipmmu_device = {
591 .platform_data = &ipmmu_platform_data,
593 .resource = ipmmu_resources,
594 .num_resources = ARRAY_SIZE(ipmmu_resources),
597 static struct renesas_intc_irqpin_config irqpin0_platform_data = {
598 .irq_base = irq_pin(0), /* IRQ0 -> IRQ7 */
599 .control_parent = true,
602 static struct resource irqpin0_resources[] = {
603 DEFINE_RES_MEM(0xe6900000, 4), /* ICR1A */
604 DEFINE_RES_MEM(0xe6900010, 4), /* INTPRI00A */
605 DEFINE_RES_MEM(0xe6900020, 1), /* INTREQ00A */
606 DEFINE_RES_MEM(0xe6900040, 1), /* INTMSK00A */
607 DEFINE_RES_MEM(0xe6900060, 1), /* INTMSKCLR00A */
608 DEFINE_RES_IRQ(gic_spi(1)), /* IRQ0 */
609 DEFINE_RES_IRQ(gic_spi(2)), /* IRQ1 */
610 DEFINE_RES_IRQ(gic_spi(3)), /* IRQ2 */
611 DEFINE_RES_IRQ(gic_spi(4)), /* IRQ3 */
612 DEFINE_RES_IRQ(gic_spi(5)), /* IRQ4 */
613 DEFINE_RES_IRQ(gic_spi(6)), /* IRQ5 */
614 DEFINE_RES_IRQ(gic_spi(7)), /* IRQ6 */
615 DEFINE_RES_IRQ(gic_spi(8)), /* IRQ7 */
618 static struct platform_device irqpin0_device = {
619 .name = "renesas_intc_irqpin",
621 .resource = irqpin0_resources,
622 .num_resources = ARRAY_SIZE(irqpin0_resources),
624 .platform_data = &irqpin0_platform_data,
628 static struct renesas_intc_irqpin_config irqpin1_platform_data = {
629 .irq_base = irq_pin(8), /* IRQ8 -> IRQ15 */
630 .control_parent = true, /* Disable spurious IRQ10 */
633 static struct resource irqpin1_resources[] = {
634 DEFINE_RES_MEM(0xe6900004, 4), /* ICR2A */
635 DEFINE_RES_MEM(0xe6900014, 4), /* INTPRI10A */
636 DEFINE_RES_MEM(0xe6900024, 1), /* INTREQ10A */
637 DEFINE_RES_MEM(0xe6900044, 1), /* INTMSK10A */
638 DEFINE_RES_MEM(0xe6900064, 1), /* INTMSKCLR10A */
639 DEFINE_RES_IRQ(gic_spi(9)), /* IRQ8 */
640 DEFINE_RES_IRQ(gic_spi(10)), /* IRQ9 */
641 DEFINE_RES_IRQ(gic_spi(11)), /* IRQ10 */
642 DEFINE_RES_IRQ(gic_spi(12)), /* IRQ11 */
643 DEFINE_RES_IRQ(gic_spi(13)), /* IRQ12 */
644 DEFINE_RES_IRQ(gic_spi(14)), /* IRQ13 */
645 DEFINE_RES_IRQ(gic_spi(15)), /* IRQ14 */
646 DEFINE_RES_IRQ(gic_spi(16)), /* IRQ15 */
649 static struct platform_device irqpin1_device = {
650 .name = "renesas_intc_irqpin",
652 .resource = irqpin1_resources,
653 .num_resources = ARRAY_SIZE(irqpin1_resources),
655 .platform_data = &irqpin1_platform_data,
659 static struct renesas_intc_irqpin_config irqpin2_platform_data = {
660 .irq_base = irq_pin(16), /* IRQ16 -> IRQ23 */
661 .control_parent = true,
664 static struct resource irqpin2_resources[] = {
665 DEFINE_RES_MEM(0xe6900008, 4), /* ICR3A */
666 DEFINE_RES_MEM(0xe6900018, 4), /* INTPRI20A */
667 DEFINE_RES_MEM(0xe6900028, 1), /* INTREQ20A */
668 DEFINE_RES_MEM(0xe6900048, 1), /* INTMSK20A */
669 DEFINE_RES_MEM(0xe6900068, 1), /* INTMSKCLR20A */
670 DEFINE_RES_IRQ(gic_spi(17)), /* IRQ16 */
671 DEFINE_RES_IRQ(gic_spi(18)), /* IRQ17 */
672 DEFINE_RES_IRQ(gic_spi(19)), /* IRQ18 */
673 DEFINE_RES_IRQ(gic_spi(20)), /* IRQ19 */
674 DEFINE_RES_IRQ(gic_spi(21)), /* IRQ20 */
675 DEFINE_RES_IRQ(gic_spi(22)), /* IRQ21 */
676 DEFINE_RES_IRQ(gic_spi(23)), /* IRQ22 */
677 DEFINE_RES_IRQ(gic_spi(24)), /* IRQ23 */
680 static struct platform_device irqpin2_device = {
681 .name = "renesas_intc_irqpin",
683 .resource = irqpin2_resources,
684 .num_resources = ARRAY_SIZE(irqpin2_resources),
686 .platform_data = &irqpin2_platform_data,
690 static struct renesas_intc_irqpin_config irqpin3_platform_data = {
691 .irq_base = irq_pin(24), /* IRQ24 -> IRQ31 */
692 .control_parent = true,
695 static struct resource irqpin3_resources[] = {
696 DEFINE_RES_MEM(0xe690000c, 4), /* ICR4A */
697 DEFINE_RES_MEM(0xe690001c, 4), /* INTPRI30A */
698 DEFINE_RES_MEM(0xe690002c, 1), /* INTREQ30A */
699 DEFINE_RES_MEM(0xe690004c, 1), /* INTMSK30A */
700 DEFINE_RES_MEM(0xe690006c, 1), /* INTMSKCLR30A */
701 DEFINE_RES_IRQ(gic_spi(25)), /* IRQ24 */
702 DEFINE_RES_IRQ(gic_spi(26)), /* IRQ25 */
703 DEFINE_RES_IRQ(gic_spi(27)), /* IRQ26 */
704 DEFINE_RES_IRQ(gic_spi(28)), /* IRQ27 */
705 DEFINE_RES_IRQ(gic_spi(29)), /* IRQ28 */
706 DEFINE_RES_IRQ(gic_spi(30)), /* IRQ29 */
707 DEFINE_RES_IRQ(gic_spi(31)), /* IRQ30 */
708 DEFINE_RES_IRQ(gic_spi(32)), /* IRQ31 */
711 static struct platform_device irqpin3_device = {
712 .name = "renesas_intc_irqpin",
714 .resource = irqpin3_resources,
715 .num_resources = ARRAY_SIZE(irqpin3_resources),
717 .platform_data = &irqpin3_platform_data,
721 static struct platform_device *sh73a0_early_devices[] __initdata = {
736 static struct platform_device *sh73a0_late_devices[] __initdata = {
751 #define SRCR2 IOMEM(0xe61580b0)
753 void __init sh73a0_add_standard_devices(void)
755 /* Clear software reset bit on SY-DMAC module */
756 __raw_writel(__raw_readl(SRCR2) & ~(1 << 18), SRCR2);
758 platform_add_devices(sh73a0_early_devices,
759 ARRAY_SIZE(sh73a0_early_devices));
760 platform_add_devices(sh73a0_late_devices,
761 ARRAY_SIZE(sh73a0_late_devices));
764 /* do nothing for !CONFIG_SMP or !CONFIG_HAVE_TWD */
765 void __init __weak sh73a0_register_twd(void) { }
767 void __init sh73a0_earlytimer_init(void)
769 shmobile_init_delay();
770 #ifndef CONFIG_COMMON_CLK
773 shmobile_earlytimer_init();
774 sh73a0_register_twd();
777 void __init sh73a0_add_early_devices(void)
779 early_platform_add_devices(sh73a0_early_devices,
780 ARRAY_SIZE(sh73a0_early_devices));
782 /* setup early console here as well */
783 shmobile_setup_console();
788 static void __init sh73a0_generic_init(void)
790 #ifdef CONFIG_CACHE_L2X0
791 /* Shared attribute override enable, 64K*8way */
792 l2x0_init(IOMEM(0xf0100000), 0x00400000, 0xc20f0fff);
794 of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
797 static const char *sh73a0_boards_compat_dt[] __initdata = {
802 DT_MACHINE_START(SH73A0_DT, "Generic SH73A0 (Flattened Device Tree)")
803 .smp = smp_ops(sh73a0_smp_ops),
804 .map_io = sh73a0_map_io,
805 .init_early = shmobile_init_delay,
806 .init_machine = sh73a0_generic_init,
807 .init_late = shmobile_init_late,
808 .dt_compat = sh73a0_boards_compat_dt,
810 #endif /* CONFIG_USE_OF */