kernel/arch/arm/mach-rockchip/pm.c

   1 /*
   2  * Copyright (c) 2014, Fuzhou Rockchip Electronics Co., Ltd
   3  * Author: Tony Xie <tony.xie@rock-chips.com>
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms and conditions of the GNU General Public License,
   7  * version 2, as published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  */
  15
  16 #include <linux/init.h>
  17 #include <linux/io.h>
  18 #include <linux/kernel.h>
  19 #include <linux/of.h>
  20 #include <linux/of_address.h>
  21 #include <linux/regmap.h>
  22 #include <linux/suspend.h>
  23 #include <linux/mfd/syscon.h>
  24 #include <linux/regulator/machine.h>
  25
  26 #include <asm/cacheflush.h>
  27 #include <asm/tlbflush.h>
  28 #include <asm/suspend.h>
  29
  30 #include "pm.h"
  31
  32 /* These enum are option of low power mode */
  33 enum {
  34         ROCKCHIP_ARM_OFF_LOGIC_NORMAL = 0,
  35         ROCKCHIP_ARM_OFF_LOGIC_DEEP = 1,
  36 };
  37
  38 struct rockchip_pm_data {
  39         const struct platform_suspend_ops *ops;
  40         int (*init)(struct device_node *np);
  41 };
  42
  43 static void __iomem *rk3288_bootram_base;
  44 static phys_addr_t rk3288_bootram_phy;
  45
  46 static struct regmap *pmu_regmap;
  47 static struct regmap *sgrf_regmap;
  48
  49 static u32 rk3288_pmu_pwr_mode_con;
  50 static u32 rk3288_sgrf_soc_con0;
  51
  52 static inline u32 rk3288_l2_config(void)
  53 {
  54         u32 l2ctlr;
  55
  56         asm("mrc p15, 1, %0, c9, c0, 2" : "=r" (l2ctlr));
  57         return l2ctlr;
  58 }
  59
  60 static void rk3288_config_bootdata(void)
  61 {
  62         rkpm_bootdata_cpusp = rk3288_bootram_phy + (SZ_4K - 8);
  63         rkpm_bootdata_cpu_code = virt_to_phys(cpu_resume);
  64
  65         rkpm_bootdata_l2ctlr_f  = 1;
  66         rkpm_bootdata_l2ctlr = rk3288_l2_config();
  67 }
  68
  69 static void rk3288_slp_mode_set(int level)
  70 {
  71         u32 mode_set, mode_set1;
  72
  73         regmap_read(sgrf_regmap, RK3288_SGRF_SOC_CON0, &rk3288_sgrf_soc_con0);
  74
  75         regmap_read(pmu_regmap, RK3288_PMU_PWRMODE_CON,
  76                     &rk3288_pmu_pwr_mode_con);
  77
  78         /*
  79          * SGRF_FAST_BOOT_EN - system to boot from FAST_BOOT_ADDR
  80          * PCLK_WDT_GATE - disable WDT during suspend.
  81          */
  82         regmap_write(sgrf_regmap, RK3288_SGRF_SOC_CON0,
  83                      SGRF_PCLK_WDT_GATE | SGRF_FAST_BOOT_EN
  84                      | SGRF_PCLK_WDT_GATE_WRITE | SGRF_FAST_BOOT_EN_WRITE);
  85
  86         /*
  87          * The dapswjdp can not auto reset before resume, that cause it may
  88          * access some illegal address during resume. Let's disable it before
  89          * suspend, and the MASKROM will enable it back.
  90          */
  91         regmap_write(sgrf_regmap, RK3288_SGRF_CPU_CON0, SGRF_DAPDEVICEEN_WRITE);
  92
  93         /* booting address of resuming system is from this register value */
  94         regmap_write(sgrf_regmap, RK3288_SGRF_FAST_BOOT_ADDR,
  95                      rk3288_bootram_phy);
  96
  97         regmap_write(pmu_regmap, RK3288_PMU_WAKEUP_CFG1,
  98                      PMU_ARMINT_WAKEUP_EN);
  99
 100         mode_set = BIT(PMU_GLOBAL_INT_DISABLE) | BIT(PMU_L2FLUSH_EN) |
 101                    BIT(PMU_SREF0_ENTER_EN) | BIT(PMU_SREF1_ENTER_EN) |
 102                    BIT(PMU_DDR0_GATING_EN) | BIT(PMU_DDR1_GATING_EN) |
 103                    BIT(PMU_PWR_MODE_EN) | BIT(PMU_CHIP_PD_EN) |
 104                    BIT(PMU_SCU_EN);
 105
 106         mode_set1 = BIT(PMU_CLR_CORE) | BIT(PMU_CLR_CPUP);
 107
 108         if (level == ROCKCHIP_ARM_OFF_LOGIC_DEEP) {
 109                 /* arm off, logic deep sleep */
 110                 mode_set |= BIT(PMU_BUS_PD_EN) |
 111                             BIT(PMU_DDR1IO_RET_EN) | BIT(PMU_DDR0IO_RET_EN) |
 112                             BIT(PMU_OSC_24M_DIS) | BIT(PMU_PMU_USE_LF) |
 113                             BIT(PMU_ALIVE_USE_LF) | BIT(PMU_PLL_PD_EN);
 114
 115                 mode_set1 |= BIT(PMU_CLR_ALIVE) | BIT(PMU_CLR_BUS) |
 116                              BIT(PMU_CLR_PERI) | BIT(PMU_CLR_DMA);
 117         } else {
 118                 /*
 119                  * arm off, logic normal
 120                  * if pmu_clk_core_src_gate_en is not set,
 121                  * wakeup will be error
 122                  */
 123                 mode_set |= BIT(PMU_CLK_CORE_SRC_GATE_EN);
 124         }
 125
 126         regmap_write(pmu_regmap, RK3288_PMU_PWRMODE_CON, mode_set);
 127         regmap_write(pmu_regmap, RK3288_PMU_PWRMODE_CON1, mode_set1);
 128 }
 129
 130 static void rk3288_slp_mode_set_resume(void)
 131 {
 132         regmap_write(pmu_regmap, RK3288_PMU_PWRMODE_CON,
 133                      rk3288_pmu_pwr_mode_con);
 134
 135         regmap_write(sgrf_regmap, RK3288_SGRF_SOC_CON0,
 136                      rk3288_sgrf_soc_con0 | SGRF_PCLK_WDT_GATE_WRITE
 137                      | SGRF_FAST_BOOT_EN_WRITE);
 138 }
 139
 140 static int rockchip_lpmode_enter(unsigned long arg)
 141 {
 142         flush_cache_all();
 143
 144         cpu_do_idle();
 145
 146         pr_err("%s: Failed to suspend\n", __func__);
 147
 148         return 1;
 149 }
 150
 151 static int rk3288_suspend_enter(suspend_state_t state)
 152 {
 153         local_fiq_disable();
 154
 155         rk3288_slp_mode_set(ROCKCHIP_ARM_OFF_LOGIC_NORMAL);
 156
 157         cpu_suspend(0, rockchip_lpmode_enter);
 158
 159         rk3288_slp_mode_set_resume();
 160
 161         local_fiq_enable();
 162
 163         return 0;
 164 }
 165
 166 static int rk3288_suspend_prepare(void)
 167 {
 168         return regulator_suspend_prepare(PM_SUSPEND_MEM);
 169 }
 170
 171 static void rk3288_suspend_finish(void)
 172 {
 173         if (regulator_suspend_finish())
 174                 pr_err("%s: Suspend finish failed\n", __func__);
 175 }
 176
 177 static int rk3288_suspend_init(struct device_node *np)
 178 {
 179         struct device_node *sram_np;
 180         struct resource res;
 181         int ret;
 182
 183         pmu_regmap = syscon_node_to_regmap(np);
 184         if (IS_ERR(pmu_regmap)) {
 185                 pr_err("%s: could not find pmu regmap\n", __func__);
 186                 return PTR_ERR(pmu_regmap);
 187         }
 188
 189         sgrf_regmap = syscon_regmap_lookup_by_compatible(
 190                                 "rockchip,rk3288-sgrf");
 191         if (IS_ERR(sgrf_regmap)) {
 192                 pr_err("%s: could not find sgrf regmap\n", __func__);
 193                 return PTR_ERR(pmu_regmap);
 194         }
 195
 196         sram_np = of_find_compatible_node(NULL, NULL,
 197                                           "rockchip,rk3288-pmu-sram");
 198         if (!sram_np) {
 199                 pr_err("%s: could not find bootram dt node\n", __func__);
 200                 return -ENODEV;
 201         }
 202
 203         rk3288_bootram_base = of_iomap(sram_np, 0);
 204         if (!rk3288_bootram_base) {
 205                 pr_err("%s: could not map bootram base\n", __func__);
 206                 return -ENOMEM;
 207         }
 208
 209         ret = of_address_to_resource(sram_np, 0, &res);
 210         if (ret) {
 211                 pr_err("%s: could not get bootram phy addr\n", __func__);
 212                 return ret;
 213         }
 214         rk3288_bootram_phy = res.start;
 215
 216         of_node_put(sram_np);
 217
 218         rk3288_config_bootdata();
 219
 220         /* copy resume code and data to bootsram */
 221         memcpy(rk3288_bootram_base, rockchip_slp_cpu_resume,
 222                rk3288_bootram_sz);
 223
 224         regmap_write(pmu_regmap, RK3288_PMU_OSC_CNT, OSC_STABL_CNT_THRESH);
 225         regmap_write(pmu_regmap, RK3288_PMU_STABL_CNT, PMU_STABL_CNT_THRESH);
 226
 227         return 0;
 228 }
 229
 230 static const struct platform_suspend_ops rk3288_suspend_ops = {
 231         .enter   = rk3288_suspend_enter,
 232         .valid   = suspend_valid_only_mem,
 233         .prepare = rk3288_suspend_prepare,
 234         .finish  = rk3288_suspend_finish,
 235 };
 236
 237 static const struct rockchip_pm_data rk3288_pm_data __initconst = {
 238         .ops = &rk3288_suspend_ops,
 239         .init = rk3288_suspend_init,
 240 };
 241
 242 static const struct of_device_id rockchip_pmu_of_device_ids[] __initconst = {
 243         {
 244                 .compatible = "rockchip,rk3288-pmu",
 245                 .data = &rk3288_pm_data,
 246         },
 247         { /* sentinel */ },
 248 };
 249
 250 void __init rockchip_suspend_init(void)
 251 {
 252         const struct rockchip_pm_data *pm_data;
 253         const struct of_device_id *match;
 254         struct device_node *np;
 255         int ret;
 256
 257         np = of_find_matching_node_and_match(NULL, rockchip_pmu_of_device_ids,
 258                                              &match);
 259         if (!match) {
 260                 pr_err("Failed to find PMU node\n");
 261                 return;
 262         }
 263         pm_data = (struct rockchip_pm_data *) match->data;
 264
 265         if (pm_data->init) {
 266                 ret = pm_data->init(np);
 267
 268                 if (ret) {
 269                         pr_err("%s: matches init error %d\n", __func__, ret);
 270                         return;
 271                 }
 272         }
 273
 274         suspend_set_ops(pm_data->ops);
 275 }