kernel/arch/arm/mach-omap2/omap_hwmod_43xx_data.c

   1 /*
   2  * Copyright (C) 2013 Texas Instruments Incorporated
   3  *
   4  * Hwmod present only in AM43x and those that differ other than register
   5  * offsets as compared to AM335x.
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation version 2.
  10  *
  11  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
  12  * kind, whether express or implied; without even the implied warranty
  13  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14  * GNU General Public License for more details.
  15  */
  16
  17 #include <linux/platform_data/gpio-omap.h>
  18 #include <linux/platform_data/spi-omap2-mcspi.h>
  19 #include "omap_hwmod.h"
  20 #include "omap_hwmod_33xx_43xx_common_data.h"
  21 #include "prcm43xx.h"
  22 #include "omap_hwmod_common_data.h"
  23 #include "hdq1w.h"
  24
  25
  26 /* IP blocks */
  27 static struct omap_hwmod am43xx_l4_hs_hwmod = {
  28         .name           = "l4_hs",
  29         .class          = &am33xx_l4_hwmod_class,
  30         .clkdm_name     = "l3_clkdm",
  31         .flags          = HWMOD_INIT_NO_IDLE,
  32         .main_clk       = "l4hs_gclk",
  33         .prcm           = {
  34                 .omap4  = {
  35                         .clkctrl_offs   = AM43XX_CM_PER_L4HS_CLKCTRL_OFFSET,
  36                         .modulemode     = MODULEMODE_SWCTRL,
  37                 },
  38         },
  39 };
  40
  41 static struct omap_hwmod_rst_info am33xx_wkup_m3_resets[] = {
  42         { .name = "wkup_m3", .rst_shift = 3, .st_shift = 5 },
  43 };
  44
  45 static struct omap_hwmod am43xx_wkup_m3_hwmod = {
  46         .name           = "wkup_m3",
  47         .class          = &am33xx_wkup_m3_hwmod_class,
  48         .clkdm_name     = "l4_wkup_aon_clkdm",
  49         /* Keep hardreset asserted */
  50         .flags          = HWMOD_INIT_NO_RESET | HWMOD_NO_IDLEST,
  51         .main_clk       = "sys_clkin_ck",
  52         .prcm           = {
  53                 .omap4  = {
  54                         .clkctrl_offs   = AM43XX_CM_WKUP_WKUP_M3_CLKCTRL_OFFSET,
  55                         .rstctrl_offs   = AM43XX_RM_WKUP_RSTCTRL_OFFSET,
  56                         .rstst_offs     = AM43XX_RM_WKUP_RSTST_OFFSET,
  57                         .modulemode     = MODULEMODE_SWCTRL,
  58                 },
  59         },
  60         .rst_lines      = am33xx_wkup_m3_resets,
  61         .rst_lines_cnt  = ARRAY_SIZE(am33xx_wkup_m3_resets),
  62 };
  63
  64 static struct omap_hwmod am43xx_control_hwmod = {
  65         .name           = "control",
  66         .class          = &am33xx_control_hwmod_class,
  67         .clkdm_name     = "l4_wkup_clkdm",
  68         .flags          = HWMOD_INIT_NO_IDLE,
  69         .main_clk       = "sys_clkin_ck",
  70         .prcm           = {
  71                 .omap4  = {
  72                         .clkctrl_offs   = AM43XX_CM_WKUP_CONTROL_CLKCTRL_OFFSET,
  73                         .modulemode     = MODULEMODE_SWCTRL,
  74                 },
  75         },
  76 };
  77
  78 static struct omap_hwmod_opt_clk gpio0_opt_clks[] = {
  79         { .role = "dbclk", .clk = "gpio0_dbclk" },
  80 };
  81
  82 static struct omap_hwmod am43xx_gpio0_hwmod = {
  83         .name           = "gpio1",
  84         .class          = &am33xx_gpio_hwmod_class,
  85         .clkdm_name     = "l4_wkup_clkdm",
  86         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
  87         .main_clk       = "sys_clkin_ck",
  88         .prcm           = {
  89                 .omap4  = {
  90                         .clkctrl_offs   = AM43XX_CM_WKUP_GPIO0_CLKCTRL_OFFSET,
  91                         .modulemode     = MODULEMODE_SWCTRL,
  92                 },
  93         },
  94         .opt_clks       = gpio0_opt_clks,
  95         .opt_clks_cnt   = ARRAY_SIZE(gpio0_opt_clks),
  96         .dev_attr       = &gpio_dev_attr,
  97 };
  98
  99 static struct omap_hwmod_class_sysconfig am43xx_synctimer_sysc = {
 100         .rev_offs       = 0x0,
 101         .sysc_offs      = 0x4,
 102         .sysc_flags     = SYSC_HAS_SIDLEMODE,
 103         .idlemodes      = (SIDLE_FORCE | SIDLE_NO),
 104         .sysc_fields    = &omap_hwmod_sysc_type1,
 105 };
 106
 107 static struct omap_hwmod_class am43xx_synctimer_hwmod_class = {
 108         .name   = "synctimer",
 109         .sysc   = &am43xx_synctimer_sysc,
 110 };
 111
 112 static struct omap_hwmod am43xx_synctimer_hwmod = {
 113         .name           = "counter_32k",
 114         .class          = &am43xx_synctimer_hwmod_class,
 115         .clkdm_name     = "l4_wkup_aon_clkdm",
 116         .flags          = HWMOD_SWSUP_SIDLE,
 117         .main_clk       = "synctimer_32kclk",
 118         .prcm = {
 119                 .omap4 = {
 120                         .clkctrl_offs = AM43XX_CM_WKUP_SYNCTIMER_CLKCTRL_OFFSET,
 121                         .modulemode   = MODULEMODE_SWCTRL,
 122                 },
 123         },
 124 };
 125
 126 static struct omap_hwmod am43xx_timer8_hwmod = {
 127         .name           = "timer8",
 128         .class          = &am33xx_timer_hwmod_class,
 129         .clkdm_name     = "l4ls_clkdm",
 130         .main_clk       = "timer8_fck",
 131         .prcm           = {
 132                 .omap4  = {
 133                         .clkctrl_offs   = AM43XX_CM_PER_TIMER8_CLKCTRL_OFFSET,
 134                         .modulemode     = MODULEMODE_SWCTRL,
 135                 },
 136         },
 137 };
 138
 139 static struct omap_hwmod am43xx_timer9_hwmod = {
 140         .name           = "timer9",
 141         .class          = &am33xx_timer_hwmod_class,
 142         .clkdm_name     = "l4ls_clkdm",
 143         .main_clk       = "timer9_fck",
 144         .prcm           = {
 145                 .omap4  = {
 146                         .clkctrl_offs   = AM43XX_CM_PER_TIMER9_CLKCTRL_OFFSET,
 147                         .modulemode     = MODULEMODE_SWCTRL,
 148                 },
 149         },
 150 };
 151
 152 static struct omap_hwmod am43xx_timer10_hwmod = {
 153         .name           = "timer10",
 154         .class          = &am33xx_timer_hwmod_class,
 155         .clkdm_name     = "l4ls_clkdm",
 156         .main_clk       = "timer10_fck",
 157         .prcm           = {
 158                 .omap4  = {
 159                         .clkctrl_offs   = AM43XX_CM_PER_TIMER10_CLKCTRL_OFFSET,
 160                         .modulemode     = MODULEMODE_SWCTRL,
 161                 },
 162         },
 163 };
 164
 165 static struct omap_hwmod am43xx_timer11_hwmod = {
 166         .name           = "timer11",
 167         .class          = &am33xx_timer_hwmod_class,
 168         .clkdm_name     = "l4ls_clkdm",
 169         .main_clk       = "timer11_fck",
 170         .prcm           = {
 171                 .omap4  = {
 172                         .clkctrl_offs   = AM43XX_CM_PER_TIMER11_CLKCTRL_OFFSET,
 173                         .modulemode     = MODULEMODE_SWCTRL,
 174                 },
 175         },
 176 };
 177
 178 static struct omap_hwmod am43xx_epwmss3_hwmod = {
 179         .name           = "epwmss3",
 180         .class          = &am33xx_epwmss_hwmod_class,
 181         .clkdm_name     = "l4ls_clkdm",
 182         .main_clk       = "l4ls_gclk",
 183         .prcm           = {
 184                 .omap4  = {
 185                         .clkctrl_offs = AM43XX_CM_PER_EPWMSS3_CLKCTRL_OFFSET,
 186                         .modulemode   = MODULEMODE_SWCTRL,
 187                 },
 188         },
 189 };
 190
 191 static struct omap_hwmod am43xx_ehrpwm3_hwmod = {
 192         .name           = "ehrpwm3",
 193         .class          = &am33xx_ehrpwm_hwmod_class,
 194         .clkdm_name     = "l4ls_clkdm",
 195         .main_clk       = "l4ls_gclk",
 196 };
 197
 198 static struct omap_hwmod am43xx_epwmss4_hwmod = {
 199         .name           = "epwmss4",
 200         .class          = &am33xx_epwmss_hwmod_class,
 201         .clkdm_name     = "l4ls_clkdm",
 202         .main_clk       = "l4ls_gclk",
 203         .prcm           = {
 204                 .omap4  = {
 205                         .clkctrl_offs = AM43XX_CM_PER_EPWMSS4_CLKCTRL_OFFSET,
 206                         .modulemode   = MODULEMODE_SWCTRL,
 207                 },
 208         },
 209 };
 210
 211 static struct omap_hwmod am43xx_ehrpwm4_hwmod = {
 212         .name           = "ehrpwm4",
 213         .class          = &am33xx_ehrpwm_hwmod_class,
 214         .clkdm_name     = "l4ls_clkdm",
 215         .main_clk       = "l4ls_gclk",
 216 };
 217
 218 static struct omap_hwmod am43xx_epwmss5_hwmod = {
 219         .name           = "epwmss5",
 220         .class          = &am33xx_epwmss_hwmod_class,
 221         .clkdm_name     = "l4ls_clkdm",
 222         .main_clk       = "l4ls_gclk",
 223         .prcm           = {
 224                 .omap4  = {
 225                         .clkctrl_offs = AM43XX_CM_PER_EPWMSS5_CLKCTRL_OFFSET,
 226                         .modulemode   = MODULEMODE_SWCTRL,
 227                 },
 228         },
 229 };
 230
 231 static struct omap_hwmod am43xx_ehrpwm5_hwmod = {
 232         .name           = "ehrpwm5",
 233         .class          = &am33xx_ehrpwm_hwmod_class,
 234         .clkdm_name     = "l4ls_clkdm",
 235         .main_clk       = "l4ls_gclk",
 236 };
 237
 238 static struct omap_hwmod am43xx_spi2_hwmod = {
 239         .name           = "spi2",
 240         .class          = &am33xx_spi_hwmod_class,
 241         .clkdm_name     = "l4ls_clkdm",
 242         .main_clk       = "dpll_per_m2_div4_ck",
 243         .prcm           = {
 244                 .omap4  = {
 245                         .clkctrl_offs = AM43XX_CM_PER_SPI2_CLKCTRL_OFFSET,
 246                         .modulemode   = MODULEMODE_SWCTRL,
 247                 },
 248         },
 249         .dev_attr       = &mcspi_attrib,
 250 };
 251
 252 static struct omap_hwmod am43xx_spi3_hwmod = {
 253         .name           = "spi3",
 254         .class          = &am33xx_spi_hwmod_class,
 255         .clkdm_name     = "l4ls_clkdm",
 256         .main_clk       = "dpll_per_m2_div4_ck",
 257         .prcm           = {
 258                 .omap4  = {
 259                         .clkctrl_offs = AM43XX_CM_PER_SPI3_CLKCTRL_OFFSET,
 260                         .modulemode   = MODULEMODE_SWCTRL,
 261                 },
 262         },
 263         .dev_attr       = &mcspi_attrib,
 264 };
 265
 266 static struct omap_hwmod am43xx_spi4_hwmod = {
 267         .name           = "spi4",
 268         .class          = &am33xx_spi_hwmod_class,
 269         .clkdm_name     = "l4ls_clkdm",
 270         .main_clk       = "dpll_per_m2_div4_ck",
 271         .prcm           = {
 272                 .omap4  = {
 273                         .clkctrl_offs = AM43XX_CM_PER_SPI4_CLKCTRL_OFFSET,
 274                         .modulemode   = MODULEMODE_SWCTRL,
 275                 },
 276         },
 277         .dev_attr       = &mcspi_attrib,
 278 };
 279
 280 static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
 281         { .role = "dbclk", .clk = "gpio4_dbclk" },
 282 };
 283
 284 static struct omap_hwmod am43xx_gpio4_hwmod = {
 285         .name           = "gpio5",
 286         .class          = &am33xx_gpio_hwmod_class,
 287         .clkdm_name     = "l4ls_clkdm",
 288         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 289         .main_clk       = "l4ls_gclk",
 290         .prcm           = {
 291                 .omap4  = {
 292                         .clkctrl_offs = AM43XX_CM_PER_GPIO4_CLKCTRL_OFFSET,
 293                         .modulemode   = MODULEMODE_SWCTRL,
 294                 },
 295         },
 296         .opt_clks       = gpio4_opt_clks,
 297         .opt_clks_cnt   = ARRAY_SIZE(gpio4_opt_clks),
 298         .dev_attr       = &gpio_dev_attr,
 299 };
 300
 301 static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
 302         { .role = "dbclk", .clk = "gpio5_dbclk" },
 303 };
 304
 305 static struct omap_hwmod am43xx_gpio5_hwmod = {
 306         .name           = "gpio6",
 307         .class          = &am33xx_gpio_hwmod_class,
 308         .clkdm_name     = "l4ls_clkdm",
 309         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 310         .main_clk       = "l4ls_gclk",
 311         .prcm           = {
 312                 .omap4  = {
 313                         .clkctrl_offs = AM43XX_CM_PER_GPIO5_CLKCTRL_OFFSET,
 314                         .modulemode   = MODULEMODE_SWCTRL,
 315                 },
 316         },
 317         .opt_clks       = gpio5_opt_clks,
 318         .opt_clks_cnt   = ARRAY_SIZE(gpio5_opt_clks),
 319         .dev_attr       = &gpio_dev_attr,
 320 };
 321
 322 static struct omap_hwmod_class am43xx_ocp2scp_hwmod_class = {
 323         .name   = "ocp2scp",
 324 };
 325
 326 static struct omap_hwmod am43xx_ocp2scp0_hwmod = {
 327         .name           = "ocp2scp0",
 328         .class          = &am43xx_ocp2scp_hwmod_class,
 329         .clkdm_name     = "l4ls_clkdm",
 330         .main_clk       = "l4ls_gclk",
 331         .prcm = {
 332                 .omap4 = {
 333                         .clkctrl_offs = AM43XX_CM_PER_USBPHYOCP2SCP0_CLKCTRL_OFFSET,
 334                         .modulemode   = MODULEMODE_SWCTRL,
 335                 },
 336         },
 337 };
 338
 339 static struct omap_hwmod am43xx_ocp2scp1_hwmod = {
 340         .name           = "ocp2scp1",
 341         .class          = &am43xx_ocp2scp_hwmod_class,
 342         .clkdm_name     = "l4ls_clkdm",
 343         .main_clk       = "l4ls_gclk",
 344         .prcm = {
 345                 .omap4 = {
 346                         .clkctrl_offs   = AM43XX_CM_PER_USBPHYOCP2SCP1_CLKCTRL_OFFSET,
 347                         .modulemode     = MODULEMODE_SWCTRL,
 348                 },
 349         },
 350 };
 351
 352 static struct omap_hwmod_class_sysconfig am43xx_usb_otg_ss_sysc = {
 353         .rev_offs       = 0x0000,
 354         .sysc_offs      = 0x0010,
 355         .sysc_flags     = (SYSC_HAS_DMADISABLE | SYSC_HAS_MIDLEMODE |
 356                                 SYSC_HAS_SIDLEMODE),
 357         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 358                                 SIDLE_SMART_WKUP | MSTANDBY_FORCE |
 359                                 MSTANDBY_NO | MSTANDBY_SMART |
 360                                 MSTANDBY_SMART_WKUP),
 361         .sysc_fields    = &omap_hwmod_sysc_type2,
 362 };
 363
 364 static struct omap_hwmod_class am43xx_usb_otg_ss_hwmod_class = {
 365         .name   = "usb_otg_ss",
 366         .sysc   = &am43xx_usb_otg_ss_sysc,
 367 };
 368
 369 static struct omap_hwmod am43xx_usb_otg_ss0_hwmod = {
 370         .name           = "usb_otg_ss0",
 371         .class          = &am43xx_usb_otg_ss_hwmod_class,
 372         .clkdm_name     = "l3s_clkdm",
 373         .main_clk       = "l3s_gclk",
 374         .prcm = {
 375                 .omap4 = {
 376                         .clkctrl_offs   = AM43XX_CM_PER_USB_OTG_SS0_CLKCTRL_OFFSET,
 377                         .modulemode     = MODULEMODE_SWCTRL,
 378                 },
 379         },
 380 };
 381
 382 static struct omap_hwmod am43xx_usb_otg_ss1_hwmod = {
 383         .name           = "usb_otg_ss1",
 384         .class          = &am43xx_usb_otg_ss_hwmod_class,
 385         .clkdm_name     = "l3s_clkdm",
 386         .main_clk       = "l3s_gclk",
 387         .prcm = {
 388                 .omap4 = {
 389                         .clkctrl_offs   = AM43XX_CM_PER_USB_OTG_SS1_CLKCTRL_OFFSET,
 390                         .modulemode     = MODULEMODE_SWCTRL,
 391                 },
 392         },
 393 };
 394
 395 static struct omap_hwmod_class_sysconfig am43xx_qspi_sysc = {
 396         .sysc_offs      = 0x0010,
 397         .sysc_flags     = SYSC_HAS_SIDLEMODE,
 398         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 399                                 SIDLE_SMART_WKUP),
 400         .sysc_fields    = &omap_hwmod_sysc_type2,
 401 };
 402
 403 static struct omap_hwmod_class am43xx_qspi_hwmod_class = {
 404         .name   = "qspi",
 405         .sysc   = &am43xx_qspi_sysc,
 406 };
 407
 408 static struct omap_hwmod am43xx_qspi_hwmod = {
 409         .name           = "qspi",
 410         .class          = &am43xx_qspi_hwmod_class,
 411         .clkdm_name     = "l3s_clkdm",
 412         .main_clk       = "l3s_gclk",
 413         .prcm = {
 414                 .omap4 = {
 415                         .clkctrl_offs = AM43XX_CM_PER_QSPI_CLKCTRL_OFFSET,
 416                         .modulemode   = MODULEMODE_SWCTRL,
 417                 },
 418         },
 419 };
 420
 421 /*
 422  * 'adc/tsc' class
 423  * TouchScreen Controller (Analog-To-Digital Converter)
 424  */
 425 static struct omap_hwmod_class_sysconfig am43xx_adc_tsc_sysc = {
 426         .rev_offs       = 0x00,
 427         .sysc_offs      = 0x10,
 428         .sysc_flags     = SYSC_HAS_SIDLEMODE,
 429         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 430                           SIDLE_SMART_WKUP),
 431         .sysc_fields    = &omap_hwmod_sysc_type2,
 432 };
 433
 434 static struct omap_hwmod_class am43xx_adc_tsc_hwmod_class = {
 435         .name           = "adc_tsc",
 436         .sysc           = &am43xx_adc_tsc_sysc,
 437 };
 438
 439 static struct omap_hwmod am43xx_adc_tsc_hwmod = {
 440         .name           = "adc_tsc",
 441         .class          = &am43xx_adc_tsc_hwmod_class,
 442         .clkdm_name     = "l3s_tsc_clkdm",
 443         .main_clk       = "adc_tsc_fck",
 444         .prcm           = {
 445                 .omap4  = {
 446                         .clkctrl_offs   = AM43XX_CM_WKUP_ADC_TSC_CLKCTRL_OFFSET,
 447                         .modulemode     = MODULEMODE_SWCTRL,
 448                 },
 449         },
 450 };
 451
 452 /* dss */
 453
 454 static struct omap_hwmod am43xx_dss_core_hwmod = {
 455         .name           = "dss_core",
 456         .class          = &omap2_dss_hwmod_class,
 457         .clkdm_name     = "dss_clkdm",
 458         .main_clk       = "disp_clk",
 459         .prcm = {
 460                 .omap4 = {
 461                         .clkctrl_offs = AM43XX_CM_PER_DSS_CLKCTRL_OFFSET,
 462                         .modulemode   = MODULEMODE_SWCTRL,
 463                 },
 464         },
 465 };
 466
 467 /* dispc */
 468
 469 struct omap_dss_dispc_dev_attr am43xx_dss_dispc_dev_attr = {
 470         .manager_count          = 1,
 471         .has_framedonetv_irq    = 0
 472 };
 473
 474 static struct omap_hwmod_class_sysconfig am43xx_dispc_sysc = {
 475         .rev_offs       = 0x0000,
 476         .sysc_offs      = 0x0010,
 477         .syss_offs      = 0x0014,
 478         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SOFTRESET |
 479                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
 480                            SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_MIDLEMODE),
 481         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 482                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
 483         .sysc_fields    = &omap_hwmod_sysc_type1,
 484 };
 485
 486 static struct omap_hwmod_class am43xx_dispc_hwmod_class = {
 487         .name   = "dispc",
 488         .sysc   = &am43xx_dispc_sysc,
 489 };
 490
 491 static struct omap_hwmod am43xx_dss_dispc_hwmod = {
 492         .name           = "dss_dispc",
 493         .class          = &am43xx_dispc_hwmod_class,
 494         .clkdm_name     = "dss_clkdm",
 495         .main_clk       = "disp_clk",
 496         .prcm = {
 497                 .omap4 = {
 498                         .clkctrl_offs = AM43XX_CM_PER_DSS_CLKCTRL_OFFSET,
 499                 },
 500         },
 501         .dev_attr       = &am43xx_dss_dispc_dev_attr,
 502         .parent_hwmod   = &am43xx_dss_core_hwmod,
 503 };
 504
 505 /* rfbi */
 506
 507 static struct omap_hwmod am43xx_dss_rfbi_hwmod = {
 508         .name           = "dss_rfbi",
 509         .class          = &omap2_rfbi_hwmod_class,
 510         .clkdm_name     = "dss_clkdm",
 511         .main_clk       = "disp_clk",
 512         .prcm = {
 513                 .omap4 = {
 514                         .clkctrl_offs = AM43XX_CM_PER_DSS_CLKCTRL_OFFSET,
 515                 },
 516         },
 517         .parent_hwmod   = &am43xx_dss_core_hwmod,
 518 };
 519
 520 /* HDQ1W */
 521 static struct omap_hwmod_class_sysconfig am43xx_hdq1w_sysc = {
 522         .rev_offs       = 0x0000,
 523         .sysc_offs      = 0x0014,
 524         .syss_offs      = 0x0018,
 525         .sysc_flags     = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
 526         .sysc_fields    = &omap_hwmod_sysc_type1,
 527 };
 528
 529 static struct omap_hwmod_class am43xx_hdq1w_hwmod_class = {
 530         .name   = "hdq1w",
 531         .sysc   = &am43xx_hdq1w_sysc,
 532         .reset  = &omap_hdq1w_reset,
 533 };
 534
 535 static struct omap_hwmod am43xx_hdq1w_hwmod = {
 536         .name           = "hdq1w",
 537         .class          = &am43xx_hdq1w_hwmod_class,
 538         .clkdm_name     = "l4ls_clkdm",
 539         .prcm = {
 540                 .omap4 = {
 541                         .clkctrl_offs = AM43XX_CM_PER_HDQ1W_CLKCTRL_OFFSET,
 542                         .modulemode   = MODULEMODE_SWCTRL,
 543                 },
 544         },
 545 };
 546
 547 static struct omap_hwmod_class_sysconfig am43xx_vpfe_sysc = {
 548         .rev_offs       = 0x0,
 549         .sysc_offs      = 0x104,
 550         .sysc_flags     = SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE,
 551         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 552                                 MSTANDBY_FORCE | MSTANDBY_SMART | MSTANDBY_NO),
 553         .sysc_fields    = &omap_hwmod_sysc_type2,
 554 };
 555
 556 static struct omap_hwmod_class am43xx_vpfe_hwmod_class = {
 557         .name           = "vpfe",
 558         .sysc           = &am43xx_vpfe_sysc,
 559 };
 560
 561 static struct omap_hwmod am43xx_vpfe0_hwmod = {
 562         .name           = "vpfe0",
 563         .class          = &am43xx_vpfe_hwmod_class,
 564         .clkdm_name     = "l3s_clkdm",
 565         .prcm           = {
 566                 .omap4  = {
 567                         .modulemode     = MODULEMODE_SWCTRL,
 568                         .clkctrl_offs   = AM43XX_CM_PER_VPFE0_CLKCTRL_OFFSET,
 569                 },
 570         },
 571 };
 572
 573 static struct omap_hwmod am43xx_vpfe1_hwmod = {
 574         .name           = "vpfe1",
 575         .class          = &am43xx_vpfe_hwmod_class,
 576         .clkdm_name     = "l3s_clkdm",
 577         .prcm           = {
 578                 .omap4  = {
 579                         .modulemode     = MODULEMODE_SWCTRL,
 580                         .clkctrl_offs   = AM43XX_CM_PER_VPFE1_CLKCTRL_OFFSET,
 581                 },
 582         },
 583 };
 584
 585 /* Interfaces */
 586 static struct omap_hwmod_ocp_if am43xx_l3_main__l4_hs = {
 587         .master         = &am33xx_l3_main_hwmod,
 588         .slave          = &am43xx_l4_hs_hwmod,
 589         .clk            = "l3s_gclk",
 590         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 591 };
 592
 593 static struct omap_hwmod_ocp_if am43xx_wkup_m3__l4_wkup = {
 594         .master         = &am43xx_wkup_m3_hwmod,
 595         .slave          = &am33xx_l4_wkup_hwmod,
 596         .clk            = "sys_clkin_ck",
 597         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 598 };
 599
 600 static struct omap_hwmod_ocp_if am43xx_l4_wkup__wkup_m3 = {
 601         .master         = &am33xx_l4_wkup_hwmod,
 602         .slave          = &am43xx_wkup_m3_hwmod,
 603         .clk            = "sys_clkin_ck",
 604         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 605 };
 606
 607 static struct omap_hwmod_ocp_if am43xx_l3_main__pruss = {
 608         .master         = &am33xx_l3_main_hwmod,
 609         .slave          = &am33xx_pruss_hwmod,
 610         .clk            = "dpll_core_m4_ck",
 611         .user           = OCP_USER_MPU,
 612 };
 613
 614 static struct omap_hwmod_ocp_if am43xx_l4_wkup__smartreflex0 = {
 615         .master         = &am33xx_l4_wkup_hwmod,
 616         .slave          = &am33xx_smartreflex0_hwmod,
 617         .clk            = "sys_clkin_ck",
 618         .user           = OCP_USER_MPU,
 619 };
 620
 621 static struct omap_hwmod_ocp_if am43xx_l4_wkup__smartreflex1 = {
 622         .master         = &am33xx_l4_wkup_hwmod,
 623         .slave          = &am33xx_smartreflex1_hwmod,
 624         .clk            = "sys_clkin_ck",
 625         .user           = OCP_USER_MPU,
 626 };
 627
 628 static struct omap_hwmod_ocp_if am43xx_l4_wkup__control = {
 629         .master         = &am33xx_l4_wkup_hwmod,
 630         .slave          = &am43xx_control_hwmod,
 631         .clk            = "sys_clkin_ck",
 632         .user           = OCP_USER_MPU,
 633 };
 634
 635 static struct omap_hwmod_ocp_if am43xx_l4_wkup__i2c1 = {
 636         .master         = &am33xx_l4_wkup_hwmod,
 637         .slave          = &am33xx_i2c1_hwmod,
 638         .clk            = "sys_clkin_ck",
 639         .user           = OCP_USER_MPU,
 640 };
 641
 642 static struct omap_hwmod_ocp_if am43xx_l4_wkup__gpio0 = {
 643         .master         = &am33xx_l4_wkup_hwmod,
 644         .slave          = &am43xx_gpio0_hwmod,
 645         .clk            = "sys_clkin_ck",
 646         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 647 };
 648
 649 static struct omap_hwmod_ocp_if am43xx_l4_wkup__adc_tsc = {
 650         .master         = &am33xx_l4_wkup_hwmod,
 651         .slave          = &am43xx_adc_tsc_hwmod,
 652         .clk            = "dpll_core_m4_div2_ck",
 653         .user           = OCP_USER_MPU,
 654 };
 655
 656 static struct omap_hwmod_ocp_if am43xx_l4_hs__cpgmac0 = {
 657         .master         = &am43xx_l4_hs_hwmod,
 658         .slave          = &am33xx_cpgmac0_hwmod,
 659         .clk            = "cpsw_125mhz_gclk",
 660         .user           = OCP_USER_MPU,
 661 };
 662
 663 static struct omap_hwmod_ocp_if am43xx_l4_wkup__timer1 = {
 664         .master         = &am33xx_l4_wkup_hwmod,
 665         .slave          = &am33xx_timer1_hwmod,
 666         .clk            = "sys_clkin_ck",
 667         .user           = OCP_USER_MPU,
 668 };
 669
 670 static struct omap_hwmod_ocp_if am43xx_l4_wkup__uart1 = {
 671         .master         = &am33xx_l4_wkup_hwmod,
 672         .slave          = &am33xx_uart1_hwmod,
 673         .clk            = "sys_clkin_ck",
 674         .user           = OCP_USER_MPU,
 675 };
 676
 677 static struct omap_hwmod_ocp_if am43xx_l4_wkup__wd_timer1 = {
 678         .master         = &am33xx_l4_wkup_hwmod,
 679         .slave          = &am33xx_wd_timer1_hwmod,
 680         .clk            = "sys_clkin_ck",
 681         .user           = OCP_USER_MPU,
 682 };
 683
 684 static struct omap_hwmod_ocp_if am33xx_l4_wkup__synctimer = {
 685         .master         = &am33xx_l4_wkup_hwmod,
 686         .slave          = &am43xx_synctimer_hwmod,
 687         .clk            = "sys_clkin_ck",
 688         .user           = OCP_USER_MPU,
 689 };
 690
 691 static struct omap_hwmod_ocp_if am43xx_l4_ls__timer8 = {
 692         .master         = &am33xx_l4_ls_hwmod,
 693         .slave          = &am43xx_timer8_hwmod,
 694         .clk            = "l4ls_gclk",
 695         .user           = OCP_USER_MPU,
 696 };
 697
 698 static struct omap_hwmod_ocp_if am43xx_l4_ls__timer9 = {
 699         .master         = &am33xx_l4_ls_hwmod,
 700         .slave          = &am43xx_timer9_hwmod,
 701         .clk            = "l4ls_gclk",
 702         .user           = OCP_USER_MPU,
 703 };
 704
 705 static struct omap_hwmod_ocp_if am43xx_l4_ls__timer10 = {
 706         .master         = &am33xx_l4_ls_hwmod,
 707         .slave          = &am43xx_timer10_hwmod,
 708         .clk            = "l4ls_gclk",
 709         .user           = OCP_USER_MPU,
 710 };
 711
 712 static struct omap_hwmod_ocp_if am43xx_l4_ls__timer11 = {
 713         .master         = &am33xx_l4_ls_hwmod,
 714         .slave          = &am43xx_timer11_hwmod,
 715         .clk            = "l4ls_gclk",
 716         .user           = OCP_USER_MPU,
 717 };
 718
 719 static struct omap_hwmod_ocp_if am43xx_l4_ls__epwmss3 = {
 720         .master         = &am33xx_l4_ls_hwmod,
 721         .slave          = &am43xx_epwmss3_hwmod,
 722         .clk            = "l4ls_gclk",
 723         .user           = OCP_USER_MPU,
 724 };
 725
 726 static struct omap_hwmod_ocp_if am43xx_epwmss3__ehrpwm3 = {
 727         .master         = &am43xx_epwmss3_hwmod,
 728         .slave          = &am43xx_ehrpwm3_hwmod,
 729         .clk            = "l4ls_gclk",
 730         .user           = OCP_USER_MPU,
 731 };
 732
 733 static struct omap_hwmod_ocp_if am43xx_l4_ls__epwmss4 = {
 734         .master         = &am33xx_l4_ls_hwmod,
 735         .slave          = &am43xx_epwmss4_hwmod,
 736         .clk            = "l4ls_gclk",
 737         .user           = OCP_USER_MPU,
 738 };
 739
 740 static struct omap_hwmod_ocp_if am43xx_epwmss4__ehrpwm4 = {
 741         .master         = &am43xx_epwmss4_hwmod,
 742         .slave          = &am43xx_ehrpwm4_hwmod,
 743         .clk            = "l4ls_gclk",
 744         .user           = OCP_USER_MPU,
 745 };
 746
 747 static struct omap_hwmod_ocp_if am43xx_l4_ls__epwmss5 = {
 748         .master         = &am33xx_l4_ls_hwmod,
 749         .slave          = &am43xx_epwmss5_hwmod,
 750         .clk            = "l4ls_gclk",
 751         .user           = OCP_USER_MPU,
 752 };
 753
 754 static struct omap_hwmod_ocp_if am43xx_epwmss5__ehrpwm5 = {
 755         .master         = &am43xx_epwmss5_hwmod,
 756         .slave          = &am43xx_ehrpwm5_hwmod,
 757         .clk            = "l4ls_gclk",
 758         .user           = OCP_USER_MPU,
 759 };
 760
 761 static struct omap_hwmod_ocp_if am43xx_l4_ls__mcspi2 = {
 762         .master         = &am33xx_l4_ls_hwmod,
 763         .slave          = &am43xx_spi2_hwmod,
 764         .clk            = "l4ls_gclk",
 765         .user           = OCP_USER_MPU,
 766 };
 767
 768 static struct omap_hwmod_ocp_if am43xx_l4_ls__mcspi3 = {
 769         .master         = &am33xx_l4_ls_hwmod,
 770         .slave          = &am43xx_spi3_hwmod,
 771         .clk            = "l4ls_gclk",
 772         .user           = OCP_USER_MPU,
 773 };
 774
 775 static struct omap_hwmod_ocp_if am43xx_l4_ls__mcspi4 = {
 776         .master         = &am33xx_l4_ls_hwmod,
 777         .slave          = &am43xx_spi4_hwmod,
 778         .clk            = "l4ls_gclk",
 779         .user           = OCP_USER_MPU,
 780 };
 781
 782 static struct omap_hwmod_ocp_if am43xx_l4_ls__gpio4 = {
 783         .master         = &am33xx_l4_ls_hwmod,
 784         .slave          = &am43xx_gpio4_hwmod,
 785         .clk            = "l4ls_gclk",
 786         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 787 };
 788
 789 static struct omap_hwmod_ocp_if am43xx_l4_ls__gpio5 = {
 790         .master         = &am33xx_l4_ls_hwmod,
 791         .slave          = &am43xx_gpio5_hwmod,
 792         .clk            = "l4ls_gclk",
 793         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 794 };
 795
 796 static struct omap_hwmod_ocp_if am43xx_l4_ls__ocp2scp0 = {
 797         .master         = &am33xx_l4_ls_hwmod,
 798         .slave          = &am43xx_ocp2scp0_hwmod,
 799         .clk            = "l4ls_gclk",
 800         .user           = OCP_USER_MPU,
 801 };
 802
 803 static struct omap_hwmod_ocp_if am43xx_l4_ls__ocp2scp1 = {
 804         .master         = &am33xx_l4_ls_hwmod,
 805         .slave          = &am43xx_ocp2scp1_hwmod,
 806         .clk            = "l4ls_gclk",
 807         .user           = OCP_USER_MPU,
 808 };
 809
 810 static struct omap_hwmod_ocp_if am43xx_l3_s__usbotgss0 = {
 811         .master         = &am33xx_l3_s_hwmod,
 812         .slave          = &am43xx_usb_otg_ss0_hwmod,
 813         .clk            = "l3s_gclk",
 814         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 815 };
 816
 817 static struct omap_hwmod_ocp_if am43xx_l3_s__usbotgss1 = {
 818         .master         = &am33xx_l3_s_hwmod,
 819         .slave          = &am43xx_usb_otg_ss1_hwmod,
 820         .clk            = "l3s_gclk",
 821         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 822 };
 823
 824 static struct omap_hwmod_ocp_if am43xx_l3_s__qspi = {
 825         .master         = &am33xx_l3_s_hwmod,
 826         .slave          = &am43xx_qspi_hwmod,
 827         .clk            = "l3s_gclk",
 828         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 829 };
 830
 831 static struct omap_hwmod_ocp_if am43xx_dss__l3_main = {
 832         .master         = &am43xx_dss_core_hwmod,
 833         .slave          = &am33xx_l3_main_hwmod,
 834         .clk            = "l3_gclk",
 835         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 836 };
 837
 838 static struct omap_hwmod_ocp_if am43xx_l4_ls__dss = {
 839         .master         = &am33xx_l4_ls_hwmod,
 840         .slave          = &am43xx_dss_core_hwmod,
 841         .clk            = "l4ls_gclk",
 842         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 843 };
 844
 845 static struct omap_hwmod_ocp_if am43xx_l4_ls__dss_dispc = {
 846         .master         = &am33xx_l4_ls_hwmod,
 847         .slave          = &am43xx_dss_dispc_hwmod,
 848         .clk            = "l4ls_gclk",
 849         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 850 };
 851
 852 static struct omap_hwmod_ocp_if am43xx_l4_ls__dss_rfbi = {
 853         .master         = &am33xx_l4_ls_hwmod,
 854         .slave          = &am43xx_dss_rfbi_hwmod,
 855         .clk            = "l4ls_gclk",
 856         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 857 };
 858
 859 static struct omap_hwmod_ocp_if am43xx_l4_ls__hdq1w = {
 860         .master         = &am33xx_l4_ls_hwmod,
 861         .slave          = &am43xx_hdq1w_hwmod,
 862         .clk            = "l4ls_gclk",
 863         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 864 };
 865
 866 static struct omap_hwmod_ocp_if am43xx_l3__vpfe0 = {
 867         .master         = &am43xx_vpfe0_hwmod,
 868         .slave          = &am33xx_l3_main_hwmod,
 869         .clk            = "l3_gclk",
 870         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 871 };
 872
 873 static struct omap_hwmod_ocp_if am43xx_l3__vpfe1 = {
 874         .master         = &am43xx_vpfe1_hwmod,
 875         .slave          = &am33xx_l3_main_hwmod,
 876         .clk            = "l3_gclk",
 877         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 878 };
 879
 880 static struct omap_hwmod_ocp_if am43xx_l4_ls__vpfe0 = {
 881         .master         = &am33xx_l4_ls_hwmod,
 882         .slave          = &am43xx_vpfe0_hwmod,
 883         .clk            = "l4ls_gclk",
 884         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 885 };
 886
 887 static struct omap_hwmod_ocp_if am43xx_l4_ls__vpfe1 = {
 888         .master         = &am33xx_l4_ls_hwmod,
 889         .slave          = &am43xx_vpfe1_hwmod,
 890         .clk            = "l4ls_gclk",
 891         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 892 };
 893
 894 static struct omap_hwmod_ocp_if *am43xx_hwmod_ocp_ifs[] __initdata = {
 895         &am33xx_l4_wkup__synctimer,
 896         &am43xx_l4_ls__timer8,
 897         &am43xx_l4_ls__timer9,
 898         &am43xx_l4_ls__timer10,
 899         &am43xx_l4_ls__timer11,
 900         &am43xx_l4_ls__epwmss3,
 901         &am43xx_epwmss3__ehrpwm3,
 902         &am43xx_l4_ls__epwmss4,
 903         &am43xx_epwmss4__ehrpwm4,
 904         &am43xx_l4_ls__epwmss5,
 905         &am43xx_epwmss5__ehrpwm5,
 906         &am43xx_l4_ls__mcspi2,
 907         &am43xx_l4_ls__mcspi3,
 908         &am43xx_l4_ls__mcspi4,
 909         &am43xx_l4_ls__gpio4,
 910         &am43xx_l4_ls__gpio5,
 911         &am43xx_l3_main__pruss,
 912         &am33xx_mpu__l3_main,
 913         &am33xx_mpu__prcm,
 914         &am33xx_l3_s__l4_ls,
 915         &am33xx_l3_s__l4_wkup,
 916         &am43xx_l3_main__l4_hs,
 917         &am33xx_l3_main__l3_s,
 918         &am33xx_l3_main__l3_instr,
 919         &am33xx_l3_main__gfx,
 920         &am33xx_l3_s__l3_main,
 921         &am33xx_pruss__l3_main,
 922         &am43xx_wkup_m3__l4_wkup,
 923         &am33xx_gfx__l3_main,
 924         &am43xx_l4_wkup__wkup_m3,
 925         &am43xx_l4_wkup__control,
 926         &am43xx_l4_wkup__smartreflex0,
 927         &am43xx_l4_wkup__smartreflex1,
 928         &am43xx_l4_wkup__uart1,
 929         &am43xx_l4_wkup__timer1,
 930         &am43xx_l4_wkup__i2c1,
 931         &am43xx_l4_wkup__gpio0,
 932         &am43xx_l4_wkup__wd_timer1,
 933         &am43xx_l4_wkup__adc_tsc,
 934         &am43xx_l3_s__qspi,
 935         &am33xx_l4_per__dcan0,
 936         &am33xx_l4_per__dcan1,
 937         &am33xx_l4_per__gpio1,
 938         &am33xx_l4_per__gpio2,
 939         &am33xx_l4_per__gpio3,
 940         &am33xx_l4_per__i2c2,
 941         &am33xx_l4_per__i2c3,
 942         &am33xx_l4_per__mailbox,
 943         &am33xx_l4_ls__mcasp0,
 944         &am33xx_l4_ls__mcasp1,
 945         &am33xx_l4_ls__mmc0,
 946         &am33xx_l4_ls__mmc1,
 947         &am33xx_l3_s__mmc2,
 948         &am33xx_l4_ls__timer2,
 949         &am33xx_l4_ls__timer3,
 950         &am33xx_l4_ls__timer4,
 951         &am33xx_l4_ls__timer5,
 952         &am33xx_l4_ls__timer6,
 953         &am33xx_l4_ls__timer7,
 954         &am33xx_l3_main__tpcc,
 955         &am33xx_l4_ls__uart2,
 956         &am33xx_l4_ls__uart3,
 957         &am33xx_l4_ls__uart4,
 958         &am33xx_l4_ls__uart5,
 959         &am33xx_l4_ls__uart6,
 960         &am33xx_l4_ls__spinlock,
 961         &am33xx_l4_ls__elm,
 962         &am33xx_l4_ls__epwmss0,
 963         &am33xx_epwmss0__ecap0,
 964         &am33xx_epwmss0__eqep0,
 965         &am33xx_epwmss0__ehrpwm0,
 966         &am33xx_l4_ls__epwmss1,
 967         &am33xx_epwmss1__ecap1,
 968         &am33xx_epwmss1__eqep1,
 969         &am33xx_epwmss1__ehrpwm1,
 970         &am33xx_l4_ls__epwmss2,
 971         &am33xx_epwmss2__ecap2,
 972         &am33xx_epwmss2__eqep2,
 973         &am33xx_epwmss2__ehrpwm2,
 974         &am33xx_l3_s__gpmc,
 975         &am33xx_l4_ls__mcspi0,
 976         &am33xx_l4_ls__mcspi1,
 977         &am33xx_l3_main__tptc0,
 978         &am33xx_l3_main__tptc1,
 979         &am33xx_l3_main__tptc2,
 980         &am33xx_l3_main__ocmc,
 981         &am43xx_l4_hs__cpgmac0,
 982         &am33xx_cpgmac0__mdio,
 983         &am33xx_l3_main__sha0,
 984         &am33xx_l3_main__aes0,
 985         &am43xx_l4_ls__ocp2scp0,
 986         &am43xx_l4_ls__ocp2scp1,
 987         &am43xx_l3_s__usbotgss0,
 988         &am43xx_l3_s__usbotgss1,
 989         &am43xx_dss__l3_main,
 990         &am43xx_l4_ls__dss,
 991         &am43xx_l4_ls__dss_dispc,
 992         &am43xx_l4_ls__dss_rfbi,
 993         &am43xx_l4_ls__hdq1w,
 994         &am43xx_l3__vpfe0,
 995         &am43xx_l3__vpfe1,
 996         &am43xx_l4_ls__vpfe0,
 997         &am43xx_l4_ls__vpfe1,
 998         NULL,
 999 };
1000
1001 int __init am43xx_hwmod_init(void)
1002 {
1003         omap_hwmod_am43xx_reg();
1004         omap_hwmod_init();
1005         return omap_hwmod_register_links(am43xx_hwmod_ocp_ifs);
1006 }