kernel/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c

   1 /*
   2  *
   3  * Copyright (C) 2013 Texas Instruments Incorporated
   4  *
   5  * Hwmod common for AM335x and AM43x
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation version 2.
  10  *
  11  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
  12  * kind, whether express or implied; without even the implied warranty
  13  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14  * GNU General Public License for more details.
  15  */
  16
  17 #include <linux/platform_data/gpio-omap.h>
  18 #include <linux/platform_data/hsmmc-omap.h>
  19 #include <linux/platform_data/spi-omap2-mcspi.h>
  20 #include "omap_hwmod.h"
  21 #include "i2c.h"
  22 #include "wd_timer.h"
  23 #include "cm33xx.h"
  24 #include "prm33xx.h"
  25 #include "omap_hwmod_33xx_43xx_common_data.h"
  26 #include "prcm43xx.h"
  27 #include "common.h"
  28
  29 #define CLKCTRL(oh, clkctrl) ((oh).prcm.omap4.clkctrl_offs = (clkctrl))
  30 #define RSTCTRL(oh, rstctrl) ((oh).prcm.omap4.rstctrl_offs = (rstctrl))
  31 #define RSTST(oh, rstst) ((oh).prcm.omap4.rstst_offs = (rstst))
  32
  33 /*
  34  * 'l3' class
  35  * instance(s): l3_main, l3_s, l3_instr
  36  */
  37 static struct omap_hwmod_class am33xx_l3_hwmod_class = {
  38         .name           = "l3",
  39 };
  40
  41 struct omap_hwmod am33xx_l3_main_hwmod = {
  42         .name           = "l3_main",
  43         .class          = &am33xx_l3_hwmod_class,
  44         .clkdm_name     = "l3_clkdm",
  45         .flags          = HWMOD_INIT_NO_IDLE,
  46         .main_clk       = "l3_gclk",
  47         .prcm           = {
  48                 .omap4  = {
  49                         .modulemode     = MODULEMODE_SWCTRL,
  50                 },
  51         },
  52 };
  53
  54 /* l3_s */
  55 struct omap_hwmod am33xx_l3_s_hwmod = {
  56         .name           = "l3_s",
  57         .class          = &am33xx_l3_hwmod_class,
  58         .clkdm_name     = "l3s_clkdm",
  59 };
  60
  61 /* l3_instr */
  62 struct omap_hwmod am33xx_l3_instr_hwmod = {
  63         .name           = "l3_instr",
  64         .class          = &am33xx_l3_hwmod_class,
  65         .clkdm_name     = "l3_clkdm",
  66         .flags          = HWMOD_INIT_NO_IDLE,
  67         .main_clk       = "l3_gclk",
  68         .prcm           = {
  69                 .omap4  = {
  70                         .modulemode     = MODULEMODE_SWCTRL,
  71                 },
  72         },
  73 };
  74
  75 /*
  76  * 'l4' class
  77  * instance(s): l4_ls, l4_hs, l4_wkup, l4_fw
  78  */
  79 struct omap_hwmod_class am33xx_l4_hwmod_class = {
  80         .name           = "l4",
  81 };
  82
  83 /* l4_ls */
  84 struct omap_hwmod am33xx_l4_ls_hwmod = {
  85         .name           = "l4_ls",
  86         .class          = &am33xx_l4_hwmod_class,
  87         .clkdm_name     = "l4ls_clkdm",
  88         .flags          = HWMOD_INIT_NO_IDLE,
  89         .main_clk       = "l4ls_gclk",
  90         .prcm           = {
  91                 .omap4  = {
  92                         .modulemode     = MODULEMODE_SWCTRL,
  93                 },
  94         },
  95 };
  96
  97 /* l4_wkup */
  98 struct omap_hwmod am33xx_l4_wkup_hwmod = {
  99         .name           = "l4_wkup",
 100         .class          = &am33xx_l4_hwmod_class,
 101         .clkdm_name     = "l4_wkup_clkdm",
 102         .flags          = HWMOD_INIT_NO_IDLE,
 103         .prcm           = {
 104                 .omap4  = {
 105                         .modulemode     = MODULEMODE_SWCTRL,
 106                 },
 107         },
 108 };
 109
 110 /*
 111  * 'mpu' class
 112  */
 113 static struct omap_hwmod_class am33xx_mpu_hwmod_class = {
 114         .name   = "mpu",
 115 };
 116
 117 struct omap_hwmod am33xx_mpu_hwmod = {
 118         .name           = "mpu",
 119         .class          = &am33xx_mpu_hwmod_class,
 120         .clkdm_name     = "mpu_clkdm",
 121         .flags          = HWMOD_INIT_NO_IDLE,
 122         .main_clk       = "dpll_mpu_m2_ck",
 123         .prcm           = {
 124                 .omap4  = {
 125                         .modulemode     = MODULEMODE_SWCTRL,
 126                 },
 127         },
 128 };
 129
 130 /*
 131  * 'wakeup m3' class
 132  * Wakeup controller sub-system under wakeup domain
 133  */
 134 struct omap_hwmod_class am33xx_wkup_m3_hwmod_class = {
 135         .name           = "wkup_m3",
 136 };
 137
 138 /*
 139  * 'pru-icss' class
 140  * Programmable Real-Time Unit and Industrial Communication Subsystem
 141  */
 142 static struct omap_hwmod_class am33xx_pruss_hwmod_class = {
 143         .name   = "pruss",
 144 };
 145
 146 static struct omap_hwmod_rst_info am33xx_pruss_resets[] = {
 147         { .name = "pruss", .rst_shift = 1 },
 148 };
 149
 150 /* pru-icss */
 151 /* Pseudo hwmod for reset control purpose only */
 152 struct omap_hwmod am33xx_pruss_hwmod = {
 153         .name           = "pruss",
 154         .class          = &am33xx_pruss_hwmod_class,
 155         .clkdm_name     = "pruss_ocp_clkdm",
 156         .main_clk       = "pruss_ocp_gclk",
 157         .prcm           = {
 158                 .omap4  = {
 159                         .modulemode     = MODULEMODE_SWCTRL,
 160                 },
 161         },
 162         .rst_lines      = am33xx_pruss_resets,
 163         .rst_lines_cnt  = ARRAY_SIZE(am33xx_pruss_resets),
 164 };
 165
 166 /* gfx */
 167 /* Pseudo hwmod for reset control purpose only */
 168 static struct omap_hwmod_class am33xx_gfx_hwmod_class = {
 169         .name   = "gfx",
 170 };
 171
 172 static struct omap_hwmod_rst_info am33xx_gfx_resets[] = {
 173         { .name = "gfx", .rst_shift = 0, .st_shift = 0},
 174 };
 175
 176 struct omap_hwmod am33xx_gfx_hwmod = {
 177         .name           = "gfx",
 178         .class          = &am33xx_gfx_hwmod_class,
 179         .clkdm_name     = "gfx_l3_clkdm",
 180         .main_clk       = "gfx_fck_div_ck",
 181         .prcm           = {
 182                 .omap4  = {
 183                         .modulemode     = MODULEMODE_SWCTRL,
 184                 },
 185         },
 186         .rst_lines      = am33xx_gfx_resets,
 187         .rst_lines_cnt  = ARRAY_SIZE(am33xx_gfx_resets),
 188 };
 189
 190 /*
 191  * 'prcm' class
 192  * power and reset manager (whole prcm infrastructure)
 193  */
 194 static struct omap_hwmod_class am33xx_prcm_hwmod_class = {
 195         .name   = "prcm",
 196 };
 197
 198 /* prcm */
 199 struct omap_hwmod am33xx_prcm_hwmod = {
 200         .name           = "prcm",
 201         .class          = &am33xx_prcm_hwmod_class,
 202         .clkdm_name     = "l4_wkup_clkdm",
 203 };
 204
 205 /*
 206  * 'emif' class
 207  * instance(s): emif
 208  */
 209 static struct omap_hwmod_class_sysconfig am33xx_emif_sysc = {
 210         .rev_offs       = 0x0000,
 211 };
 212
 213 struct omap_hwmod_class am33xx_emif_hwmod_class = {
 214         .name           = "emif",
 215         .sysc           = &am33xx_emif_sysc,
 216 };
 217
 218 /*
 219  * 'aes0' class
 220  */
 221 static struct omap_hwmod_class_sysconfig am33xx_aes0_sysc = {
 222         .rev_offs       = 0x80,
 223         .sysc_offs      = 0x84,
 224         .syss_offs      = 0x88,
 225         .sysc_flags     = SYSS_HAS_RESET_STATUS,
 226 };
 227
 228 static struct omap_hwmod_class am33xx_aes0_hwmod_class = {
 229         .name           = "aes0",
 230         .sysc           = &am33xx_aes0_sysc,
 231 };
 232
 233 struct omap_hwmod am33xx_aes0_hwmod = {
 234         .name           = "aes",
 235         .class          = &am33xx_aes0_hwmod_class,
 236         .clkdm_name     = "l3_clkdm",
 237         .main_clk       = "aes0_fck",
 238         .prcm           = {
 239                 .omap4  = {
 240                         .modulemode     = MODULEMODE_SWCTRL,
 241                 },
 242         },
 243 };
 244
 245 /* sha0 HIB2 (the 'P' (public) device) */
 246 static struct omap_hwmod_class_sysconfig am33xx_sha0_sysc = {
 247         .rev_offs       = 0x100,
 248         .sysc_offs      = 0x110,
 249         .syss_offs      = 0x114,
 250         .sysc_flags     = SYSS_HAS_RESET_STATUS,
 251 };
 252
 253 static struct omap_hwmod_class am33xx_sha0_hwmod_class = {
 254         .name           = "sha0",
 255         .sysc           = &am33xx_sha0_sysc,
 256 };
 257
 258 struct omap_hwmod am33xx_sha0_hwmod = {
 259         .name           = "sham",
 260         .class          = &am33xx_sha0_hwmod_class,
 261         .clkdm_name     = "l3_clkdm",
 262         .main_clk       = "l3_gclk",
 263         .prcm           = {
 264                 .omap4  = {
 265                         .modulemode     = MODULEMODE_SWCTRL,
 266                 },
 267         },
 268 };
 269
 270 /* ocmcram */
 271 static struct omap_hwmod_class am33xx_ocmcram_hwmod_class = {
 272         .name = "ocmcram",
 273 };
 274
 275 struct omap_hwmod am33xx_ocmcram_hwmod = {
 276         .name           = "ocmcram",
 277         .class          = &am33xx_ocmcram_hwmod_class,
 278         .clkdm_name     = "l3_clkdm",
 279         .flags          = HWMOD_INIT_NO_IDLE,
 280         .main_clk       = "l3_gclk",
 281         .prcm           = {
 282                 .omap4  = {
 283                         .modulemode     = MODULEMODE_SWCTRL,
 284                 },
 285         },
 286 };
 287
 288 /* 'smartreflex' class */
 289 static struct omap_hwmod_class am33xx_smartreflex_hwmod_class = {
 290         .name           = "smartreflex",
 291 };
 292
 293 /* smartreflex0 */
 294 struct omap_hwmod am33xx_smartreflex0_hwmod = {
 295         .name           = "smartreflex0",
 296         .class          = &am33xx_smartreflex_hwmod_class,
 297         .clkdm_name     = "l4_wkup_clkdm",
 298         .main_clk       = "smartreflex0_fck",
 299         .prcm           = {
 300                 .omap4  = {
 301                         .modulemode     = MODULEMODE_SWCTRL,
 302                 },
 303         },
 304 };
 305
 306 /* smartreflex1 */
 307 struct omap_hwmod am33xx_smartreflex1_hwmod = {
 308         .name           = "smartreflex1",
 309         .class          = &am33xx_smartreflex_hwmod_class,
 310         .clkdm_name     = "l4_wkup_clkdm",
 311         .main_clk       = "smartreflex1_fck",
 312         .prcm           = {
 313                 .omap4  = {
 314                         .modulemode     = MODULEMODE_SWCTRL,
 315                 },
 316         },
 317 };
 318
 319 /*
 320  * 'control' module class
 321  */
 322 struct omap_hwmod_class am33xx_control_hwmod_class = {
 323         .name           = "control",
 324 };
 325
 326 /*
 327  * 'cpgmac' class
 328  * cpsw/cpgmac sub system
 329  */
 330 static struct omap_hwmod_class_sysconfig am33xx_cpgmac_sysc = {
 331         .rev_offs       = 0x0,
 332         .sysc_offs      = 0x8,
 333         .syss_offs      = 0x4,
 334         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
 335                            SYSS_HAS_RESET_STATUS),
 336         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | MSTANDBY_FORCE |
 337                            MSTANDBY_NO),
 338         .sysc_fields    = &omap_hwmod_sysc_type3,
 339 };
 340
 341 static struct omap_hwmod_class am33xx_cpgmac0_hwmod_class = {
 342         .name           = "cpgmac0",
 343         .sysc           = &am33xx_cpgmac_sysc,
 344 };
 345
 346 struct omap_hwmod am33xx_cpgmac0_hwmod = {
 347         .name           = "cpgmac0",
 348         .class          = &am33xx_cpgmac0_hwmod_class,
 349         .clkdm_name     = "cpsw_125mhz_clkdm",
 350         .flags          = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
 351         .main_clk       = "cpsw_125mhz_gclk",
 352         .mpu_rt_idx     = 1,
 353         .prcm           = {
 354                 .omap4  = {
 355                         .modulemode     = MODULEMODE_SWCTRL,
 356                 },
 357         },
 358 };
 359
 360 /*
 361  * mdio class
 362  */
 363 static struct omap_hwmod_class am33xx_mdio_hwmod_class = {
 364         .name           = "davinci_mdio",
 365 };
 366
 367 struct omap_hwmod am33xx_mdio_hwmod = {
 368         .name           = "davinci_mdio",
 369         .class          = &am33xx_mdio_hwmod_class,
 370         .clkdm_name     = "cpsw_125mhz_clkdm",
 371         .main_clk       = "cpsw_125mhz_gclk",
 372 };
 373
 374 /*
 375  * dcan class
 376  */
 377 static struct omap_hwmod_class am33xx_dcan_hwmod_class = {
 378         .name = "d_can",
 379 };
 380
 381 /* dcan0 */
 382 struct omap_hwmod am33xx_dcan0_hwmod = {
 383         .name           = "d_can0",
 384         .class          = &am33xx_dcan_hwmod_class,
 385         .clkdm_name     = "l4ls_clkdm",
 386         .main_clk       = "dcan0_fck",
 387         .prcm           = {
 388                 .omap4  = {
 389                         .modulemode     = MODULEMODE_SWCTRL,
 390                 },
 391         },
 392 };
 393
 394 /* dcan1 */
 395 struct omap_hwmod am33xx_dcan1_hwmod = {
 396         .name           = "d_can1",
 397         .class          = &am33xx_dcan_hwmod_class,
 398         .clkdm_name     = "l4ls_clkdm",
 399         .main_clk       = "dcan1_fck",
 400         .prcm           = {
 401                 .omap4  = {
 402                         .modulemode     = MODULEMODE_SWCTRL,
 403                 },
 404         },
 405 };
 406
 407 /* elm */
 408 static struct omap_hwmod_class_sysconfig am33xx_elm_sysc = {
 409         .rev_offs       = 0x0000,
 410         .sysc_offs      = 0x0010,
 411         .syss_offs      = 0x0014,
 412         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
 413                         SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
 414                         SYSS_HAS_RESET_STATUS),
 415         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 416         .sysc_fields    = &omap_hwmod_sysc_type1,
 417 };
 418
 419 static struct omap_hwmod_class am33xx_elm_hwmod_class = {
 420         .name           = "elm",
 421         .sysc           = &am33xx_elm_sysc,
 422 };
 423
 424 struct omap_hwmod am33xx_elm_hwmod = {
 425         .name           = "elm",
 426         .class          = &am33xx_elm_hwmod_class,
 427         .clkdm_name     = "l4ls_clkdm",
 428         .main_clk       = "l4ls_gclk",
 429         .prcm           = {
 430                 .omap4  = {
 431                         .modulemode     = MODULEMODE_SWCTRL,
 432                 },
 433         },
 434 };
 435
 436 /* pwmss  */
 437 static struct omap_hwmod_class_sysconfig am33xx_epwmss_sysc = {
 438         .rev_offs       = 0x0,
 439         .sysc_offs      = 0x4,
 440         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE),
 441         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 442                         SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
 443                         MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
 444         .sysc_fields    = &omap_hwmod_sysc_type2,
 445 };
 446
 447 struct omap_hwmod_class am33xx_epwmss_hwmod_class = {
 448         .name           = "epwmss",
 449         .sysc           = &am33xx_epwmss_sysc,
 450 };
 451
 452 static struct omap_hwmod_class am33xx_ecap_hwmod_class = {
 453         .name           = "ecap",
 454 };
 455
 456 static struct omap_hwmod_class am33xx_eqep_hwmod_class = {
 457         .name           = "eqep",
 458 };
 459
 460 struct omap_hwmod_class am33xx_ehrpwm_hwmod_class = {
 461         .name           = "ehrpwm",
 462 };
 463
 464 /* epwmss0 */
 465 struct omap_hwmod am33xx_epwmss0_hwmod = {
 466         .name           = "epwmss0",
 467         .class          = &am33xx_epwmss_hwmod_class,
 468         .clkdm_name     = "l4ls_clkdm",
 469         .main_clk       = "l4ls_gclk",
 470         .prcm           = {
 471                 .omap4  = {
 472                         .modulemode     = MODULEMODE_SWCTRL,
 473                 },
 474         },
 475 };
 476
 477 /* ecap0 */
 478 struct omap_hwmod am33xx_ecap0_hwmod = {
 479         .name           = "ecap0",
 480         .class          = &am33xx_ecap_hwmod_class,
 481         .clkdm_name     = "l4ls_clkdm",
 482         .main_clk       = "l4ls_gclk",
 483 };
 484
 485 /* eqep0 */
 486 struct omap_hwmod am33xx_eqep0_hwmod = {
 487         .name           = "eqep0",
 488         .class          = &am33xx_eqep_hwmod_class,
 489         .clkdm_name     = "l4ls_clkdm",
 490         .main_clk       = "l4ls_gclk",
 491 };
 492
 493 /* ehrpwm0 */
 494 struct omap_hwmod am33xx_ehrpwm0_hwmod = {
 495         .name           = "ehrpwm0",
 496         .class          = &am33xx_ehrpwm_hwmod_class,
 497         .clkdm_name     = "l4ls_clkdm",
 498         .main_clk       = "l4ls_gclk",
 499 };
 500
 501 /* epwmss1 */
 502 struct omap_hwmod am33xx_epwmss1_hwmod = {
 503         .name           = "epwmss1",
 504         .class          = &am33xx_epwmss_hwmod_class,
 505         .clkdm_name     = "l4ls_clkdm",
 506         .main_clk       = "l4ls_gclk",
 507         .prcm           = {
 508                 .omap4  = {
 509                         .modulemode     = MODULEMODE_SWCTRL,
 510                 },
 511         },
 512 };
 513
 514 /* ecap1 */
 515 struct omap_hwmod am33xx_ecap1_hwmod = {
 516         .name           = "ecap1",
 517         .class          = &am33xx_ecap_hwmod_class,
 518         .clkdm_name     = "l4ls_clkdm",
 519         .main_clk       = "l4ls_gclk",
 520 };
 521
 522 /* eqep1 */
 523 struct omap_hwmod am33xx_eqep1_hwmod = {
 524         .name           = "eqep1",
 525         .class          = &am33xx_eqep_hwmod_class,
 526         .clkdm_name     = "l4ls_clkdm",
 527         .main_clk       = "l4ls_gclk",
 528 };
 529
 530 /* ehrpwm1 */
 531 struct omap_hwmod am33xx_ehrpwm1_hwmod = {
 532         .name           = "ehrpwm1",
 533         .class          = &am33xx_ehrpwm_hwmod_class,
 534         .clkdm_name     = "l4ls_clkdm",
 535         .main_clk       = "l4ls_gclk",
 536 };
 537
 538 /* epwmss2 */
 539 struct omap_hwmod am33xx_epwmss2_hwmod = {
 540         .name           = "epwmss2",
 541         .class          = &am33xx_epwmss_hwmod_class,
 542         .clkdm_name     = "l4ls_clkdm",
 543         .main_clk       = "l4ls_gclk",
 544         .prcm           = {
 545                 .omap4  = {
 546                         .modulemode     = MODULEMODE_SWCTRL,
 547                 },
 548         },
 549 };
 550
 551 /* ecap2 */
 552 struct omap_hwmod am33xx_ecap2_hwmod = {
 553         .name           = "ecap2",
 554         .class          = &am33xx_ecap_hwmod_class,
 555         .clkdm_name     = "l4ls_clkdm",
 556         .main_clk       = "l4ls_gclk",
 557 };
 558
 559 /* eqep2 */
 560 struct omap_hwmod am33xx_eqep2_hwmod = {
 561         .name           = "eqep2",
 562         .class          = &am33xx_eqep_hwmod_class,
 563         .clkdm_name     = "l4ls_clkdm",
 564         .main_clk       = "l4ls_gclk",
 565 };
 566
 567 /* ehrpwm2 */
 568 struct omap_hwmod am33xx_ehrpwm2_hwmod = {
 569         .name           = "ehrpwm2",
 570         .class          = &am33xx_ehrpwm_hwmod_class,
 571         .clkdm_name     = "l4ls_clkdm",
 572         .main_clk       = "l4ls_gclk",
 573 };
 574
 575 /*
 576  * 'gpio' class: for gpio 0,1,2,3
 577  */
 578 static struct omap_hwmod_class_sysconfig am33xx_gpio_sysc = {
 579         .rev_offs       = 0x0000,
 580         .sysc_offs      = 0x0010,
 581         .syss_offs      = 0x0114,
 582         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
 583                           SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
 584                           SYSS_HAS_RESET_STATUS),
 585         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 586                           SIDLE_SMART_WKUP),
 587         .sysc_fields    = &omap_hwmod_sysc_type1,
 588 };
 589
 590 struct omap_hwmod_class am33xx_gpio_hwmod_class = {
 591         .name           = "gpio",
 592         .sysc           = &am33xx_gpio_sysc,
 593         .rev            = 2,
 594 };
 595
 596 struct omap_gpio_dev_attr gpio_dev_attr = {
 597         .bank_width     = 32,
 598         .dbck_flag      = true,
 599 };
 600
 601 /* gpio1 */
 602 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
 603         { .role = "dbclk", .clk = "gpio1_dbclk" },
 604 };
 605
 606 struct omap_hwmod am33xx_gpio1_hwmod = {
 607         .name           = "gpio2",
 608         .class          = &am33xx_gpio_hwmod_class,
 609         .clkdm_name     = "l4ls_clkdm",
 610         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 611         .main_clk       = "l4ls_gclk",
 612         .prcm           = {
 613                 .omap4  = {
 614                         .modulemode     = MODULEMODE_SWCTRL,
 615                 },
 616         },
 617         .opt_clks       = gpio1_opt_clks,
 618         .opt_clks_cnt   = ARRAY_SIZE(gpio1_opt_clks),
 619         .dev_attr       = &gpio_dev_attr,
 620 };
 621
 622 /* gpio2 */
 623 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
 624         { .role = "dbclk", .clk = "gpio2_dbclk" },
 625 };
 626
 627 struct omap_hwmod am33xx_gpio2_hwmod = {
 628         .name           = "gpio3",
 629         .class          = &am33xx_gpio_hwmod_class,
 630         .clkdm_name     = "l4ls_clkdm",
 631         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 632         .main_clk       = "l4ls_gclk",
 633         .prcm           = {
 634                 .omap4  = {
 635                         .modulemode     = MODULEMODE_SWCTRL,
 636                 },
 637         },
 638         .opt_clks       = gpio2_opt_clks,
 639         .opt_clks_cnt   = ARRAY_SIZE(gpio2_opt_clks),
 640         .dev_attr       = &gpio_dev_attr,
 641 };
 642
 643 /* gpio3 */
 644 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
 645         { .role = "dbclk", .clk = "gpio3_dbclk" },
 646 };
 647
 648 struct omap_hwmod am33xx_gpio3_hwmod = {
 649         .name           = "gpio4",
 650         .class          = &am33xx_gpio_hwmod_class,
 651         .clkdm_name     = "l4ls_clkdm",
 652         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 653         .main_clk       = "l4ls_gclk",
 654         .prcm           = {
 655                 .omap4  = {
 656                         .modulemode     = MODULEMODE_SWCTRL,
 657                 },
 658         },
 659         .opt_clks       = gpio3_opt_clks,
 660         .opt_clks_cnt   = ARRAY_SIZE(gpio3_opt_clks),
 661         .dev_attr       = &gpio_dev_attr,
 662 };
 663
 664 /* gpmc */
 665 static struct omap_hwmod_class_sysconfig gpmc_sysc = {
 666         .rev_offs       = 0x0,
 667         .sysc_offs      = 0x10,
 668         .syss_offs      = 0x14,
 669         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
 670                         SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
 671         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 672         .sysc_fields    = &omap_hwmod_sysc_type1,
 673 };
 674
 675 static struct omap_hwmod_class am33xx_gpmc_hwmod_class = {
 676         .name           = "gpmc",
 677         .sysc           = &gpmc_sysc,
 678 };
 679
 680 struct omap_hwmod am33xx_gpmc_hwmod = {
 681         .name           = "gpmc",
 682         .class          = &am33xx_gpmc_hwmod_class,
 683         .clkdm_name     = "l3s_clkdm",
 684         /* Skip reset for CONFIG_OMAP_GPMC_DEBUG for bootloader timings */
 685         .flags          = DEBUG_OMAP_GPMC_HWMOD_FLAGS,
 686         .main_clk       = "l3s_gclk",
 687         .prcm           = {
 688                 .omap4  = {
 689                         .modulemode     = MODULEMODE_SWCTRL,
 690                 },
 691         },
 692 };
 693
 694 /* 'i2c' class */
 695 static struct omap_hwmod_class_sysconfig am33xx_i2c_sysc = {
 696         .sysc_offs      = 0x0010,
 697         .syss_offs      = 0x0090,
 698         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 699                           SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
 700                           SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
 701         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 702                           SIDLE_SMART_WKUP),
 703         .sysc_fields    = &omap_hwmod_sysc_type1,
 704 };
 705
 706 static struct omap_hwmod_class i2c_class = {
 707         .name           = "i2c",
 708         .sysc           = &am33xx_i2c_sysc,
 709         .rev            = OMAP_I2C_IP_VERSION_2,
 710         .reset          = &omap_i2c_reset,
 711 };
 712
 713 static struct omap_i2c_dev_attr i2c_dev_attr = {
 714         .flags = OMAP_I2C_FLAG_BUS_SHIFT_NONE,
 715 };
 716
 717 /* i2c1 */
 718 struct omap_hwmod am33xx_i2c1_hwmod = {
 719         .name           = "i2c1",
 720         .class          = &i2c_class,
 721         .clkdm_name     = "l4_wkup_clkdm",
 722         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
 723         .main_clk       = "dpll_per_m2_div4_wkupdm_ck",
 724         .prcm           = {
 725                 .omap4  = {
 726                         .modulemode     = MODULEMODE_SWCTRL,
 727                 },
 728         },
 729         .dev_attr       = &i2c_dev_attr,
 730 };
 731
 732 /* i2c1 */
 733 struct omap_hwmod am33xx_i2c2_hwmod = {
 734         .name           = "i2c2",
 735         .class          = &i2c_class,
 736         .clkdm_name     = "l4ls_clkdm",
 737         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
 738         .main_clk       = "dpll_per_m2_div4_ck",
 739         .prcm           = {
 740                 .omap4 = {
 741                         .modulemode     = MODULEMODE_SWCTRL,
 742                 },
 743         },
 744         .dev_attr       = &i2c_dev_attr,
 745 };
 746
 747 /* i2c3 */
 748 struct omap_hwmod am33xx_i2c3_hwmod = {
 749         .name           = "i2c3",
 750         .class          = &i2c_class,
 751         .clkdm_name     = "l4ls_clkdm",
 752         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
 753         .main_clk       = "dpll_per_m2_div4_ck",
 754         .prcm           = {
 755                 .omap4  = {
 756                         .modulemode     = MODULEMODE_SWCTRL,
 757                 },
 758         },
 759         .dev_attr       = &i2c_dev_attr,
 760 };
 761
 762 /*
 763  * 'mailbox' class
 764  * mailbox module allowing communication between the on-chip processors using a
 765  * queued mailbox-interrupt mechanism.
 766  */
 767 static struct omap_hwmod_class_sysconfig am33xx_mailbox_sysc = {
 768         .rev_offs       = 0x0000,
 769         .sysc_offs      = 0x0010,
 770         .sysc_flags     = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
 771                           SYSC_HAS_SOFTRESET),
 772         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 773         .sysc_fields    = &omap_hwmod_sysc_type2,
 774 };
 775
 776 static struct omap_hwmod_class am33xx_mailbox_hwmod_class = {
 777         .name   = "mailbox",
 778         .sysc   = &am33xx_mailbox_sysc,
 779 };
 780
 781 struct omap_hwmod am33xx_mailbox_hwmod = {
 782         .name           = "mailbox",
 783         .class          = &am33xx_mailbox_hwmod_class,
 784         .clkdm_name     = "l4ls_clkdm",
 785         .main_clk       = "l4ls_gclk",
 786         .prcm = {
 787                 .omap4 = {
 788                         .modulemode     = MODULEMODE_SWCTRL,
 789                 },
 790         },
 791 };
 792
 793 /*
 794  * 'mcasp' class
 795  */
 796 static struct omap_hwmod_class_sysconfig am33xx_mcasp_sysc = {
 797         .rev_offs       = 0x0,
 798         .sysc_offs      = 0x4,
 799         .sysc_flags     = SYSC_HAS_SIDLEMODE,
 800         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 801         .sysc_fields    = &omap_hwmod_sysc_type3,
 802 };
 803
 804 static struct omap_hwmod_class am33xx_mcasp_hwmod_class = {
 805         .name           = "mcasp",
 806         .sysc           = &am33xx_mcasp_sysc,
 807 };
 808
 809 /* mcasp0 */
 810 struct omap_hwmod am33xx_mcasp0_hwmod = {
 811         .name           = "mcasp0",
 812         .class          = &am33xx_mcasp_hwmod_class,
 813         .clkdm_name     = "l3s_clkdm",
 814         .main_clk       = "mcasp0_fck",
 815         .prcm           = {
 816                 .omap4  = {
 817                         .modulemode     = MODULEMODE_SWCTRL,
 818                 },
 819         },
 820 };
 821
 822 /* mcasp1 */
 823 struct omap_hwmod am33xx_mcasp1_hwmod = {
 824         .name           = "mcasp1",
 825         .class          = &am33xx_mcasp_hwmod_class,
 826         .clkdm_name     = "l3s_clkdm",
 827         .main_clk       = "mcasp1_fck",
 828         .prcm           = {
 829                 .omap4  = {
 830                         .modulemode     = MODULEMODE_SWCTRL,
 831                 },
 832         },
 833 };
 834
 835 /* 'mmc' class */
 836 static struct omap_hwmod_class_sysconfig am33xx_mmc_sysc = {
 837         .rev_offs       = 0x1fc,
 838         .sysc_offs      = 0x10,
 839         .syss_offs      = 0x14,
 840         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
 841                           SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
 842                           SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
 843         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 844         .sysc_fields    = &omap_hwmod_sysc_type1,
 845 };
 846
 847 static struct omap_hwmod_class am33xx_mmc_hwmod_class = {
 848         .name           = "mmc",
 849         .sysc           = &am33xx_mmc_sysc,
 850 };
 851
 852 /* mmc0 */
 853 static struct omap_hsmmc_dev_attr am33xx_mmc0_dev_attr = {
 854         .flags          = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
 855 };
 856
 857 struct omap_hwmod am33xx_mmc0_hwmod = {
 858         .name           = "mmc1",
 859         .class          = &am33xx_mmc_hwmod_class,
 860         .clkdm_name     = "l4ls_clkdm",
 861         .main_clk       = "mmc_clk",
 862         .prcm           = {
 863                 .omap4  = {
 864                         .modulemode     = MODULEMODE_SWCTRL,
 865                 },
 866         },
 867         .dev_attr       = &am33xx_mmc0_dev_attr,
 868 };
 869
 870 /* mmc1 */
 871 static struct omap_hsmmc_dev_attr am33xx_mmc1_dev_attr = {
 872         .flags          = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
 873 };
 874
 875 struct omap_hwmod am33xx_mmc1_hwmod = {
 876         .name           = "mmc2",
 877         .class          = &am33xx_mmc_hwmod_class,
 878         .clkdm_name     = "l4ls_clkdm",
 879         .main_clk       = "mmc_clk",
 880         .prcm           = {
 881                 .omap4  = {
 882                         .modulemode     = MODULEMODE_SWCTRL,
 883                 },
 884         },
 885         .dev_attr       = &am33xx_mmc1_dev_attr,
 886 };
 887
 888 /* mmc2 */
 889 static struct omap_hsmmc_dev_attr am33xx_mmc2_dev_attr = {
 890         .flags          = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
 891 };
 892 struct omap_hwmod am33xx_mmc2_hwmod = {
 893         .name           = "mmc3",
 894         .class          = &am33xx_mmc_hwmod_class,
 895         .clkdm_name     = "l3s_clkdm",
 896         .main_clk       = "mmc_clk",
 897         .prcm           = {
 898                 .omap4  = {
 899                         .modulemode     = MODULEMODE_SWCTRL,
 900                 },
 901         },
 902         .dev_attr       = &am33xx_mmc2_dev_attr,
 903 };
 904
 905 /*
 906  * 'rtc' class
 907  * rtc subsystem
 908  */
 909 static struct omap_hwmod_class_sysconfig am33xx_rtc_sysc = {
 910         .rev_offs       = 0x0074,
 911         .sysc_offs      = 0x0078,
 912         .sysc_flags     = SYSC_HAS_SIDLEMODE,
 913         .idlemodes      = (SIDLE_FORCE | SIDLE_NO |
 914                           SIDLE_SMART | SIDLE_SMART_WKUP),
 915         .sysc_fields    = &omap_hwmod_sysc_type3,
 916 };
 917
 918 static struct omap_hwmod_class am33xx_rtc_hwmod_class = {
 919         .name           = "rtc",
 920         .sysc           = &am33xx_rtc_sysc,
 921 };
 922
 923 struct omap_hwmod am33xx_rtc_hwmod = {
 924         .name           = "rtc",
 925         .class          = &am33xx_rtc_hwmod_class,
 926         .clkdm_name     = "l4_rtc_clkdm",
 927         .main_clk       = "clk_32768_ck",
 928         .prcm           = {
 929                 .omap4  = {
 930                         .modulemode     = MODULEMODE_SWCTRL,
 931                 },
 932         },
 933 };
 934
 935 /* 'spi' class */
 936 static struct omap_hwmod_class_sysconfig am33xx_mcspi_sysc = {
 937         .rev_offs       = 0x0000,
 938         .sysc_offs      = 0x0110,
 939         .syss_offs      = 0x0114,
 940         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
 941                           SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
 942                           SYSS_HAS_RESET_STATUS),
 943         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 944         .sysc_fields    = &omap_hwmod_sysc_type1,
 945 };
 946
 947 struct omap_hwmod_class am33xx_spi_hwmod_class = {
 948         .name           = "mcspi",
 949         .sysc           = &am33xx_mcspi_sysc,
 950         .rev            = OMAP4_MCSPI_REV,
 951 };
 952
 953 /* spi0 */
 954 struct omap2_mcspi_dev_attr mcspi_attrib = {
 955         .num_chipselect = 2,
 956 };
 957 struct omap_hwmod am33xx_spi0_hwmod = {
 958         .name           = "spi0",
 959         .class          = &am33xx_spi_hwmod_class,
 960         .clkdm_name     = "l4ls_clkdm",
 961         .main_clk       = "dpll_per_m2_div4_ck",
 962         .prcm           = {
 963                 .omap4  = {
 964                         .modulemode     = MODULEMODE_SWCTRL,
 965                 },
 966         },
 967         .dev_attr       = &mcspi_attrib,
 968 };
 969
 970 /* spi1 */
 971 struct omap_hwmod am33xx_spi1_hwmod = {
 972         .name           = "spi1",
 973         .class          = &am33xx_spi_hwmod_class,
 974         .clkdm_name     = "l4ls_clkdm",
 975         .main_clk       = "dpll_per_m2_div4_ck",
 976         .prcm           = {
 977                 .omap4  = {
 978                         .modulemode     = MODULEMODE_SWCTRL,
 979                 },
 980         },
 981         .dev_attr       = &mcspi_attrib,
 982 };
 983
 984 /*
 985  * 'spinlock' class
 986  * spinlock provides hardware assistance for synchronizing the
 987  * processes running on multiple processors
 988  */
 989
 990 static struct omap_hwmod_class_sysconfig am33xx_spinlock_sysc = {
 991         .rev_offs       = 0x0000,
 992         .sysc_offs      = 0x0010,
 993         .syss_offs      = 0x0014,
 994         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 995                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
 996                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
 997         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 998         .sysc_fields    = &omap_hwmod_sysc_type1,
 999 };
1000
1001 static struct omap_hwmod_class am33xx_spinlock_hwmod_class = {
1002         .name           = "spinlock",
1003         .sysc           = &am33xx_spinlock_sysc,
1004 };
1005
1006 struct omap_hwmod am33xx_spinlock_hwmod = {
1007         .name           = "spinlock",
1008         .class          = &am33xx_spinlock_hwmod_class,
1009         .clkdm_name     = "l4ls_clkdm",
1010         .main_clk       = "l4ls_gclk",
1011         .prcm           = {
1012                 .omap4  = {
1013                         .modulemode     = MODULEMODE_SWCTRL,
1014                 },
1015         },
1016 };
1017
1018 /* 'timer 2-7' class */
1019 static struct omap_hwmod_class_sysconfig am33xx_timer_sysc = {
1020         .rev_offs       = 0x0000,
1021         .sysc_offs      = 0x0010,
1022         .syss_offs      = 0x0014,
1023         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1024         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1025                           SIDLE_SMART_WKUP),
1026         .sysc_fields    = &omap_hwmod_sysc_type2,
1027 };
1028
1029 struct omap_hwmod_class am33xx_timer_hwmod_class = {
1030         .name           = "timer",
1031         .sysc           = &am33xx_timer_sysc,
1032 };
1033
1034 /* timer1 1ms */
1035 static struct omap_hwmod_class_sysconfig am33xx_timer1ms_sysc = {
1036         .rev_offs       = 0x0000,
1037         .sysc_offs      = 0x0010,
1038         .syss_offs      = 0x0014,
1039         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1040                         SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
1041                         SYSS_HAS_RESET_STATUS),
1042         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1043         .sysc_fields    = &omap_hwmod_sysc_type1,
1044 };
1045
1046 static struct omap_hwmod_class am33xx_timer1ms_hwmod_class = {
1047         .name           = "timer",
1048         .sysc           = &am33xx_timer1ms_sysc,
1049 };
1050
1051 struct omap_hwmod am33xx_timer1_hwmod = {
1052         .name           = "timer1",
1053         .class          = &am33xx_timer1ms_hwmod_class,
1054         .clkdm_name     = "l4_wkup_clkdm",
1055         .main_clk       = "timer1_fck",
1056         .prcm           = {
1057                 .omap4  = {
1058                         .modulemode     = MODULEMODE_SWCTRL,
1059                 },
1060         },
1061 };
1062
1063 struct omap_hwmod am33xx_timer2_hwmod = {
1064         .name           = "timer2",
1065         .class          = &am33xx_timer_hwmod_class,
1066         .clkdm_name     = "l4ls_clkdm",
1067         .main_clk       = "timer2_fck",
1068         .prcm           = {
1069                 .omap4  = {
1070                         .modulemode     = MODULEMODE_SWCTRL,
1071                 },
1072         },
1073 };
1074
1075 struct omap_hwmod am33xx_timer3_hwmod = {
1076         .name           = "timer3",
1077         .class          = &am33xx_timer_hwmod_class,
1078         .clkdm_name     = "l4ls_clkdm",
1079         .main_clk       = "timer3_fck",
1080         .prcm           = {
1081                 .omap4  = {
1082                         .modulemode     = MODULEMODE_SWCTRL,
1083                 },
1084         },
1085 };
1086
1087 struct omap_hwmod am33xx_timer4_hwmod = {
1088         .name           = "timer4",
1089         .class          = &am33xx_timer_hwmod_class,
1090         .clkdm_name     = "l4ls_clkdm",
1091         .main_clk       = "timer4_fck",
1092         .prcm           = {
1093                 .omap4  = {
1094                         .modulemode     = MODULEMODE_SWCTRL,
1095                 },
1096         },
1097 };
1098
1099 struct omap_hwmod am33xx_timer5_hwmod = {
1100         .name           = "timer5",
1101         .class          = &am33xx_timer_hwmod_class,
1102         .clkdm_name     = "l4ls_clkdm",
1103         .main_clk       = "timer5_fck",
1104         .prcm           = {
1105                 .omap4  = {
1106                         .modulemode     = MODULEMODE_SWCTRL,
1107                 },
1108         },
1109 };
1110
1111 struct omap_hwmod am33xx_timer6_hwmod = {
1112         .name           = "timer6",
1113         .class          = &am33xx_timer_hwmod_class,
1114         .clkdm_name     = "l4ls_clkdm",
1115         .main_clk       = "timer6_fck",
1116         .prcm           = {
1117                 .omap4  = {
1118                         .modulemode     = MODULEMODE_SWCTRL,
1119                 },
1120         },
1121 };
1122
1123 struct omap_hwmod am33xx_timer7_hwmod = {
1124         .name           = "timer7",
1125         .class          = &am33xx_timer_hwmod_class,
1126         .clkdm_name     = "l4ls_clkdm",
1127         .main_clk       = "timer7_fck",
1128         .prcm           = {
1129                 .omap4  = {
1130                         .modulemode     = MODULEMODE_SWCTRL,
1131                 },
1132         },
1133 };
1134
1135 /* tpcc */
1136 static struct omap_hwmod_class am33xx_tpcc_hwmod_class = {
1137         .name           = "tpcc",
1138 };
1139
1140 struct omap_hwmod am33xx_tpcc_hwmod = {
1141         .name           = "tpcc",
1142         .class          = &am33xx_tpcc_hwmod_class,
1143         .clkdm_name     = "l3_clkdm",
1144         .main_clk       = "l3_gclk",
1145         .prcm           = {
1146                 .omap4  = {
1147                         .modulemode     = MODULEMODE_SWCTRL,
1148                 },
1149         },
1150 };
1151
1152 static struct omap_hwmod_class_sysconfig am33xx_tptc_sysc = {
1153         .rev_offs       = 0x0,
1154         .sysc_offs      = 0x10,
1155         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1156                           SYSC_HAS_MIDLEMODE),
1157         .idlemodes      = (SIDLE_FORCE | SIDLE_SMART | MSTANDBY_FORCE),
1158         .sysc_fields    = &omap_hwmod_sysc_type2,
1159 };
1160
1161 /* 'tptc' class */
1162 static struct omap_hwmod_class am33xx_tptc_hwmod_class = {
1163         .name           = "tptc",
1164         .sysc           = &am33xx_tptc_sysc,
1165 };
1166
1167 /* tptc0 */
1168 struct omap_hwmod am33xx_tptc0_hwmod = {
1169         .name           = "tptc0",
1170         .class          = &am33xx_tptc_hwmod_class,
1171         .clkdm_name     = "l3_clkdm",
1172         .flags          = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
1173         .main_clk       = "l3_gclk",
1174         .prcm           = {
1175                 .omap4  = {
1176                         .modulemode     = MODULEMODE_SWCTRL,
1177                 },
1178         },
1179 };
1180
1181 /* tptc1 */
1182 struct omap_hwmod am33xx_tptc1_hwmod = {
1183         .name           = "tptc1",
1184         .class          = &am33xx_tptc_hwmod_class,
1185         .clkdm_name     = "l3_clkdm",
1186         .flags          = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
1187         .main_clk       = "l3_gclk",
1188         .prcm           = {
1189                 .omap4  = {
1190                         .modulemode     = MODULEMODE_SWCTRL,
1191                 },
1192         },
1193 };
1194
1195 /* tptc2 */
1196 struct omap_hwmod am33xx_tptc2_hwmod = {
1197         .name           = "tptc2",
1198         .class          = &am33xx_tptc_hwmod_class,
1199         .clkdm_name     = "l3_clkdm",
1200         .flags          = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
1201         .main_clk       = "l3_gclk",
1202         .prcm           = {
1203                 .omap4  = {
1204                         .modulemode     = MODULEMODE_SWCTRL,
1205                 },
1206         },
1207 };
1208
1209 /* 'uart' class */
1210 static struct omap_hwmod_class_sysconfig uart_sysc = {
1211         .rev_offs       = 0x50,
1212         .sysc_offs      = 0x54,
1213         .syss_offs      = 0x58,
1214         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP |
1215                           SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
1216         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1217                           SIDLE_SMART_WKUP),
1218         .sysc_fields    = &omap_hwmod_sysc_type1,
1219 };
1220
1221 static struct omap_hwmod_class uart_class = {
1222         .name           = "uart",
1223         .sysc           = &uart_sysc,
1224 };
1225
1226 struct omap_hwmod am33xx_uart1_hwmod = {
1227         .name           = "uart1",
1228         .class          = &uart_class,
1229         .clkdm_name     = "l4_wkup_clkdm",
1230         .flags          = DEBUG_AM33XXUART1_FLAGS | HWMOD_SWSUP_SIDLE_ACT,
1231         .main_clk       = "dpll_per_m2_div4_wkupdm_ck",
1232         .prcm           = {
1233                 .omap4  = {
1234                         .modulemode     = MODULEMODE_SWCTRL,
1235                 },
1236         },
1237 };
1238
1239 struct omap_hwmod am33xx_uart2_hwmod = {
1240         .name           = "uart2",
1241         .class          = &uart_class,
1242         .clkdm_name     = "l4ls_clkdm",
1243         .flags          = HWMOD_SWSUP_SIDLE_ACT,
1244         .main_clk       = "dpll_per_m2_div4_ck",
1245         .prcm           = {
1246                 .omap4  = {
1247                         .modulemode     = MODULEMODE_SWCTRL,
1248                 },
1249         },
1250 };
1251
1252 /* uart3 */
1253 struct omap_hwmod am33xx_uart3_hwmod = {
1254         .name           = "uart3",
1255         .class          = &uart_class,
1256         .clkdm_name     = "l4ls_clkdm",
1257         .flags          = HWMOD_SWSUP_SIDLE_ACT,
1258         .main_clk       = "dpll_per_m2_div4_ck",
1259         .prcm           = {
1260                 .omap4  = {
1261                         .modulemode     = MODULEMODE_SWCTRL,
1262                 },
1263         },
1264 };
1265
1266 struct omap_hwmod am33xx_uart4_hwmod = {
1267         .name           = "uart4",
1268         .class          = &uart_class,
1269         .clkdm_name     = "l4ls_clkdm",
1270         .flags          = HWMOD_SWSUP_SIDLE_ACT,
1271         .main_clk       = "dpll_per_m2_div4_ck",
1272         .prcm           = {
1273                 .omap4  = {
1274                         .modulemode     = MODULEMODE_SWCTRL,
1275                 },
1276         },
1277 };
1278
1279 struct omap_hwmod am33xx_uart5_hwmod = {
1280         .name           = "uart5",
1281         .class          = &uart_class,
1282         .clkdm_name     = "l4ls_clkdm",
1283         .flags          = HWMOD_SWSUP_SIDLE_ACT,
1284         .main_clk       = "dpll_per_m2_div4_ck",
1285         .prcm           = {
1286                 .omap4  = {
1287                         .modulemode     = MODULEMODE_SWCTRL,
1288                 },
1289         },
1290 };
1291
1292 struct omap_hwmod am33xx_uart6_hwmod = {
1293         .name           = "uart6",
1294         .class          = &uart_class,
1295         .clkdm_name     = "l4ls_clkdm",
1296         .flags          = HWMOD_SWSUP_SIDLE_ACT,
1297         .main_clk       = "dpll_per_m2_div4_ck",
1298         .prcm           = {
1299                 .omap4  = {
1300                         .modulemode     = MODULEMODE_SWCTRL,
1301                 },
1302         },
1303 };
1304
1305 /* 'wd_timer' class */
1306 static struct omap_hwmod_class_sysconfig wdt_sysc = {
1307         .rev_offs       = 0x0,
1308         .sysc_offs      = 0x10,
1309         .syss_offs      = 0x14,
1310         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE |
1311                         SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1312         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1313                         SIDLE_SMART_WKUP),
1314         .sysc_fields    = &omap_hwmod_sysc_type1,
1315 };
1316
1317 static struct omap_hwmod_class am33xx_wd_timer_hwmod_class = {
1318         .name           = "wd_timer",
1319         .sysc           = &wdt_sysc,
1320         .pre_shutdown   = &omap2_wd_timer_disable,
1321 };
1322
1323 /*
1324  * XXX: device.c file uses hardcoded name for watchdog timer
1325  * driver "wd_timer2, so we are also using same name as of now...
1326  */
1327 struct omap_hwmod am33xx_wd_timer1_hwmod = {
1328         .name           = "wd_timer2",
1329         .class          = &am33xx_wd_timer_hwmod_class,
1330         .clkdm_name     = "l4_wkup_clkdm",
1331         .flags          = HWMOD_SWSUP_SIDLE,
1332         .main_clk       = "wdt1_fck",
1333         .prcm           = {
1334                 .omap4  = {
1335                         .modulemode     = MODULEMODE_SWCTRL,
1336                 },
1337         },
1338 };
1339
1340 static void omap_hwmod_am33xx_clkctrl(void)
1341 {
1342         CLKCTRL(am33xx_uart2_hwmod, AM33XX_CM_PER_UART1_CLKCTRL_OFFSET);
1343         CLKCTRL(am33xx_uart3_hwmod, AM33XX_CM_PER_UART2_CLKCTRL_OFFSET);
1344         CLKCTRL(am33xx_uart4_hwmod, AM33XX_CM_PER_UART3_CLKCTRL_OFFSET);
1345         CLKCTRL(am33xx_uart5_hwmod, AM33XX_CM_PER_UART4_CLKCTRL_OFFSET);
1346         CLKCTRL(am33xx_uart6_hwmod, AM33XX_CM_PER_UART5_CLKCTRL_OFFSET);
1347         CLKCTRL(am33xx_dcan0_hwmod, AM33XX_CM_PER_DCAN0_CLKCTRL_OFFSET);
1348         CLKCTRL(am33xx_dcan1_hwmod, AM33XX_CM_PER_DCAN1_CLKCTRL_OFFSET);
1349         CLKCTRL(am33xx_elm_hwmod, AM33XX_CM_PER_ELM_CLKCTRL_OFFSET);
1350         CLKCTRL(am33xx_epwmss0_hwmod, AM33XX_CM_PER_EPWMSS0_CLKCTRL_OFFSET);
1351         CLKCTRL(am33xx_epwmss1_hwmod, AM33XX_CM_PER_EPWMSS1_CLKCTRL_OFFSET);
1352         CLKCTRL(am33xx_epwmss2_hwmod, AM33XX_CM_PER_EPWMSS2_CLKCTRL_OFFSET);
1353         CLKCTRL(am33xx_gpio1_hwmod, AM33XX_CM_PER_GPIO1_CLKCTRL_OFFSET);
1354         CLKCTRL(am33xx_gpio2_hwmod, AM33XX_CM_PER_GPIO2_CLKCTRL_OFFSET);
1355         CLKCTRL(am33xx_gpio3_hwmod, AM33XX_CM_PER_GPIO3_CLKCTRL_OFFSET);
1356         CLKCTRL(am33xx_i2c2_hwmod, AM33XX_CM_PER_I2C1_CLKCTRL_OFFSET);
1357         CLKCTRL(am33xx_i2c3_hwmod, AM33XX_CM_PER_I2C2_CLKCTRL_OFFSET);
1358         CLKCTRL(am33xx_mailbox_hwmod, AM33XX_CM_PER_MAILBOX0_CLKCTRL_OFFSET);
1359         CLKCTRL(am33xx_mcasp0_hwmod, AM33XX_CM_PER_MCASP0_CLKCTRL_OFFSET);
1360         CLKCTRL(am33xx_mcasp1_hwmod, AM33XX_CM_PER_MCASP1_CLKCTRL_OFFSET);
1361         CLKCTRL(am33xx_mmc0_hwmod, AM33XX_CM_PER_MMC0_CLKCTRL_OFFSET);
1362         CLKCTRL(am33xx_mmc1_hwmod, AM33XX_CM_PER_MMC1_CLKCTRL_OFFSET);
1363         CLKCTRL(am33xx_spi0_hwmod, AM33XX_CM_PER_SPI0_CLKCTRL_OFFSET);
1364         CLKCTRL(am33xx_spi1_hwmod, AM33XX_CM_PER_SPI1_CLKCTRL_OFFSET);
1365         CLKCTRL(am33xx_spinlock_hwmod, AM33XX_CM_PER_SPINLOCK_CLKCTRL_OFFSET);
1366         CLKCTRL(am33xx_timer2_hwmod, AM33XX_CM_PER_TIMER2_CLKCTRL_OFFSET);
1367         CLKCTRL(am33xx_timer3_hwmod, AM33XX_CM_PER_TIMER3_CLKCTRL_OFFSET);
1368         CLKCTRL(am33xx_timer4_hwmod, AM33XX_CM_PER_TIMER4_CLKCTRL_OFFSET);
1369         CLKCTRL(am33xx_timer5_hwmod, AM33XX_CM_PER_TIMER5_CLKCTRL_OFFSET);
1370         CLKCTRL(am33xx_timer6_hwmod, AM33XX_CM_PER_TIMER6_CLKCTRL_OFFSET);
1371         CLKCTRL(am33xx_timer7_hwmod, AM33XX_CM_PER_TIMER7_CLKCTRL_OFFSET);
1372         CLKCTRL(am33xx_smartreflex0_hwmod,
1373                 AM33XX_CM_WKUP_SMARTREFLEX0_CLKCTRL_OFFSET);
1374         CLKCTRL(am33xx_smartreflex1_hwmod,
1375                 AM33XX_CM_WKUP_SMARTREFLEX1_CLKCTRL_OFFSET);
1376         CLKCTRL(am33xx_uart1_hwmod, AM33XX_CM_WKUP_UART0_CLKCTRL_OFFSET);
1377         CLKCTRL(am33xx_timer1_hwmod, AM33XX_CM_WKUP_TIMER1_CLKCTRL_OFFSET);
1378         CLKCTRL(am33xx_i2c1_hwmod, AM33XX_CM_WKUP_I2C0_CLKCTRL_OFFSET);
1379         CLKCTRL(am33xx_wd_timer1_hwmod, AM33XX_CM_WKUP_WDT1_CLKCTRL_OFFSET);
1380         CLKCTRL(am33xx_rtc_hwmod, AM33XX_CM_RTC_RTC_CLKCTRL_OFFSET);
1381         CLKCTRL(am33xx_mmc2_hwmod, AM33XX_CM_PER_MMC2_CLKCTRL_OFFSET);
1382         CLKCTRL(am33xx_gpmc_hwmod, AM33XX_CM_PER_GPMC_CLKCTRL_OFFSET);
1383         CLKCTRL(am33xx_l4_ls_hwmod, AM33XX_CM_PER_L4LS_CLKCTRL_OFFSET);
1384         CLKCTRL(am33xx_l4_wkup_hwmod, AM33XX_CM_WKUP_L4WKUP_CLKCTRL_OFFSET);
1385         CLKCTRL(am33xx_l3_main_hwmod, AM33XX_CM_PER_L3_CLKCTRL_OFFSET);
1386         CLKCTRL(am33xx_tpcc_hwmod, AM33XX_CM_PER_TPCC_CLKCTRL_OFFSET);
1387         CLKCTRL(am33xx_tptc0_hwmod, AM33XX_CM_PER_TPTC0_CLKCTRL_OFFSET);
1388         CLKCTRL(am33xx_tptc1_hwmod, AM33XX_CM_PER_TPTC1_CLKCTRL_OFFSET);
1389         CLKCTRL(am33xx_tptc2_hwmod, AM33XX_CM_PER_TPTC2_CLKCTRL_OFFSET);
1390         CLKCTRL(am33xx_gfx_hwmod, AM33XX_CM_GFX_GFX_CLKCTRL_OFFSET);
1391         CLKCTRL(am33xx_cpgmac0_hwmod, AM33XX_CM_PER_CPGMAC0_CLKCTRL_OFFSET);
1392         CLKCTRL(am33xx_pruss_hwmod, AM33XX_CM_PER_PRUSS_CLKCTRL_OFFSET);
1393         CLKCTRL(am33xx_mpu_hwmod , AM33XX_CM_MPU_MPU_CLKCTRL_OFFSET);
1394         CLKCTRL(am33xx_l3_instr_hwmod , AM33XX_CM_PER_L3_INSTR_CLKCTRL_OFFSET);
1395         CLKCTRL(am33xx_ocmcram_hwmod , AM33XX_CM_PER_OCMCRAM_CLKCTRL_OFFSET);
1396         CLKCTRL(am33xx_sha0_hwmod , AM33XX_CM_PER_SHA0_CLKCTRL_OFFSET);
1397         CLKCTRL(am33xx_aes0_hwmod , AM33XX_CM_PER_AES0_CLKCTRL_OFFSET);
1398 }
1399
1400 static void omap_hwmod_am33xx_rst(void)
1401 {
1402         RSTCTRL(am33xx_pruss_hwmod, AM33XX_RM_PER_RSTCTRL_OFFSET);
1403         RSTCTRL(am33xx_gfx_hwmod, AM33XX_RM_GFX_RSTCTRL_OFFSET);
1404         RSTST(am33xx_gfx_hwmod, AM33XX_RM_GFX_RSTST_OFFSET);
1405 }
1406
1407 void omap_hwmod_am33xx_reg(void)
1408 {
1409         omap_hwmod_am33xx_clkctrl();
1410         omap_hwmod_am33xx_rst();
1411 }
1412
1413 static void omap_hwmod_am43xx_clkctrl(void)
1414 {
1415         CLKCTRL(am33xx_uart2_hwmod, AM43XX_CM_PER_UART1_CLKCTRL_OFFSET);
1416         CLKCTRL(am33xx_uart3_hwmod, AM43XX_CM_PER_UART2_CLKCTRL_OFFSET);
1417         CLKCTRL(am33xx_uart4_hwmod, AM43XX_CM_PER_UART3_CLKCTRL_OFFSET);
1418         CLKCTRL(am33xx_uart5_hwmod, AM43XX_CM_PER_UART4_CLKCTRL_OFFSET);
1419         CLKCTRL(am33xx_uart6_hwmod, AM43XX_CM_PER_UART5_CLKCTRL_OFFSET);
1420         CLKCTRL(am33xx_dcan0_hwmod, AM43XX_CM_PER_DCAN0_CLKCTRL_OFFSET);
1421         CLKCTRL(am33xx_dcan1_hwmod, AM43XX_CM_PER_DCAN1_CLKCTRL_OFFSET);
1422         CLKCTRL(am33xx_elm_hwmod, AM43XX_CM_PER_ELM_CLKCTRL_OFFSET);
1423         CLKCTRL(am33xx_epwmss0_hwmod, AM43XX_CM_PER_EPWMSS0_CLKCTRL_OFFSET);
1424         CLKCTRL(am33xx_epwmss1_hwmod, AM43XX_CM_PER_EPWMSS1_CLKCTRL_OFFSET);
1425         CLKCTRL(am33xx_epwmss2_hwmod, AM43XX_CM_PER_EPWMSS2_CLKCTRL_OFFSET);
1426         CLKCTRL(am33xx_gpio1_hwmod, AM43XX_CM_PER_GPIO1_CLKCTRL_OFFSET);
1427         CLKCTRL(am33xx_gpio2_hwmod, AM43XX_CM_PER_GPIO2_CLKCTRL_OFFSET);
1428         CLKCTRL(am33xx_gpio3_hwmod, AM43XX_CM_PER_GPIO3_CLKCTRL_OFFSET);
1429         CLKCTRL(am33xx_i2c2_hwmod, AM43XX_CM_PER_I2C1_CLKCTRL_OFFSET);
1430         CLKCTRL(am33xx_i2c3_hwmod, AM43XX_CM_PER_I2C2_CLKCTRL_OFFSET);
1431         CLKCTRL(am33xx_mailbox_hwmod, AM43XX_CM_PER_MAILBOX0_CLKCTRL_OFFSET);
1432         CLKCTRL(am33xx_mcasp0_hwmod, AM43XX_CM_PER_MCASP0_CLKCTRL_OFFSET);
1433         CLKCTRL(am33xx_mcasp1_hwmod, AM43XX_CM_PER_MCASP1_CLKCTRL_OFFSET);
1434         CLKCTRL(am33xx_mmc0_hwmod, AM43XX_CM_PER_MMC0_CLKCTRL_OFFSET);
1435         CLKCTRL(am33xx_mmc1_hwmod, AM43XX_CM_PER_MMC1_CLKCTRL_OFFSET);
1436         CLKCTRL(am33xx_spi0_hwmod, AM43XX_CM_PER_SPI0_CLKCTRL_OFFSET);
1437         CLKCTRL(am33xx_spi1_hwmod, AM43XX_CM_PER_SPI1_CLKCTRL_OFFSET);
1438         CLKCTRL(am33xx_spinlock_hwmod, AM43XX_CM_PER_SPINLOCK_CLKCTRL_OFFSET);
1439         CLKCTRL(am33xx_timer2_hwmod, AM43XX_CM_PER_TIMER2_CLKCTRL_OFFSET);
1440         CLKCTRL(am33xx_timer3_hwmod, AM43XX_CM_PER_TIMER3_CLKCTRL_OFFSET);
1441         CLKCTRL(am33xx_timer4_hwmod, AM43XX_CM_PER_TIMER4_CLKCTRL_OFFSET);
1442         CLKCTRL(am33xx_timer5_hwmod, AM43XX_CM_PER_TIMER5_CLKCTRL_OFFSET);
1443         CLKCTRL(am33xx_timer6_hwmod, AM43XX_CM_PER_TIMER6_CLKCTRL_OFFSET);
1444         CLKCTRL(am33xx_timer7_hwmod, AM43XX_CM_PER_TIMER7_CLKCTRL_OFFSET);
1445         CLKCTRL(am33xx_smartreflex0_hwmod,
1446                 AM43XX_CM_WKUP_SMARTREFLEX0_CLKCTRL_OFFSET);
1447         CLKCTRL(am33xx_smartreflex1_hwmod,
1448                 AM43XX_CM_WKUP_SMARTREFLEX1_CLKCTRL_OFFSET);
1449         CLKCTRL(am33xx_uart1_hwmod, AM43XX_CM_WKUP_UART0_CLKCTRL_OFFSET);
1450         CLKCTRL(am33xx_timer1_hwmod, AM43XX_CM_WKUP_TIMER1_CLKCTRL_OFFSET);
1451         CLKCTRL(am33xx_i2c1_hwmod, AM43XX_CM_WKUP_I2C0_CLKCTRL_OFFSET);
1452         CLKCTRL(am33xx_wd_timer1_hwmod, AM43XX_CM_WKUP_WDT1_CLKCTRL_OFFSET);
1453         CLKCTRL(am33xx_rtc_hwmod, AM43XX_CM_RTC_RTC_CLKCTRL_OFFSET);
1454         CLKCTRL(am33xx_mmc2_hwmod, AM43XX_CM_PER_MMC2_CLKCTRL_OFFSET);
1455         CLKCTRL(am33xx_gpmc_hwmod, AM43XX_CM_PER_GPMC_CLKCTRL_OFFSET);
1456         CLKCTRL(am33xx_l4_ls_hwmod, AM43XX_CM_PER_L4LS_CLKCTRL_OFFSET);
1457         CLKCTRL(am33xx_l4_wkup_hwmod, AM43XX_CM_WKUP_L4WKUP_CLKCTRL_OFFSET);
1458         CLKCTRL(am33xx_l3_main_hwmod, AM43XX_CM_PER_L3_CLKCTRL_OFFSET);
1459         CLKCTRL(am33xx_tpcc_hwmod, AM43XX_CM_PER_TPCC_CLKCTRL_OFFSET);
1460         CLKCTRL(am33xx_tptc0_hwmod, AM43XX_CM_PER_TPTC0_CLKCTRL_OFFSET);
1461         CLKCTRL(am33xx_tptc1_hwmod, AM43XX_CM_PER_TPTC1_CLKCTRL_OFFSET);
1462         CLKCTRL(am33xx_tptc2_hwmod, AM43XX_CM_PER_TPTC2_CLKCTRL_OFFSET);
1463         CLKCTRL(am33xx_gfx_hwmod, AM43XX_CM_GFX_GFX_CLKCTRL_OFFSET);
1464         CLKCTRL(am33xx_cpgmac0_hwmod, AM43XX_CM_PER_CPGMAC0_CLKCTRL_OFFSET);
1465         CLKCTRL(am33xx_pruss_hwmod, AM43XX_CM_PER_PRUSS_CLKCTRL_OFFSET);
1466         CLKCTRL(am33xx_mpu_hwmod , AM43XX_CM_MPU_MPU_CLKCTRL_OFFSET);
1467         CLKCTRL(am33xx_l3_instr_hwmod , AM43XX_CM_PER_L3_INSTR_CLKCTRL_OFFSET);
1468         CLKCTRL(am33xx_ocmcram_hwmod , AM43XX_CM_PER_OCMCRAM_CLKCTRL_OFFSET);
1469         CLKCTRL(am33xx_sha0_hwmod , AM43XX_CM_PER_SHA0_CLKCTRL_OFFSET);
1470         CLKCTRL(am33xx_aes0_hwmod , AM43XX_CM_PER_AES0_CLKCTRL_OFFSET);
1471 }
1472
1473 static void omap_hwmod_am43xx_rst(void)
1474 {
1475         RSTCTRL(am33xx_pruss_hwmod, AM43XX_RM_PER_RSTCTRL_OFFSET);
1476         RSTCTRL(am33xx_gfx_hwmod, AM43XX_RM_GFX_RSTCTRL_OFFSET);
1477         RSTST(am33xx_pruss_hwmod, AM43XX_RM_PER_RSTST_OFFSET);
1478         RSTST(am33xx_gfx_hwmod, AM43XX_RM_GFX_RSTST_OFFSET);
1479 }
1480
1481 void omap_hwmod_am43xx_reg(void)
1482 {
1483         omap_hwmod_am43xx_clkctrl();
1484         omap_hwmod_am43xx_rst();
1485 }