kernel/arch/arm/include/asm/cputype.h

   1 #ifndef __ASM_ARM_CPUTYPE_H
   2 #define __ASM_ARM_CPUTYPE_H
   3
   4 #include <linux/stringify.h>
   5 #include <linux/kernel.h>
   6
   7 #define CPUID_ID        0
   8 #define CPUID_CACHETYPE 1
   9 #define CPUID_TCM       2
  10 #define CPUID_TLBTYPE   3
  11 #define CPUID_MPUIR     4
  12 #define CPUID_MPIDR     5
  13 #define CPUID_REVIDR    6
  14
  15 #ifdef CONFIG_CPU_V7M
  16 #define CPUID_EXT_PFR0  0x40
  17 #define CPUID_EXT_PFR1  0x44
  18 #define CPUID_EXT_DFR0  0x48
  19 #define CPUID_EXT_AFR0  0x4c
  20 #define CPUID_EXT_MMFR0 0x50
  21 #define CPUID_EXT_MMFR1 0x54
  22 #define CPUID_EXT_MMFR2 0x58
  23 #define CPUID_EXT_MMFR3 0x5c
  24 #define CPUID_EXT_ISAR0 0x60
  25 #define CPUID_EXT_ISAR1 0x64
  26 #define CPUID_EXT_ISAR2 0x68
  27 #define CPUID_EXT_ISAR3 0x6c
  28 #define CPUID_EXT_ISAR4 0x70
  29 #define CPUID_EXT_ISAR5 0x74
  30 #else
  31 #define CPUID_EXT_PFR0  "c1, 0"
  32 #define CPUID_EXT_PFR1  "c1, 1"
  33 #define CPUID_EXT_DFR0  "c1, 2"
  34 #define CPUID_EXT_AFR0  "c1, 3"
  35 #define CPUID_EXT_MMFR0 "c1, 4"
  36 #define CPUID_EXT_MMFR1 "c1, 5"
  37 #define CPUID_EXT_MMFR2 "c1, 6"
  38 #define CPUID_EXT_MMFR3 "c1, 7"
  39 #define CPUID_EXT_ISAR0 "c2, 0"
  40 #define CPUID_EXT_ISAR1 "c2, 1"
  41 #define CPUID_EXT_ISAR2 "c2, 2"
  42 #define CPUID_EXT_ISAR3 "c2, 3"
  43 #define CPUID_EXT_ISAR4 "c2, 4"
  44 #define CPUID_EXT_ISAR5 "c2, 5"
  45 #endif
  46
  47 #define MPIDR_SMP_BITMASK (0x3 << 30)
  48 #define MPIDR_SMP_VALUE (0x2 << 30)
  49
  50 #define MPIDR_MT_BITMASK (0x1 << 24)
  51
  52 #define MPIDR_HWID_BITMASK 0xFFFFFF
  53
  54 #define MPIDR_INVALID (~MPIDR_HWID_BITMASK)
  55
  56 #define MPIDR_LEVEL_BITS 8
  57 #define MPIDR_LEVEL_MASK ((1 << MPIDR_LEVEL_BITS) - 1)
  58
  59 #define MPIDR_AFFINITY_LEVEL(mpidr, level) \
  60         ((mpidr >> (MPIDR_LEVEL_BITS * level)) & MPIDR_LEVEL_MASK)
  61
  62 #define ARM_CPU_IMP_ARM                 0x41
  63 #define ARM_CPU_IMP_INTEL               0x69
  64
  65 /* ARM implemented processors */
  66 #define ARM_CPU_PART_ARM1136            0x4100b360
  67 #define ARM_CPU_PART_ARM1156            0x4100b560
  68 #define ARM_CPU_PART_ARM1176            0x4100b760
  69 #define ARM_CPU_PART_ARM11MPCORE        0x4100b020
  70 #define ARM_CPU_PART_CORTEX_A8          0x4100c080
  71 #define ARM_CPU_PART_CORTEX_A9          0x4100c090
  72 #define ARM_CPU_PART_CORTEX_A5          0x4100c050
  73 #define ARM_CPU_PART_CORTEX_A7          0x4100c070
  74 #define ARM_CPU_PART_CORTEX_A12         0x4100c0d0
  75 #define ARM_CPU_PART_CORTEX_A17         0x4100c0e0
  76 #define ARM_CPU_PART_CORTEX_A15         0x4100c0f0
  77 #define ARM_CPU_PART_MASK               0xff00fff0
  78
  79 #define ARM_CPU_XSCALE_ARCH_MASK        0xe000
  80 #define ARM_CPU_XSCALE_ARCH_V1          0x2000
  81 #define ARM_CPU_XSCALE_ARCH_V2          0x4000
  82 #define ARM_CPU_XSCALE_ARCH_V3          0x6000
  83
  84 /* Qualcomm implemented cores */
  85 #define ARM_CPU_PART_SCORPION           0x510002d0
  86
  87 extern unsigned int processor_id;
  88
  89 #ifdef CONFIG_CPU_CP15
  90 #define read_cpuid(reg)                                                 \
  91         ({                                                              \
  92                 unsigned int __val;                                     \
  93                 asm("mrc        p15, 0, %0, c0, c0, " __stringify(reg)  \
  94                     : "=r" (__val)                                      \
  95                     :                                                   \
  96                     : "cc");                                            \
  97                 __val;                                                  \
  98         })
  99
 100 /*
 101  * The memory clobber prevents gcc 4.5 from reordering the mrc before
 102  * any is_smp() tests, which can cause undefined instruction aborts on
 103  * ARM1136 r0 due to the missing extended CP15 registers.
 104  */
 105 #define read_cpuid_ext(ext_reg)                                         \
 106         ({                                                              \
 107                 unsigned int __val;                                     \
 108                 asm("mrc        p15, 0, %0, c0, " ext_reg               \
 109                     : "=r" (__val)                                      \
 110                     :                                                   \
 111                     : "memory");                                        \
 112                 __val;                                                  \
 113         })
 114
 115 #elif defined(CONFIG_CPU_V7M)
 116
 117 #include <asm/io.h>
 118 #include <asm/v7m.h>
 119
 120 #define read_cpuid(reg)                                                 \
 121         ({                                                              \
 122                 WARN_ON_ONCE(1);                                        \
 123                 0;                                                      \
 124         })
 125
 126 static inline unsigned int __attribute_const__ read_cpuid_ext(unsigned offset)
 127 {
 128         return readl(BASEADDR_V7M_SCB + offset);
 129 }
 130
 131 #else /* ifdef CONFIG_CPU_CP15 / elif defined (CONFIG_CPU_V7M) */
 132
 133 /*
 134  * read_cpuid and read_cpuid_ext should only ever be called on machines that
 135  * have cp15 so warn on other usages.
 136  */
 137 #define read_cpuid(reg)                                                 \
 138         ({                                                              \
 139                 WARN_ON_ONCE(1);                                        \
 140                 0;                                                      \
 141         })
 142
 143 #define read_cpuid_ext(reg) read_cpuid(reg)
 144
 145 #endif /* ifdef CONFIG_CPU_CP15 / else */
 146
 147 #ifdef CONFIG_CPU_CP15
 148 /*
 149  * The CPU ID never changes at run time, so we might as well tell the
 150  * compiler that it's constant.  Use this function to read the CPU ID
 151  * rather than directly reading processor_id or read_cpuid() directly.
 152  */
 153 static inline unsigned int __attribute_const__ read_cpuid_id(void)
 154 {
 155         return read_cpuid(CPUID_ID);
 156 }
 157
 158 #elif defined(CONFIG_CPU_V7M)
 159
 160 static inline unsigned int __attribute_const__ read_cpuid_id(void)
 161 {
 162         return readl(BASEADDR_V7M_SCB + V7M_SCB_CPUID);
 163 }
 164
 165 #else /* ifdef CONFIG_CPU_CP15 / elif defined(CONFIG_CPU_V7M) */
 166
 167 static inline unsigned int __attribute_const__ read_cpuid_id(void)
 168 {
 169         return processor_id;
 170 }
 171
 172 #endif /* ifdef CONFIG_CPU_CP15 / else */
 173
 174 static inline unsigned int __attribute_const__ read_cpuid_implementor(void)
 175 {
 176         return (read_cpuid_id() & 0xFF000000) >> 24;
 177 }
 178
 179 /*
 180  * The CPU part number is meaningless without referring to the CPU
 181  * implementer: implementers are free to define their own part numbers
 182  * which are permitted to clash with other implementer part numbers.
 183  */
 184 static inline unsigned int __attribute_const__ read_cpuid_part(void)
 185 {
 186         return read_cpuid_id() & ARM_CPU_PART_MASK;
 187 }
 188
 189 static inline unsigned int __attribute_const__ __deprecated read_cpuid_part_number(void)
 190 {
 191         return read_cpuid_id() & 0xFFF0;
 192 }
 193
 194 static inline unsigned int __attribute_const__ xscale_cpu_arch_version(void)
 195 {
 196         return read_cpuid_id() & ARM_CPU_XSCALE_ARCH_MASK;
 197 }
 198
 199 static inline unsigned int __attribute_const__ read_cpuid_cachetype(void)
 200 {
 201         return read_cpuid(CPUID_CACHETYPE);
 202 }
 203
 204 static inline unsigned int __attribute_const__ read_cpuid_tcmstatus(void)
 205 {
 206         return read_cpuid(CPUID_TCM);
 207 }
 208
 209 static inline unsigned int __attribute_const__ read_cpuid_mpidr(void)
 210 {
 211         return read_cpuid(CPUID_MPIDR);
 212 }
 213
 214 /*
 215  * Intel's XScale3 core supports some v6 features (supersections, L2)
 216  * but advertises itself as v5 as it does not support the v6 ISA.  For
 217  * this reason, we need a way to explicitly test for this type of CPU.
 218  */
 219 #ifndef CONFIG_CPU_XSC3
 220 #define cpu_is_xsc3()   0
 221 #else
 222 static inline int cpu_is_xsc3(void)
 223 {
 224         unsigned int id;
 225         id = read_cpuid_id() & 0xffffe000;
 226         /* It covers both Intel ID and Marvell ID */
 227         if ((id == 0x69056000) || (id == 0x56056000))
 228                 return 1;
 229
 230         return 0;
 231 }
 232 #endif
 233
 234 #if !defined(CONFIG_CPU_XSCALE) && !defined(CONFIG_CPU_XSC3)
 235 #define cpu_is_xscale() 0
 236 #else
 237 #define cpu_is_xscale() 1
 238 #endif
 239
 240 /*
 241  * Marvell's PJ4 and PJ4B cores are based on V7 version,
 242  * but require a specical sequence for enabling coprocessors.
 243  * For this reason, we need a way to distinguish them.
 244  */
 245 #if defined(CONFIG_CPU_PJ4) || defined(CONFIG_CPU_PJ4B)
 246 static inline int cpu_is_pj4(void)
 247 {
 248         unsigned int id;
 249
 250         id = read_cpuid_id();
 251         if ((id & 0xff0fff00) == 0x560f5800)
 252                 return 1;
 253
 254         return 0;
 255 }
 256 #else
 257 #define cpu_is_pj4()    0
 258 #endif
 259
 260 static inline int __attribute_const__ cpuid_feature_extract_field(u32 features,
 261                                                                   int field)
 262 {
 263         int feature = (features >> field) & 15;
 264
 265         /* feature registers are signed values */
 266         if (feature > 8)
 267                 feature -= 16;
 268
 269         return feature;
 270 }
 271
 272 #define cpuid_feature_extract(reg, field) \
 273         cpuid_feature_extract_field(read_cpuid_ext(reg), field)
 274
 275 #endif