kernel/arch/arm/boot/dts/sun9i-a80.dtsi

   1 /*
   2  * Copyright 2014 Chen-Yu Tsai
   3  *
   4  * Chen-Yu Tsai <wens@csie.org>
   5  *
   6  * This file is dual-licensed: you can use it either under the terms
   7  * of the GPL or the X11 license, at your option. Note that this dual
   8  * licensing only applies to this file, and not this project as a
   9  * whole.
  10  *
  11  *  a) This file is free software; you can redistribute it and/or
  12  *     modify it under the terms of the GNU General Public License as
  13  *     published by the Free Software Foundation; either version 2 of the
  14  *     License, or (at your option) any later version.
  15  *
  16  *     This file is distributed in the hope that it will be useful,
  17  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  *     GNU General Public License for more details.
  20  *
  21  *     You should have received a copy of the GNU General Public
  22  *     License along with this file; if not, write to the Free
  23  *     Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
  24  *     MA 02110-1301 USA
  25  *
  26  * Or, alternatively,
  27  *
  28  *  b) Permission is hereby granted, free of charge, to any person
  29  *     obtaining a copy of this software and associated documentation
  30  *     files (the "Software"), to deal in the Software without
  31  *     restriction, including without limitation the rights to use,
  32  *     copy, modify, merge, publish, distribute, sublicense, and/or
  33  *     sell copies of the Software, and to permit persons to whom the
  34  *     Software is furnished to do so, subject to the following
  35  *     conditions:
  36  *
  37  *     The above copyright notice and this permission notice shall be
  38  *     included in all copies or substantial portions of the Software.
  39  *
  40  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  41  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  42  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  43  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  44  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  45  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  46  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  47  *     OTHER DEALINGS IN THE SOFTWARE.
  48  */
  49
  50 #include "skeleton64.dtsi"
  51
  52 #include <dt-bindings/interrupt-controller/arm-gic.h>
  53
  54 #include <dt-bindings/pinctrl/sun4i-a10.h>
  55
  56 / {
  57         interrupt-parent = <&gic>;
  58
  59         cpus {
  60                 #address-cells = <1>;
  61                 #size-cells = <0>;
  62
  63                 cpu0: cpu@0 {
  64                         compatible = "arm,cortex-a7";
  65                         device_type = "cpu";
  66                         reg = <0x0>;
  67                 };
  68
  69                 cpu1: cpu@1 {
  70                         compatible = "arm,cortex-a7";
  71                         device_type = "cpu";
  72                         reg = <0x1>;
  73                 };
  74
  75                 cpu2: cpu@2 {
  76                         compatible = "arm,cortex-a7";
  77                         device_type = "cpu";
  78                         reg = <0x2>;
  79                 };
  80
  81                 cpu3: cpu@3 {
  82                         compatible = "arm,cortex-a7";
  83                         device_type = "cpu";
  84                         reg = <0x3>;
  85                 };
  86
  87                 cpu4: cpu@100 {
  88                         compatible = "arm,cortex-a15";
  89                         device_type = "cpu";
  90                         reg = <0x100>;
  91                 };
  92
  93                 cpu5: cpu@101 {
  94                         compatible = "arm,cortex-a15";
  95                         device_type = "cpu";
  96                         reg = <0x101>;
  97                 };
  98
  99                 cpu6: cpu@102 {
 100                         compatible = "arm,cortex-a15";
 101                         device_type = "cpu";
 102                         reg = <0x102>;
 103                 };
 104
 105                 cpu7: cpu@103 {
 106                         compatible = "arm,cortex-a15";
 107                         device_type = "cpu";
 108                         reg = <0x103>;
 109                 };
 110         };
 111
 112         memory {
 113                 /* 8GB max. with LPAE */
 114                 reg = <0 0x20000000 0x02 0>;
 115         };
 116
 117         clocks {
 118                 #address-cells = <1>;
 119                 #size-cells = <1>;
 120                 /*
 121                  * map 64 bit address range down to 32 bits,
 122                  * as the peripherals are all under 512MB.
 123                  */
 124                 ranges = <0 0 0 0x20000000>;
 125
 126                 osc24M: osc24M_clk {
 127                         #clock-cells = <0>;
 128                         compatible = "fixed-clock";
 129                         clock-frequency = <24000000>;
 130                         clock-output-names = "osc24M";
 131                 };
 132
 133                 osc32k: osc32k_clk {
 134                         #clock-cells = <0>;
 135                         compatible = "fixed-clock";
 136                         clock-frequency = <32768>;
 137                         clock-output-names = "osc32k";
 138                 };
 139
 140                 pll4: clk@0600000c {
 141                         #clock-cells = <0>;
 142                         compatible = "allwinner,sun9i-a80-pll4-clk";
 143                         reg = <0x0600000c 0x4>;
 144                         clocks = <&osc24M>;
 145                         clock-output-names = "pll4";
 146                 };
 147
 148                 pll12: clk@0600002c {
 149                         #clock-cells = <0>;
 150                         compatible = "allwinner,sun9i-a80-pll4-clk";
 151                         reg = <0x0600002c 0x4>;
 152                         clocks = <&osc24M>;
 153                         clock-output-names = "pll12";
 154                 };
 155
 156                 gt_clk: clk@0600005c {
 157                         #clock-cells = <0>;
 158                         compatible = "allwinner,sun9i-a80-gt-clk";
 159                         reg = <0x0600005c 0x4>;
 160                         clocks = <&osc24M>, <&pll4>, <&pll12>, <&pll12>;
 161                         clock-output-names = "gt";
 162                 };
 163
 164                 ahb0: clk@06000060 {
 165                         #clock-cells = <0>;
 166                         compatible = "allwinner,sun9i-a80-ahb-clk";
 167                         reg = <0x06000060 0x4>;
 168                         clocks = <&gt_clk>, <&pll4>, <&pll12>, <&pll12>;
 169                         clock-output-names = "ahb0";
 170                 };
 171
 172                 ahb1: clk@06000064 {
 173                         #clock-cells = <0>;
 174                         compatible = "allwinner,sun9i-a80-ahb-clk";
 175                         reg = <0x06000064 0x4>;
 176                         clocks = <&gt_clk>, <&pll4>, <&pll12>, <&pll12>;
 177                         clock-output-names = "ahb1";
 178                 };
 179
 180                 ahb2: clk@06000068 {
 181                         #clock-cells = <0>;
 182                         compatible = "allwinner,sun9i-a80-ahb-clk";
 183                         reg = <0x06000068 0x4>;
 184                         clocks = <&gt_clk>, <&pll4>, <&pll12>, <&pll12>;
 185                         clock-output-names = "ahb2";
 186                 };
 187
 188                 apb0: clk@06000070 {
 189                         #clock-cells = <0>;
 190                         compatible = "allwinner,sun9i-a80-apb0-clk";
 191                         reg = <0x06000070 0x4>;
 192                         clocks = <&osc24M>, <&pll4>;
 193                         clock-output-names = "apb0";
 194                 };
 195
 196                 apb1: clk@06000074 {
 197                         #clock-cells = <0>;
 198                         compatible = "allwinner,sun9i-a80-apb1-clk";
 199                         reg = <0x06000074 0x4>;
 200                         clocks = <&osc24M>, <&pll4>;
 201                         clock-output-names = "apb1";
 202                 };
 203
 204                 cci400_clk: clk@06000078 {
 205                         #clock-cells = <0>;
 206                         compatible = "allwinner,sun9i-a80-gt-clk";
 207                         reg = <0x06000078 0x4>;
 208                         clocks = <&osc24M>, <&pll4>, <&pll12>, <&pll12>;
 209                         clock-output-names = "cci400";
 210                 };
 211
 212                 mmc0_clk: clk@06000410 {
 213                         #clock-cells = <1>;
 214                         compatible = "allwinner,sun9i-a80-mmc-clk";
 215                         reg = <0x06000410 0x4>;
 216                         clocks = <&osc24M>, <&pll4>;
 217                         clock-output-names = "mmc0", "mmc0_output",
 218                                              "mmc0_sample";
 219                 };
 220
 221                 mmc1_clk: clk@06000414 {
 222                         #clock-cells = <1>;
 223                         compatible = "allwinner,sun9i-a80-mmc-clk";
 224                         reg = <0x06000414 0x4>;
 225                         clocks = <&osc24M>, <&pll4>;
 226                         clock-output-names = "mmc1", "mmc1_output",
 227                                              "mmc1_sample";
 228                 };
 229
 230                 mmc2_clk: clk@06000418 {
 231                         #clock-cells = <1>;
 232                         compatible = "allwinner,sun9i-a80-mmc-clk";
 233                         reg = <0x06000418 0x4>;
 234                         clocks = <&osc24M>, <&pll4>;
 235                         clock-output-names = "mmc2", "mmc2_output",
 236                                              "mmc2_sample";
 237                 };
 238
 239                 mmc3_clk: clk@0600041c {
 240                         #clock-cells = <1>;
 241                         compatible = "allwinner,sun9i-a80-mmc-clk";
 242                         reg = <0x0600041c 0x4>;
 243                         clocks = <&osc24M>, <&pll4>;
 244                         clock-output-names = "mmc3", "mmc3_output",
 245                                              "mmc3_sample";
 246                 };
 247
 248                 ahb0_gates: clk@06000580 {
 249                         #clock-cells = <1>;
 250                         compatible = "allwinner,sun9i-a80-ahb0-gates-clk";
 251                         reg = <0x06000580 0x4>;
 252                         clocks = <&ahb0>;
 253                         clock-indices = <0>, <1>, <3>, <5>, <8>, <12>, <13>,
 254                                         <14>, <15>, <16>, <18>, <20>, <21>,
 255                                         <22>, <23>;
 256                         clock-output-names = "ahb0_fd", "ahb0_ve", "ahb0_gpu",
 257                                         "ahb0_ss", "ahb0_sd", "ahb0_nand1",
 258                                         "ahb0_nand0", "ahb0_sdram",
 259                                         "ahb0_mipi_hsi", "ahb0_sata", "ahb0_ts",
 260                                         "ahb0_spi0","ahb0_spi1", "ahb0_spi2",
 261                                         "ahb0_spi3";
 262                 };
 263
 264                 ahb1_gates: clk@06000584 {
 265                         #clock-cells = <1>;
 266                         compatible = "allwinner,sun9i-a80-ahb1-gates-clk";
 267                         reg = <0x06000584 0x4>;
 268                         clocks = <&ahb1>;
 269                         clock-indices = <0>, <1>, <17>, <21>, <22>, <23>, <24>;
 270                         clock-output-names = "ahb1_usbotg", "ahb1_usbhci",
 271                                         "ahb1_gmac", "ahb1_msgbox",
 272                                         "ahb1_spinlock", "ahb1_hstimer",
 273                                         "ahb1_dma";
 274                 };
 275
 276                 ahb2_gates: clk@06000588 {
 277                         #clock-cells = <1>;
 278                         compatible = "allwinner,sun9i-a80-ahb2-gates-clk";
 279                         reg = <0x06000588 0x4>;
 280                         clocks = <&ahb2>;
 281                         clock-indices = <0>, <1>, <2>, <4>, <5>, <7>, <8>,
 282                                         <11>;
 283                         clock-output-names = "ahb2_lcd0", "ahb2_lcd1",
 284                                         "ahb2_edp", "ahb2_csi", "ahb2_hdmi",
 285                                         "ahb2_de", "ahb2_mp", "ahb2_mipi_dsi";
 286                 };
 287
 288                 apb0_gates: clk@06000590 {
 289                         #clock-cells = <1>;
 290                         compatible = "allwinner,sun9i-a80-apb0-gates-clk";
 291                         reg = <0x06000590 0x4>;
 292                         clocks = <&apb0>;
 293                         clock-indices = <1>, <5>, <11>, <12>, <13>, <15>,
 294                                         <17>, <18>, <19>;
 295                         clock-output-names = "apb0_spdif", "apb0_pio",
 296                                         "apb0_ac97", "apb0_i2s0", "apb0_i2s1",
 297                                         "apb0_lradc", "apb0_gpadc", "apb0_twd",
 298                                         "apb0_cirtx";
 299                 };
 300
 301                 apb1_gates: clk@06000594 {
 302                         #clock-cells = <1>;
 303                         compatible = "allwinner,sun9i-a80-apb1-gates-clk";
 304                         reg = <0x06000594 0x4>;
 305                         clocks = <&apb1>;
 306                         clock-indices = <0>, <1>, <2>, <3>, <4>,
 307                                         <16>, <17>, <18>, <19>, <20>, <21>;
 308                         clock-output-names = "apb1_i2c0", "apb1_i2c1",
 309                                         "apb1_i2c2", "apb1_i2c3", "apb1_i2c4",
 310                                         "apb1_uart0", "apb1_uart1",
 311                                         "apb1_uart2", "apb1_uart3",
 312                                         "apb1_uart4", "apb1_uart5";
 313                 };
 314         };
 315
 316         soc {
 317                 compatible = "simple-bus";
 318                 #address-cells = <1>;
 319                 #size-cells = <1>;
 320                 /*
 321                  * map 64 bit address range down to 32 bits,
 322                  * as the peripherals are all under 512MB.
 323                  */
 324                 ranges = <0 0 0 0x20000000>;
 325
 326                 mmc0: mmc@01c0f000 {
 327                         compatible = "allwinner,sun5i-a13-mmc";
 328                         reg = <0x01c0f000 0x1000>;
 329                         clocks = <&mmc_config_clk 0>, <&mmc0_clk 0>,
 330                                  <&mmc0_clk 1>, <&mmc0_clk 2>;
 331                         clock-names = "ahb", "mmc", "output", "sample";
 332                         resets = <&mmc_config_clk 0>;
 333                         reset-names = "ahb";
 334                         interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 335                         status = "disabled";
 336                 };
 337
 338                 mmc1: mmc@01c10000 {
 339                         compatible = "allwinner,sun5i-a13-mmc";
 340                         reg = <0x01c10000 0x1000>;
 341                         clocks = <&mmc_config_clk 1>, <&mmc1_clk 0>,
 342                                  <&mmc1_clk 1>, <&mmc1_clk 2>;
 343                         clock-names = "ahb", "mmc", "output", "sample";
 344                         resets = <&mmc_config_clk 1>;
 345                         reset-names = "ahb";
 346                         interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 347                         status = "disabled";
 348                 };
 349
 350                 mmc2: mmc@01c11000 {
 351                         compatible = "allwinner,sun5i-a13-mmc";
 352                         reg = <0x01c11000 0x1000>;
 353                         clocks = <&mmc_config_clk 2>, <&mmc2_clk 0>,
 354                                  <&mmc2_clk 1>, <&mmc2_clk 2>;
 355                         clock-names = "ahb", "mmc", "output", "sample";
 356                         resets = <&mmc_config_clk 2>;
 357                         reset-names = "ahb";
 358                         interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 359                         status = "disabled";
 360                 };
 361
 362                 mmc3: mmc@01c12000 {
 363                         compatible = "allwinner,sun5i-a13-mmc";
 364                         reg = <0x01c12000 0x1000>;
 365                         clocks = <&mmc_config_clk 3>, <&mmc3_clk 0>,
 366                                  <&mmc3_clk 1>, <&mmc3_clk 2>;
 367                         clock-names = "ahb", "mmc", "output", "sample";
 368                         resets = <&mmc_config_clk 3>;
 369                         reset-names = "ahb";
 370                         interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
 371                         status = "disabled";
 372                 };
 373
 374                 mmc_config_clk: clk@01c13000 {
 375                         compatible = "allwinner,sun9i-a80-mmc-config-clk";
 376                         reg = <0x01c13000 0x10>;
 377                         clocks = <&ahb0_gates 8>;
 378                         clock-names = "ahb";
 379                         resets = <&ahb0_resets 8>;
 380                         reset-names = "ahb";
 381                         #clock-cells = <1>;
 382                         #reset-cells = <1>;
 383                         clock-output-names = "mmc0_config", "mmc1_config",
 384                                              "mmc2_config", "mmc3_config";
 385                 };
 386
 387                 gic: interrupt-controller@01c41000 {
 388                         compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
 389                         reg = <0x01c41000 0x1000>,
 390                               <0x01c42000 0x1000>,
 391                               <0x01c44000 0x2000>,
 392                               <0x01c46000 0x2000>;
 393                         interrupt-controller;
 394                         #interrupt-cells = <3>;
 395                         interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 396                 };
 397
 398                 ahb0_resets: reset@060005a0 {
 399                         #reset-cells = <1>;
 400                         compatible = "allwinner,sun6i-a31-clock-reset";
 401                         reg = <0x060005a0 0x4>;
 402                 };
 403
 404                 ahb1_resets: reset@060005a4 {
 405                         #reset-cells = <1>;
 406                         compatible = "allwinner,sun6i-a31-clock-reset";
 407                         reg = <0x060005a4 0x4>;
 408                 };
 409
 410                 ahb2_resets: reset@060005a8 {
 411                         #reset-cells = <1>;
 412                         compatible = "allwinner,sun6i-a31-clock-reset";
 413                         reg = <0x060005a8 0x4>;
 414                 };
 415
 416                 apb0_resets: reset@060005b0 {
 417                         #reset-cells = <1>;
 418                         compatible = "allwinner,sun6i-a31-clock-reset";
 419                         reg = <0x060005b0 0x4>;
 420                 };
 421
 422                 apb1_resets: reset@060005b4 {
 423                         #reset-cells = <1>;
 424                         compatible = "allwinner,sun6i-a31-clock-reset";
 425                         reg = <0x060005b4 0x4>;
 426                 };
 427
 428                 timer@06000c00 {
 429                         compatible = "allwinner,sun4i-a10-timer";
 430                         reg = <0x06000c00 0xa0>;
 431                         interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
 432                                      <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
 433                                      <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
 434                                      <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
 435                                      <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
 436                                      <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 437
 438                         clocks = <&osc24M>;
 439                 };
 440
 441                 pio: pinctrl@06000800 {
 442                         compatible = "allwinner,sun9i-a80-pinctrl";
 443                         reg = <0x06000800 0x400>;
 444                         interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
 445                                      <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
 446                                      <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
 447                                      <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
 448                                      <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
 449                         clocks = <&apb0_gates 5>;
 450                         gpio-controller;
 451                         interrupt-controller;
 452                         #interrupt-cells = <2>;
 453                         #size-cells = <0>;
 454                         #gpio-cells = <3>;
 455
 456                         i2c3_pins_a: i2c3@0 {
 457                                 allwinner,pins = "PG10", "PG11";
 458                                 allwinner,function = "i2c3";
 459                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 460                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 461                         };
 462
 463                         mmc0_pins: mmc0 {
 464                                 allwinner,pins = "PF0", "PF1" ,"PF2", "PF3",
 465                                                  "PF4", "PF5";
 466                                 allwinner,function = "mmc0";
 467                                 allwinner,drive = <SUN4I_PINCTRL_30_MA>;
 468                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 469                         };
 470
 471                         mmc2_8bit_pins: mmc2_8bit {
 472                                 allwinner,pins = "PC6", "PC7", "PC8", "PC9",
 473                                                  "PC10", "PC11", "PC12",
 474                                                  "PC13", "PC14", "PC15";
 475                                 allwinner,function = "mmc2";
 476                                 allwinner,drive = <SUN4I_PINCTRL_30_MA>;
 477                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 478                         };
 479
 480                         uart0_pins_a: uart0@0 {
 481                                 allwinner,pins = "PH12", "PH13";
 482                                 allwinner,function = "uart0";
 483                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 484                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 485                         };
 486
 487                         uart4_pins_a: uart4@0 {
 488                                 allwinner,pins = "PG12", "PG13", "PG14", "PG15";
 489                                 allwinner,function = "uart4";
 490                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 491                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 492                         };
 493                 };
 494
 495                 uart0: serial@07000000 {
 496                         compatible = "snps,dw-apb-uart";
 497                         reg = <0x07000000 0x400>;
 498                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
 499                         reg-shift = <2>;
 500                         reg-io-width = <4>;
 501                         clocks = <&apb1_gates 16>;
 502                         resets = <&apb1_resets 16>;
 503                         status = "disabled";
 504                 };
 505
 506                 uart1: serial@07000400 {
 507                         compatible = "snps,dw-apb-uart";
 508                         reg = <0x07000400 0x400>;
 509                         interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 510                         reg-shift = <2>;
 511                         reg-io-width = <4>;
 512                         clocks = <&apb1_gates 17>;
 513                         resets = <&apb1_resets 17>;
 514                         status = "disabled";
 515                 };
 516
 517                 uart2: serial@07000800 {
 518                         compatible = "snps,dw-apb-uart";
 519                         reg = <0x07000800 0x400>;
 520                         interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
 521                         reg-shift = <2>;
 522                         reg-io-width = <4>;
 523                         clocks = <&apb1_gates 18>;
 524                         resets = <&apb1_resets 18>;
 525                         status = "disabled";
 526                 };
 527
 528                 uart3: serial@07000c00 {
 529                         compatible = "snps,dw-apb-uart";
 530                         reg = <0x07000c00 0x400>;
 531                         interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 532                         reg-shift = <2>;
 533                         reg-io-width = <4>;
 534                         clocks = <&apb1_gates 19>;
 535                         resets = <&apb1_resets 19>;
 536                         status = "disabled";
 537                 };
 538
 539                 uart4: serial@07001000 {
 540                         compatible = "snps,dw-apb-uart";
 541                         reg = <0x07001000 0x400>;
 542                         interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
 543                         reg-shift = <2>;
 544                         reg-io-width = <4>;
 545                         clocks = <&apb1_gates 20>;
 546                         resets = <&apb1_resets 20>;
 547                         status = "disabled";
 548                 };
 549
 550                 uart5: serial@07001400 {
 551                         compatible = "snps,dw-apb-uart";
 552                         reg = <0x07001400 0x400>;
 553                         interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
 554                         reg-shift = <2>;
 555                         reg-io-width = <4>;
 556                         clocks = <&apb1_gates 21>;
 557                         resets = <&apb1_resets 21>;
 558                         status = "disabled";
 559                 };
 560
 561                 i2c0: i2c@07002800 {
 562                         compatible = "allwinner,sun6i-a31-i2c";
 563                         reg = <0x07002800 0x400>;
 564                         interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
 565                         clocks = <&apb1_gates 0>;
 566                         resets = <&apb1_resets 0>;
 567                         status = "disabled";
 568                         #address-cells = <1>;
 569                         #size-cells = <0>;
 570                 };
 571
 572                 i2c1: i2c@07002c00 {
 573                         compatible = "allwinner,sun6i-a31-i2c";
 574                         reg = <0x07002c00 0x400>;
 575                         interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
 576                         clocks = <&apb1_gates 1>;
 577                         resets = <&apb1_resets 1>;
 578                         status = "disabled";
 579                         #address-cells = <1>;
 580                         #size-cells = <0>;
 581                 };
 582
 583                 i2c2: i2c@07003000 {
 584                         compatible = "allwinner,sun6i-a31-i2c";
 585                         reg = <0x07003000 0x400>;
 586                         interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
 587                         clocks = <&apb1_gates 2>;
 588                         resets = <&apb1_resets 2>;
 589                         status = "disabled";
 590                         #address-cells = <1>;
 591                         #size-cells = <0>;
 592                 };
 593
 594                 i2c3: i2c@07003400 {
 595                         compatible = "allwinner,sun6i-a31-i2c";
 596                         reg = <0x07003400 0x400>;
 597                         interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
 598                         clocks = <&apb1_gates 3>;
 599                         resets = <&apb1_resets 3>;
 600                         status = "disabled";
 601                         #address-cells = <1>;
 602                         #size-cells = <0>;
 603                 };
 604
 605                 i2c4: i2c@07003800 {
 606                         compatible = "allwinner,sun6i-a31-i2c";
 607                         reg = <0x07003800 0x400>;
 608                         interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 609                         clocks = <&apb1_gates 4>;
 610                         resets = <&apb1_resets 4>;
 611                         status = "disabled";
 612                         #address-cells = <1>;
 613                         #size-cells = <0>;
 614                 };
 615
 616                 r_wdt: watchdog@08001000 {
 617                         compatible = "allwinner,sun6i-a31-wdt";
 618                         reg = <0x08001000 0x20>;
 619                         interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 620                 };
 621
 622                 r_uart: serial@08002800 {
 623                         compatible = "snps,dw-apb-uart";
 624                         reg = <0x08002800 0x400>;
 625                         interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 626                         reg-shift = <2>;
 627                         reg-io-width = <4>;
 628                         clocks = <&osc24M>;
 629                         status = "disabled";
 630                 };
 631         };
 632 };