kernel/arch/arm/boot/dts/sun5i-a10s.dtsi

   1 /*
   2  * Copyright 2013 Maxime Ripard
   3  *
   4  * Maxime Ripard <maxime.ripard@free-electrons.com>
   5  *
   6  * The code contained herein is licensed under the GNU General Public
   7  * License. You may obtain a copy of the GNU General Public License
   8  * Version 2 or later at the following locations:
   9  *
  10  * http://www.opensource.org/licenses/gpl-license.html
  11  * http://www.gnu.org/copyleft/gpl.html
  12  */
  13
  14 #include "skeleton.dtsi"
  15
  16 #include <dt-bindings/dma/sun4i-a10.h>
  17 #include <dt-bindings/pinctrl/sun4i-a10.h>
  18
  19 / {
  20         interrupt-parent = <&intc>;
  21
  22         aliases {
  23                 ethernet0 = &emac;
  24         };
  25
  26         chosen {
  27                 #address-cells = <1>;
  28                 #size-cells = <1>;
  29                 ranges;
  30
  31                 framebuffer@0 {
  32                         compatible = "allwinner,simple-framebuffer", "simple-framebuffer";
  33                         allwinner,pipeline = "de_be0-lcd0-hdmi";
  34                         clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 43>,
  35                                  <&ahb_gates 44>;
  36                         status = "disabled";
  37                 };
  38
  39                 framebuffer@1 {
  40                         compatible = "allwinner,simple-framebuffer",
  41                                      "simple-framebuffer";
  42                         allwinner,pipeline = "de_be0-lcd0";
  43                         clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 44>;
  44                         status = "disabled";
  45                 };
  46         };
  47
  48         cpus {
  49                 cpu@0 {
  50                         compatible = "arm,cortex-a8";
  51                 };
  52         };
  53
  54         memory {
  55                 reg = <0x40000000 0x20000000>;
  56         };
  57
  58         clocks {
  59                 #address-cells = <1>;
  60                 #size-cells = <1>;
  61                 ranges;
  62
  63                 /*
  64                  * This is a dummy clock, to be used as placeholder on
  65                  * other mux clocks when a specific parent clock is not
  66                  * yet implemented. It should be dropped when the driver
  67                  * is complete.
  68                  */
  69                 dummy: dummy {
  70                         #clock-cells = <0>;
  71                         compatible = "fixed-clock";
  72                         clock-frequency = <0>;
  73                 };
  74
  75                 osc24M: clk@01c20050 {
  76                         #clock-cells = <0>;
  77                         compatible = "allwinner,sun4i-a10-osc-clk";
  78                         reg = <0x01c20050 0x4>;
  79                         clock-frequency = <24000000>;
  80                         clock-output-names = "osc24M";
  81                 };
  82
  83                 osc32k: clk@0 {
  84                         #clock-cells = <0>;
  85                         compatible = "fixed-clock";
  86                         clock-frequency = <32768>;
  87                         clock-output-names = "osc32k";
  88                 };
  89
  90                 pll1: clk@01c20000 {
  91                         #clock-cells = <0>;
  92                         compatible = "allwinner,sun4i-a10-pll1-clk";
  93                         reg = <0x01c20000 0x4>;
  94                         clocks = <&osc24M>;
  95                         clock-output-names = "pll1";
  96                 };
  97
  98                 pll4: clk@01c20018 {
  99                         #clock-cells = <0>;
 100                         compatible = "allwinner,sun4i-a10-pll1-clk";
 101                         reg = <0x01c20018 0x4>;
 102                         clocks = <&osc24M>;
 103                         clock-output-names = "pll4";
 104                 };
 105
 106                 pll5: clk@01c20020 {
 107                         #clock-cells = <1>;
 108                         compatible = "allwinner,sun4i-a10-pll5-clk";
 109                         reg = <0x01c20020 0x4>;
 110                         clocks = <&osc24M>;
 111                         clock-output-names = "pll5_ddr", "pll5_other";
 112                 };
 113
 114                 pll6: clk@01c20028 {
 115                         #clock-cells = <1>;
 116                         compatible = "allwinner,sun4i-a10-pll6-clk";
 117                         reg = <0x01c20028 0x4>;
 118                         clocks = <&osc24M>;
 119                         clock-output-names = "pll6_sata", "pll6_other", "pll6";
 120                 };
 121
 122                 /* dummy is 200M */
 123                 cpu: cpu@01c20054 {
 124                         #clock-cells = <0>;
 125                         compatible = "allwinner,sun4i-a10-cpu-clk";
 126                         reg = <0x01c20054 0x4>;
 127                         clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>;
 128                         clock-output-names = "cpu";
 129                 };
 130
 131                 axi: axi@01c20054 {
 132                         #clock-cells = <0>;
 133                         compatible = "allwinner,sun4i-a10-axi-clk";
 134                         reg = <0x01c20054 0x4>;
 135                         clocks = <&cpu>;
 136                         clock-output-names = "axi";
 137                 };
 138
 139                 axi_gates: clk@01c2005c {
 140                         #clock-cells = <1>;
 141                         compatible = "allwinner,sun4i-a10-axi-gates-clk";
 142                         reg = <0x01c2005c 0x4>;
 143                         clocks = <&axi>;
 144                         clock-output-names = "axi_dram";
 145                 };
 146
 147                 ahb: ahb@01c20054 {
 148                         #clock-cells = <0>;
 149                         compatible = "allwinner,sun4i-a10-ahb-clk";
 150                         reg = <0x01c20054 0x4>;
 151                         clocks = <&axi>;
 152                         clock-output-names = "ahb";
 153                 };
 154
 155                 ahb_gates: clk@01c20060 {
 156                         #clock-cells = <1>;
 157                         compatible = "allwinner,sun5i-a10s-ahb-gates-clk";
 158                         reg = <0x01c20060 0x8>;
 159                         clocks = <&ahb>;
 160                         clock-output-names = "ahb_usbotg", "ahb_ehci", "ahb_ohci",
 161                                 "ahb_ss", "ahb_dma", "ahb_bist", "ahb_mmc0",
 162                                 "ahb_mmc1", "ahb_mmc2", "ahb_nand", "ahb_sdram",
 163                                 "ahb_emac", "ahb_ts", "ahb_spi0", "ahb_spi1",
 164                                 "ahb_spi2", "ahb_gps", "ahb_stimer", "ahb_ve",
 165                                 "ahb_tve", "ahb_lcd", "ahb_csi", "ahb_hdmi",
 166                                 "ahb_de_be", "ahb_de_fe", "ahb_iep", "ahb_mali400";
 167                 };
 168
 169                 apb0: apb0@01c20054 {
 170                         #clock-cells = <0>;
 171                         compatible = "allwinner,sun4i-a10-apb0-clk";
 172                         reg = <0x01c20054 0x4>;
 173                         clocks = <&ahb>;
 174                         clock-output-names = "apb0";
 175                 };
 176
 177                 apb0_gates: clk@01c20068 {
 178                         #clock-cells = <1>;
 179                         compatible = "allwinner,sun5i-a10s-apb0-gates-clk";
 180                         reg = <0x01c20068 0x4>;
 181                         clocks = <&apb0>;
 182                         clock-output-names = "apb0_codec", "apb0_iis", "apb0_pio",
 183                                 "apb0_ir", "apb0_keypad";
 184                 };
 185
 186                 apb1: clk@01c20058 {
 187                         #clock-cells = <0>;
 188                         compatible = "allwinner,sun4i-a10-apb1-clk";
 189                         reg = <0x01c20058 0x4>;
 190                         clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
 191                         clock-output-names = "apb1";
 192                 };
 193
 194                 apb1_gates: clk@01c2006c {
 195                         #clock-cells = <1>;
 196                         compatible = "allwinner,sun5i-a10s-apb1-gates-clk";
 197                         reg = <0x01c2006c 0x4>;
 198                         clocks = <&apb1>;
 199                         clock-output-names = "apb1_i2c0", "apb1_i2c1",
 200                                 "apb1_i2c2", "apb1_uart0", "apb1_uart1",
 201                                 "apb1_uart2", "apb1_uart3";
 202                 };
 203
 204                 nand_clk: clk@01c20080 {
 205                         #clock-cells = <0>;
 206                         compatible = "allwinner,sun4i-a10-mod0-clk";
 207                         reg = <0x01c20080 0x4>;
 208                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 209                         clock-output-names = "nand";
 210                 };
 211
 212                 ms_clk: clk@01c20084 {
 213                         #clock-cells = <0>;
 214                         compatible = "allwinner,sun4i-a10-mod0-clk";
 215                         reg = <0x01c20084 0x4>;
 216                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 217                         clock-output-names = "ms";
 218                 };
 219
 220                 mmc0_clk: clk@01c20088 {
 221                         #clock-cells = <1>;
 222                         compatible = "allwinner,sun4i-a10-mmc-clk";
 223                         reg = <0x01c20088 0x4>;
 224                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 225                         clock-output-names = "mmc0",
 226                                              "mmc0_output",
 227                                              "mmc0_sample";
 228                 };
 229
 230                 mmc1_clk: clk@01c2008c {
 231                         #clock-cells = <1>;
 232                         compatible = "allwinner,sun4i-a10-mmc-clk";
 233                         reg = <0x01c2008c 0x4>;
 234                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 235                         clock-output-names = "mmc1",
 236                                              "mmc1_output",
 237                                              "mmc1_sample";
 238                 };
 239
 240                 mmc2_clk: clk@01c20090 {
 241                         #clock-cells = <1>;
 242                         compatible = "allwinner,sun4i-a10-mmc-clk";
 243                         reg = <0x01c20090 0x4>;
 244                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 245                         clock-output-names = "mmc2",
 246                                              "mmc2_output",
 247                                              "mmc2_sample";
 248                 };
 249
 250                 ts_clk: clk@01c20098 {
 251                         #clock-cells = <0>;
 252                         compatible = "allwinner,sun4i-a10-mod0-clk";
 253                         reg = <0x01c20098 0x4>;
 254                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 255                         clock-output-names = "ts";
 256                 };
 257
 258                 ss_clk: clk@01c2009c {
 259                         #clock-cells = <0>;
 260                         compatible = "allwinner,sun4i-a10-mod0-clk";
 261                         reg = <0x01c2009c 0x4>;
 262                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 263                         clock-output-names = "ss";
 264                 };
 265
 266                 spi0_clk: clk@01c200a0 {
 267                         #clock-cells = <0>;
 268                         compatible = "allwinner,sun4i-a10-mod0-clk";
 269                         reg = <0x01c200a0 0x4>;
 270                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 271                         clock-output-names = "spi0";
 272                 };
 273
 274                 spi1_clk: clk@01c200a4 {
 275                         #clock-cells = <0>;
 276                         compatible = "allwinner,sun4i-a10-mod0-clk";
 277                         reg = <0x01c200a4 0x4>;
 278                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 279                         clock-output-names = "spi1";
 280                 };
 281
 282                 spi2_clk: clk@01c200a8 {
 283                         #clock-cells = <0>;
 284                         compatible = "allwinner,sun4i-a10-mod0-clk";
 285                         reg = <0x01c200a8 0x4>;
 286                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 287                         clock-output-names = "spi2";
 288                 };
 289
 290                 ir0_clk: clk@01c200b0 {
 291                         #clock-cells = <0>;
 292                         compatible = "allwinner,sun4i-a10-mod0-clk";
 293                         reg = <0x01c200b0 0x4>;
 294                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 295                         clock-output-names = "ir0";
 296                 };
 297
 298                 usb_clk: clk@01c200cc {
 299                         #clock-cells = <1>;
 300                         #reset-cells = <1>;
 301                         compatible = "allwinner,sun5i-a13-usb-clk";
 302                         reg = <0x01c200cc 0x4>;
 303                         clocks = <&pll6 1>;
 304                         clock-output-names = "usb_ohci0", "usb_phy";
 305                 };
 306
 307                 mbus_clk: clk@01c2015c {
 308                         #clock-cells = <0>;
 309                         compatible = "allwinner,sun5i-a13-mbus-clk";
 310                         reg = <0x01c2015c 0x4>;
 311                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 312                         clock-output-names = "mbus";
 313                 };
 314         };
 315
 316         soc@01c00000 {
 317                 compatible = "simple-bus";
 318                 #address-cells = <1>;
 319                 #size-cells = <1>;
 320                 ranges;
 321
 322                 dma: dma-controller@01c02000 {
 323                         compatible = "allwinner,sun4i-a10-dma";
 324                         reg = <0x01c02000 0x1000>;
 325                         interrupts = <27>;
 326                         clocks = <&ahb_gates 6>;
 327                         #dma-cells = <2>;
 328                 };
 329
 330                 spi0: spi@01c05000 {
 331                         compatible = "allwinner,sun4i-a10-spi";
 332                         reg = <0x01c05000 0x1000>;
 333                         interrupts = <10>;
 334                         clocks = <&ahb_gates 20>, <&spi0_clk>;
 335                         clock-names = "ahb", "mod";
 336                         dmas = <&dma SUN4I_DMA_DEDICATED 27>,
 337                                <&dma SUN4I_DMA_DEDICATED 26>;
 338                         dma-names = "rx", "tx";
 339                         status = "disabled";
 340                         #address-cells = <1>;
 341                         #size-cells = <0>;
 342                 };
 343
 344                 spi1: spi@01c06000 {
 345                         compatible = "allwinner,sun4i-a10-spi";
 346                         reg = <0x01c06000 0x1000>;
 347                         interrupts = <11>;
 348                         clocks = <&ahb_gates 21>, <&spi1_clk>;
 349                         clock-names = "ahb", "mod";
 350                         dmas = <&dma SUN4I_DMA_DEDICATED 9>,
 351                                <&dma SUN4I_DMA_DEDICATED 8>;
 352                         dma-names = "rx", "tx";
 353                         status = "disabled";
 354                         #address-cells = <1>;
 355                         #size-cells = <0>;
 356                 };
 357
 358                 emac: ethernet@01c0b000 {
 359                         compatible = "allwinner,sun4i-a10-emac";
 360                         reg = <0x01c0b000 0x1000>;
 361                         interrupts = <55>;
 362                         clocks = <&ahb_gates 17>;
 363                         status = "disabled";
 364                 };
 365
 366                 mdio: mdio@01c0b080 {
 367                         compatible = "allwinner,sun4i-a10-mdio";
 368                         reg = <0x01c0b080 0x14>;
 369                         status = "disabled";
 370                         #address-cells = <1>;
 371                         #size-cells = <0>;
 372                 };
 373
 374                 mmc0: mmc@01c0f000 {
 375                         compatible = "allwinner,sun5i-a13-mmc";
 376                         reg = <0x01c0f000 0x1000>;
 377                         clocks = <&ahb_gates 8>,
 378                                  <&mmc0_clk 0>,
 379                                  <&mmc0_clk 1>,
 380                                  <&mmc0_clk 2>;
 381                         clock-names = "ahb",
 382                                       "mmc",
 383                                       "output",
 384                                       "sample";
 385                         interrupts = <32>;
 386                         status = "disabled";
 387                 };
 388
 389                 mmc1: mmc@01c10000 {
 390                         compatible = "allwinner,sun5i-a13-mmc";
 391                         reg = <0x01c10000 0x1000>;
 392                         clocks = <&ahb_gates 9>,
 393                                  <&mmc1_clk 0>,
 394                                  <&mmc1_clk 1>,
 395                                  <&mmc1_clk 2>;
 396                         clock-names = "ahb",
 397                                       "mmc",
 398                                       "output",
 399                                       "sample";
 400                         interrupts = <33>;
 401                         status = "disabled";
 402                 };
 403
 404                 mmc2: mmc@01c11000 {
 405                         compatible = "allwinner,sun5i-a13-mmc";
 406                         reg = <0x01c11000 0x1000>;
 407                         clocks = <&ahb_gates 10>,
 408                                  <&mmc2_clk 0>,
 409                                  <&mmc2_clk 1>,
 410                                  <&mmc2_clk 2>;
 411                         clock-names = "ahb",
 412                                       "mmc",
 413                                       "output",
 414                                       "sample";
 415                         interrupts = <34>;
 416                         status = "disabled";
 417                 };
 418
 419                 usbphy: phy@01c13400 {
 420                         #phy-cells = <1>;
 421                         compatible = "allwinner,sun5i-a13-usb-phy";
 422                         reg = <0x01c13400 0x10 0x01c14800 0x4>;
 423                         reg-names = "phy_ctrl", "pmu1";
 424                         clocks = <&usb_clk 8>;
 425                         clock-names = "usb_phy";
 426                         resets = <&usb_clk 0>, <&usb_clk 1>;
 427                         reset-names = "usb0_reset", "usb1_reset";
 428                         status = "disabled";
 429                 };
 430
 431                 ehci0: usb@01c14000 {
 432                         compatible = "allwinner,sun5i-a10s-ehci", "generic-ehci";
 433                         reg = <0x01c14000 0x100>;
 434                         interrupts = <39>;
 435                         clocks = <&ahb_gates 1>;
 436                         phys = <&usbphy 1>;
 437                         phy-names = "usb";
 438                         status = "disabled";
 439                 };
 440
 441                 ohci0: usb@01c14400 {
 442                         compatible = "allwinner,sun5i-a10s-ohci", "generic-ohci";
 443                         reg = <0x01c14400 0x100>;
 444                         interrupts = <40>;
 445                         clocks = <&usb_clk 6>, <&ahb_gates 2>;
 446                         phys = <&usbphy 1>;
 447                         phy-names = "usb";
 448                         status = "disabled";
 449                 };
 450
 451                 spi2: spi@01c17000 {
 452                         compatible = "allwinner,sun4i-a10-spi";
 453                         reg = <0x01c17000 0x1000>;
 454                         interrupts = <12>;
 455                         clocks = <&ahb_gates 22>, <&spi2_clk>;
 456                         clock-names = "ahb", "mod";
 457                         dmas = <&dma SUN4I_DMA_DEDICATED 29>,
 458                                <&dma SUN4I_DMA_DEDICATED 28>;
 459                         dma-names = "rx", "tx";
 460                         status = "disabled";
 461                         #address-cells = <1>;
 462                         #size-cells = <0>;
 463                 };
 464
 465                 intc: interrupt-controller@01c20400 {
 466                         compatible = "allwinner,sun4i-a10-ic";
 467                         reg = <0x01c20400 0x400>;
 468                         interrupt-controller;
 469                         #interrupt-cells = <1>;
 470                 };
 471
 472                 pio: pinctrl@01c20800 {
 473                         compatible = "allwinner,sun5i-a10s-pinctrl";
 474                         reg = <0x01c20800 0x400>;
 475                         interrupts = <28>;
 476                         clocks = <&apb0_gates 5>;
 477                         gpio-controller;
 478                         interrupt-controller;
 479                         #interrupt-cells = <2>;
 480                         #size-cells = <0>;
 481                         #gpio-cells = <3>;
 482
 483                         uart0_pins_a: uart0@0 {
 484                                 allwinner,pins = "PB19", "PB20";
 485                                 allwinner,function = "uart0";
 486                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 487                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 488                         };
 489
 490                         uart2_pins_a: uart2@0 {
 491                                 allwinner,pins = "PC18", "PC19";
 492                                 allwinner,function = "uart2";
 493                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 494                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 495                         };
 496
 497                         uart3_pins_a: uart3@0 {
 498                                 allwinner,pins = "PG9", "PG10";
 499                                 allwinner,function = "uart3";
 500                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 501                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 502                         };
 503
 504                         emac_pins_a: emac0@0 {
 505                                 allwinner,pins = "PA0", "PA1", "PA2",
 506                                                 "PA3", "PA4", "PA5", "PA6",
 507                                                 "PA7", "PA8", "PA9", "PA10",
 508                                                 "PA11", "PA12", "PA13", "PA14",
 509                                                 "PA15", "PA16";
 510                                 allwinner,function = "emac";
 511                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 512                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 513                         };
 514
 515                         i2c0_pins_a: i2c0@0 {
 516                                 allwinner,pins = "PB0", "PB1";
 517                                 allwinner,function = "i2c0";
 518                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 519                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 520                         };
 521
 522                         i2c1_pins_a: i2c1@0 {
 523                                 allwinner,pins = "PB15", "PB16";
 524                                 allwinner,function = "i2c1";
 525                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 526                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 527                         };
 528
 529                         i2c2_pins_a: i2c2@0 {
 530                                 allwinner,pins = "PB17", "PB18";
 531                                 allwinner,function = "i2c2";
 532                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 533                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 534                         };
 535
 536                         mmc0_pins_a: mmc0@0 {
 537                                 allwinner,pins = "PF0","PF1","PF2","PF3","PF4","PF5";
 538                                 allwinner,function = "mmc0";
 539                                 allwinner,drive = <SUN4I_PINCTRL_30_MA>;
 540                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 541                         };
 542
 543                         mmc1_pins_a: mmc1@0 {
 544                                 allwinner,pins = "PG3","PG4","PG5","PG6","PG7","PG8";
 545                                 allwinner,function = "mmc1";
 546                                 allwinner,drive = <SUN4I_PINCTRL_30_MA>;
 547                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 548                         };
 549                 };
 550
 551                 timer@01c20c00 {
 552                         compatible = "allwinner,sun4i-a10-timer";
 553                         reg = <0x01c20c00 0x90>;
 554                         interrupts = <22>;
 555                         clocks = <&osc24M>;
 556                 };
 557
 558                 wdt: watchdog@01c20c90 {
 559                         compatible = "allwinner,sun4i-a10-wdt";
 560                         reg = <0x01c20c90 0x10>;
 561                 };
 562
 563                 lradc: lradc@01c22800 {
 564                         compatible = "allwinner,sun4i-a10-lradc-keys";
 565                         reg = <0x01c22800 0x100>;
 566                         interrupts = <31>;
 567                         status = "disabled";
 568                 };
 569
 570                 sid: eeprom@01c23800 {
 571                         compatible = "allwinner,sun4i-a10-sid";
 572                         reg = <0x01c23800 0x10>;
 573                 };
 574
 575                 rtp: rtp@01c25000 {
 576                         compatible = "allwinner,sun5i-a13-ts";
 577                         reg = <0x01c25000 0x100>;
 578                         interrupts = <29>;
 579                         #thermal-sensor-cells = <0>;
 580                 };
 581
 582                 uart0: serial@01c28000 {
 583                         compatible = "snps,dw-apb-uart";
 584                         reg = <0x01c28000 0x400>;
 585                         interrupts = <1>;
 586                         reg-shift = <2>;
 587                         reg-io-width = <4>;
 588                         clocks = <&apb1_gates 16>;
 589                         status = "disabled";
 590                 };
 591
 592                 uart1: serial@01c28400 {
 593                         compatible = "snps,dw-apb-uart";
 594                         reg = <0x01c28400 0x400>;
 595                         interrupts = <2>;
 596                         reg-shift = <2>;
 597                         reg-io-width = <4>;
 598                         clocks = <&apb1_gates 17>;
 599                         status = "disabled";
 600                 };
 601
 602                 uart2: serial@01c28800 {
 603                         compatible = "snps,dw-apb-uart";
 604                         reg = <0x01c28800 0x400>;
 605                         interrupts = <3>;
 606                         reg-shift = <2>;
 607                         reg-io-width = <4>;
 608                         clocks = <&apb1_gates 18>;
 609                         status = "disabled";
 610                 };
 611
 612                 uart3: serial@01c28c00 {
 613                         compatible = "snps,dw-apb-uart";
 614                         reg = <0x01c28c00 0x400>;
 615                         interrupts = <4>;
 616                         reg-shift = <2>;
 617                         reg-io-width = <4>;
 618                         clocks = <&apb1_gates 19>;
 619                         status = "disabled";
 620                 };
 621
 622                 i2c0: i2c@01c2ac00 {
 623                         #address-cells = <1>;
 624                         #size-cells = <0>;
 625                         compatible = "allwinner,sun5i-a10s-i2c", "allwinner,sun4i-a10-i2c";
 626                         reg = <0x01c2ac00 0x400>;
 627                         interrupts = <7>;
 628                         clocks = <&apb1_gates 0>;
 629                         status = "disabled";
 630                 };
 631
 632                 i2c1: i2c@01c2b000 {
 633                         #address-cells = <1>;
 634                         #size-cells = <0>;
 635                         compatible = "allwinner,sun5i-a10s-i2c", "allwinner,sun4i-a10-i2c";
 636                         reg = <0x01c2b000 0x400>;
 637                         interrupts = <8>;
 638                         clocks = <&apb1_gates 1>;
 639                         status = "disabled";
 640                 };
 641
 642                 i2c2: i2c@01c2b400 {
 643                         #address-cells = <1>;
 644                         #size-cells = <0>;
 645                         compatible = "allwinner,sun5i-a10s-i2c", "allwinner,sun4i-a10-i2c";
 646                         reg = <0x01c2b400 0x400>;
 647                         interrupts = <9>;
 648                         clocks = <&apb1_gates 2>;
 649                         status = "disabled";
 650                 };
 651
 652                 timer@01c60000 {
 653                         compatible = "allwinner,sun5i-a13-hstimer";
 654                         reg = <0x01c60000 0x1000>;
 655                         interrupts = <82>, <83>;
 656                         clocks = <&ahb_gates 28>;
 657                 };
 658         };
 659 };