kernel/arch/arm/boot/dts/sama5d4.dtsi

   1 /*
   2  * sama5d4.dtsi - Device Tree Include file for SAMA5D4 family SoC
   3  *
   4  *  Copyright (C) 2014 Atmel,
   5  *                2014 Nicolas Ferre <nicolas.ferre@atmel.com>
   6  *
   7  * This file is dual-licensed: you can use it either under the terms
   8  * of the GPL or the X11 license, at your option. Note that this dual
   9  * licensing only applies to this file, and not this project as a
  10  * whole.
  11  *
  12  *  a) This file is free software; you can redistribute it and/or
  13  *     modify it under the terms of the GNU General Public License as
  14  *     published by the Free Software Foundation; either version 2 of the
  15  *     License, or (at your option) any later version.
  16  *
  17  *     This file is distributed in the hope that it will be useful,
  18  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  19  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  20  *     GNU General Public License for more details.
  21  *
  22  * Or, alternatively,
  23  *
  24  *  b) Permission is hereby granted, free of charge, to any person
  25  *     obtaining a copy of this software and associated documentation
  26  *     files (the "Software"), to deal in the Software without
  27  *     restriction, including without limitation the rights to use,
  28  *     copy, modify, merge, publish, distribute, sublicense, and/or
  29  *     sell copies of the Software, and to permit persons to whom the
  30  *     Software is furnished to do so, subject to the following
  31  *     conditions:
  32  *
  33  *     The above copyright notice and this permission notice shall be
  34  *     included in all copies or substantial portions of the Software.
  35  *
  36  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  37  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  38  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  39  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  40  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  41  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  42  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  43  *     OTHER DEALINGS IN THE SOFTWARE.
  44  */
  45
  46 #include "skeleton.dtsi"
  47 #include <dt-bindings/clock/at91.h>
  48 #include <dt-bindings/dma/at91.h>
  49 #include <dt-bindings/pinctrl/at91.h>
  50 #include <dt-bindings/interrupt-controller/irq.h>
  51 #include <dt-bindings/gpio/gpio.h>
  52
  53 / {
  54         model = "Atmel SAMA5D4 family SoC";
  55         compatible = "atmel,sama5d4";
  56         interrupt-parent = <&aic>;
  57
  58         aliases {
  59                 serial0 = &usart3;
  60                 serial1 = &usart4;
  61                 serial2 = &usart2;
  62                 gpio0 = &pioA;
  63                 gpio1 = &pioB;
  64                 gpio2 = &pioC;
  65                 gpio3 = &pioD;
  66                 gpio4 = &pioE;
  67                 pwm0 = &pwm0;
  68                 ssc0 = &ssc0;
  69                 ssc1 = &ssc1;
  70                 tcb0 = &tcb0;
  71                 tcb1 = &tcb1;
  72                 i2c0 = &i2c0;
  73                 i2c1 = &i2c1;
  74                 i2c2 = &i2c2;
  75         };
  76         cpus {
  77                 #address-cells = <1>;
  78                 #size-cells = <0>;
  79
  80                 cpu@0 {
  81                         device_type = "cpu";
  82                         compatible = "arm,cortex-a5";
  83                         reg = <0>;
  84                         next-level-cache = <&L2>;
  85                 };
  86         };
  87
  88         memory {
  89                 reg = <0x20000000 0x20000000>;
  90         };
  91
  92         clocks {
  93                 slow_xtal: slow_xtal {
  94                         compatible = "fixed-clock";
  95                         #clock-cells = <0>;
  96                         clock-frequency = <0>;
  97                 };
  98
  99                 main_xtal: main_xtal {
 100                         compatible = "fixed-clock";
 101                         #clock-cells = <0>;
 102                         clock-frequency = <0>;
 103                 };
 104
 105                 adc_op_clk: adc_op_clk{
 106                         compatible = "fixed-clock";
 107                         #clock-cells = <0>;
 108                         clock-frequency = <1000000>;
 109                 };
 110         };
 111
 112         ns_sram: sram@00210000 {
 113                 compatible = "mmio-sram";
 114                 reg = <0x00210000 0x10000>;
 115         };
 116
 117         ahb {
 118                 compatible = "simple-bus";
 119                 #address-cells = <1>;
 120                 #size-cells = <1>;
 121                 ranges;
 122
 123                 usb0: gadget@00400000 {
 124                         #address-cells = <1>;
 125                         #size-cells = <0>;
 126                         compatible = "atmel,sama5d3-udc";
 127                         reg = <0x00400000 0x100000
 128                                0xfc02c000 0x4000>;
 129                         interrupts = <47 IRQ_TYPE_LEVEL_HIGH 2>;
 130                         clocks = <&udphs_clk>, <&utmi>;
 131                         clock-names = "pclk", "hclk";
 132                         status = "disabled";
 133
 134                         ep0 {
 135                                 reg = <0>;
 136                                 atmel,fifo-size = <64>;
 137                                 atmel,nb-banks = <1>;
 138                         };
 139
 140                         ep1 {
 141                                 reg = <1>;
 142                                 atmel,fifo-size = <1024>;
 143                                 atmel,nb-banks = <3>;
 144                                 atmel,can-dma;
 145                                 atmel,can-isoc;
 146                         };
 147
 148                         ep2 {
 149                                 reg = <2>;
 150                                 atmel,fifo-size = <1024>;
 151                                 atmel,nb-banks = <3>;
 152                                 atmel,can-dma;
 153                                 atmel,can-isoc;
 154                         };
 155
 156                         ep3 {
 157                                 reg = <3>;
 158                                 atmel,fifo-size = <1024>;
 159                                 atmel,nb-banks = <2>;
 160                                 atmel,can-dma;
 161                                 atmel,can-isoc;
 162                         };
 163
 164                         ep4 {
 165                                 reg = <4>;
 166                                 atmel,fifo-size = <1024>;
 167                                 atmel,nb-banks = <2>;
 168                                 atmel,can-dma;
 169                                 atmel,can-isoc;
 170                         };
 171
 172                         ep5 {
 173                                 reg = <5>;
 174                                 atmel,fifo-size = <1024>;
 175                                 atmel,nb-banks = <2>;
 176                                 atmel,can-dma;
 177                                 atmel,can-isoc;
 178                         };
 179
 180                         ep6 {
 181                                 reg = <6>;
 182                                 atmel,fifo-size = <1024>;
 183                                 atmel,nb-banks = <2>;
 184                                 atmel,can-dma;
 185                                 atmel,can-isoc;
 186                         };
 187
 188                         ep7 {
 189                                 reg = <7>;
 190                                 atmel,fifo-size = <1024>;
 191                                 atmel,nb-banks = <2>;
 192                                 atmel,can-dma;
 193                                 atmel,can-isoc;
 194                         };
 195
 196                         ep8 {
 197                                 reg = <8>;
 198                                 atmel,fifo-size = <1024>;
 199                                 atmel,nb-banks = <2>;
 200                                 atmel,can-isoc;
 201                         };
 202
 203                         ep9 {
 204                                 reg = <9>;
 205                                 atmel,fifo-size = <1024>;
 206                                 atmel,nb-banks = <2>;
 207                                 atmel,can-isoc;
 208                         };
 209
 210                         ep10 {
 211                                 reg = <10>;
 212                                 atmel,fifo-size = <1024>;
 213                                 atmel,nb-banks = <2>;
 214                                 atmel,can-isoc;
 215                         };
 216
 217                         ep11 {
 218                                 reg = <11>;
 219                                 atmel,fifo-size = <1024>;
 220                                 atmel,nb-banks = <2>;
 221                                 atmel,can-isoc;
 222                         };
 223
 224                         ep12 {
 225                                 reg = <12>;
 226                                 atmel,fifo-size = <1024>;
 227                                 atmel,nb-banks = <2>;
 228                                 atmel,can-isoc;
 229                         };
 230
 231                         ep13 {
 232                                 reg = <13>;
 233                                 atmel,fifo-size = <1024>;
 234                                 atmel,nb-banks = <2>;
 235                                 atmel,can-isoc;
 236                         };
 237
 238                         ep14 {
 239                                 reg = <14>;
 240                                 atmel,fifo-size = <1024>;
 241                                 atmel,nb-banks = <2>;
 242                                 atmel,can-isoc;
 243                         };
 244
 245                         ep15 {
 246                                 reg = <15>;
 247                                 atmel,fifo-size = <1024>;
 248                                 atmel,nb-banks = <2>;
 249                                 atmel,can-isoc;
 250                         };
 251                 };
 252
 253                 usb1: ohci@00500000 {
 254                         compatible = "atmel,at91rm9200-ohci", "usb-ohci";
 255                         reg = <0x00500000 0x100000>;
 256                         interrupts = <46 IRQ_TYPE_LEVEL_HIGH 2>;
 257                         clocks = <&usb>, <&uhphs_clk>, <&uhphs_clk>,
 258                                  <&uhpck>;
 259                         clock-names = "usb_clk", "ohci_clk", "hclk", "uhpck";
 260                         status = "disabled";
 261                 };
 262
 263                 usb2: ehci@00600000 {
 264                         compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
 265                         reg = <0x00600000 0x100000>;
 266                         interrupts = <46 IRQ_TYPE_LEVEL_HIGH 2>;
 267                         clocks = <&utmi>, <&uhphs_clk>, <&uhpck>;
 268                         clock-names = "usb_clk", "ehci_clk", "uhpck";
 269                         status = "disabled";
 270                 };
 271
 272                 L2: cache-controller@00a00000 {
 273                         compatible = "arm,pl310-cache";
 274                         reg = <0x00a00000 0x1000>;
 275                         interrupts = <67 IRQ_TYPE_LEVEL_HIGH 4>;
 276                         cache-unified;
 277                         cache-level = <2>;
 278                 };
 279
 280                 nand0: nand@80000000 {
 281                         compatible = "atmel,sama5d4-nand", "atmel,at91rm9200-nand";
 282                         #address-cells = <1>;
 283                         #size-cells = <1>;
 284                         ranges;
 285                         reg = < 0x80000000 0x08000000   /* EBI CS3 */
 286                                 0xfc05c070 0x00000490   /* SMC PMECC regs */
 287                                 0xfc05c500 0x00000100   /* SMC PMECC Error Location regs */
 288                                 >;
 289                         interrupts = <22 IRQ_TYPE_LEVEL_HIGH 6>;
 290                         atmel,nand-addr-offset = <21>;
 291                         atmel,nand-cmd-offset = <22>;
 292                         atmel,nand-has-dma;
 293                         pinctrl-names = "default";
 294                         pinctrl-0 = <&pinctrl_nand>;
 295                         status = "disabled";
 296
 297                         nfc@90000000 {
 298                                 compatible = "atmel,sama5d3-nfc";
 299                                 #address-cells = <1>;
 300                                 #size-cells = <1>;
 301                                 reg = <
 302                                         0x90000000 0x10000000   /* NFC Command Registers */
 303                                         0xfc05c000 0x00000070   /* NFC HSMC regs */
 304                                         0x00100000 0x00100000   /* NFC SRAM banks */
 305                                          >;
 306                                 clocks = <&hsmc_clk>;
 307                                 atmel,write-by-sram;
 308                         };
 309                 };
 310
 311                 apb {
 312                         compatible = "simple-bus";
 313                         #address-cells = <1>;
 314                         #size-cells = <1>;
 315                         ranges;
 316
 317                         hlcdc: hlcdc@f0000000 {
 318                                 compatible = "atmel,sama5d4-hlcdc";
 319                                 reg = <0xf0000000 0x4000>;
 320                                 interrupts = <51 IRQ_TYPE_LEVEL_HIGH 0>;
 321                                 clocks = <&lcdc_clk>, <&lcdck>, <&clk32k>;
 322                                 clock-names = "periph_clk","sys_clk", "slow_clk";
 323                                 status = "disabled";
 324
 325                                 hlcdc-display-controller {
 326                                         compatible = "atmel,hlcdc-display-controller";
 327                                         #address-cells = <1>;
 328                                         #size-cells = <0>;
 329
 330                                         port@0 {
 331                                                 #address-cells = <1>;
 332                                                 #size-cells = <0>;
 333                                                 reg = <0>;
 334                                         };
 335                                 };
 336
 337                                 hlcdc_pwm: hlcdc-pwm {
 338                                         compatible = "atmel,hlcdc-pwm";
 339                                         pinctrl-names = "default";
 340                                         pinctrl-0 = <&pinctrl_lcd_pwm>;
 341                                         #pwm-cells = <3>;
 342                                 };
 343                         };
 344
 345                         dma1: dma-controller@f0004000 {
 346                                 compatible = "atmel,sama5d4-dma";
 347                                 reg = <0xf0004000 0x200>;
 348                                 interrupts = <50 IRQ_TYPE_LEVEL_HIGH 0>;
 349                                 #dma-cells = <1>;
 350                                 clocks = <&dma1_clk>;
 351                                 clock-names = "dma_clk";
 352                         };
 353
 354                         isi: isi@f0008000 {
 355                                 compatible = "atmel,at91sam9g45-isi";
 356                                 reg = <0xf0008000 0x4000>;
 357                                 interrupts = <52 IRQ_TYPE_LEVEL_HIGH 5>;
 358                                 pinctrl-names = "default";
 359                                 pinctrl-0 = <&pinctrl_isi_data_0_7>;
 360                                 clocks = <&isi_clk>;
 361                                 clock-names = "isi_clk";
 362                                 status = "disabled";
 363                                 port {
 364                                         #address-cells = <1>;
 365                                         #size-cells = <0>;
 366                                 };
 367                         };
 368
 369                         ramc0: ramc@f0010000 {
 370                                 compatible = "atmel,sama5d3-ddramc";
 371                                 reg = <0xf0010000 0x200>;
 372                                 clocks = <&ddrck>, <&mpddr_clk>;
 373                                 clock-names = "ddrck", "mpddr";
 374                         };
 375
 376                         dma0: dma-controller@f0014000 {
 377                                 compatible = "atmel,sama5d4-dma";
 378                                 reg = <0xf0014000 0x200>;
 379                                 interrupts = <8 IRQ_TYPE_LEVEL_HIGH 0>;
 380                                 #dma-cells = <1>;
 381                                 clocks = <&dma0_clk>;
 382                                 clock-names = "dma_clk";
 383                         };
 384
 385                         pmc: pmc@f0018000 {
 386                                 compatible = "atmel,sama5d3-pmc";
 387                                 reg = <0xf0018000 0x120>;
 388                                 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
 389                                 interrupt-controller;
 390                                 #address-cells = <1>;
 391                                 #size-cells = <0>;
 392                                 #interrupt-cells = <1>;
 393
 394                                 main_rc_osc: main_rc_osc {
 395                                         compatible = "atmel,at91sam9x5-clk-main-rc-osc";
 396                                         #clock-cells = <0>;
 397                                         interrupt-parent = <&pmc>;
 398                                         interrupts = <AT91_PMC_MOSCRCS>;
 399                                         clock-frequency = <12000000>;
 400                                         clock-accuracy = <100000000>;
 401                                 };
 402
 403                                 main_osc: main_osc {
 404                                         compatible = "atmel,at91rm9200-clk-main-osc";
 405                                         #clock-cells = <0>;
 406                                         interrupt-parent = <&pmc>;
 407                                         interrupts = <AT91_PMC_MOSCS>;
 408                                         clocks = <&main_xtal>;
 409                                 };
 410
 411                                 main: mainck {
 412                                         compatible = "atmel,at91sam9x5-clk-main";
 413                                         #clock-cells = <0>;
 414                                         interrupt-parent = <&pmc>;
 415                                         interrupts = <AT91_PMC_MOSCSELS>;
 416                                         clocks = <&main_rc_osc &main_osc>;
 417                                 };
 418
 419                                 plla: pllack {
 420                                         compatible = "atmel,sama5d3-clk-pll";
 421                                         #clock-cells = <0>;
 422                                         interrupt-parent = <&pmc>;
 423                                         interrupts = <AT91_PMC_LOCKA>;
 424                                         clocks = <&main>;
 425                                         reg = <0>;
 426                                         atmel,clk-input-range = <12000000 12000000>;
 427                                         #atmel,pll-clk-output-range-cells = <4>;
 428                                         atmel,pll-clk-output-ranges = <600000000 1200000000 0 0>;
 429                                 };
 430
 431                                 plladiv: plladivck {
 432                                         compatible = "atmel,at91sam9x5-clk-plldiv";
 433                                         #clock-cells = <0>;
 434                                         clocks = <&plla>;
 435                                 };
 436
 437                                 utmi: utmick {
 438                                         compatible = "atmel,at91sam9x5-clk-utmi";
 439                                         #clock-cells = <0>;
 440                                         interrupt-parent = <&pmc>;
 441                                         interrupts = <AT91_PMC_LOCKU>;
 442                                         clocks = <&main>;
 443                                 };
 444
 445                                 mck: masterck {
 446                                         compatible = "atmel,at91sam9x5-clk-master";
 447                                         #clock-cells = <0>;
 448                                         interrupt-parent = <&pmc>;
 449                                         interrupts = <AT91_PMC_MCKRDY>;
 450                                         clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>;
 451                                         atmel,clk-output-range = <125000000 177000000>;
 452                                         atmel,clk-divisors = <1 2 4 3>;
 453                                 };
 454
 455                                 h32ck: h32mxck {
 456                                         #clock-cells = <0>;
 457                                         compatible = "atmel,sama5d4-clk-h32mx";
 458                                         clocks = <&mck>;
 459                                 };
 460
 461                                 usb: usbck {
 462                                         compatible = "atmel,at91sam9x5-clk-usb";
 463                                         #clock-cells = <0>;
 464                                         clocks = <&plladiv>, <&utmi>;
 465                                 };
 466
 467                                 prog: progck {
 468                                         compatible = "atmel,at91sam9x5-clk-programmable";
 469                                         #address-cells = <1>;
 470                                         #size-cells = <0>;
 471                                         interrupt-parent = <&pmc>;
 472                                         clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>, <&mck>;
 473
 474                                         prog0: prog0 {
 475                                                 #clock-cells = <0>;
 476                                                 reg = <0>;
 477                                                 interrupts = <AT91_PMC_PCKRDY(0)>;
 478                                         };
 479
 480                                         prog1: prog1 {
 481                                                 #clock-cells = <0>;
 482                                                 reg = <1>;
 483                                                 interrupts = <AT91_PMC_PCKRDY(1)>;
 484                                         };
 485
 486                                         prog2: prog2 {
 487                                                 #clock-cells = <0>;
 488                                                 reg = <2>;
 489                                                 interrupts = <AT91_PMC_PCKRDY(2)>;
 490                                         };
 491                                 };
 492
 493                                 smd: smdclk {
 494                                         compatible = "atmel,at91sam9x5-clk-smd";
 495                                         #clock-cells = <0>;
 496                                         clocks = <&plladiv>, <&utmi>;
 497                                 };
 498
 499                                 systemck {
 500                                         compatible = "atmel,at91rm9200-clk-system";
 501                                         #address-cells = <1>;
 502                                         #size-cells = <0>;
 503
 504                                         ddrck: ddrck {
 505                                                 #clock-cells = <0>;
 506                                                 reg = <2>;
 507                                                 clocks = <&mck>;
 508                                         };
 509
 510                                         lcdck: lcdck {
 511                                                 #clock-cells = <0>;
 512                                                 reg = <3>;
 513                                                 clocks = <&mck>;
 514                                         };
 515
 516                                         smdck: smdck {
 517                                                 #clock-cells = <0>;
 518                                                 reg = <4>;
 519                                                 clocks = <&smd>;
 520                                         };
 521
 522                                         uhpck: uhpck {
 523                                                 #clock-cells = <0>;
 524                                                 reg = <6>;
 525                                                 clocks = <&usb>;
 526                                         };
 527
 528                                         udpck: udpck {
 529                                                 #clock-cells = <0>;
 530                                                 reg = <7>;
 531                                                 clocks = <&usb>;
 532                                         };
 533
 534                                         pck0: pck0 {
 535                                                 #clock-cells = <0>;
 536                                                 reg = <8>;
 537                                                 clocks = <&prog0>;
 538                                         };
 539
 540                                         pck1: pck1 {
 541                                                 #clock-cells = <0>;
 542                                                 reg = <9>;
 543                                                 clocks = <&prog1>;
 544                                         };
 545
 546                                         pck2: pck2 {
 547                                                 #clock-cells = <0>;
 548                                                 reg = <10>;
 549                                                 clocks = <&prog2>;
 550                                         };
 551                                 };
 552
 553                                 periph32ck {
 554                                         compatible = "atmel,at91sam9x5-clk-peripheral";
 555                                         #address-cells = <1>;
 556                                         #size-cells = <0>;
 557                                         clocks = <&h32ck>;
 558
 559                                         pioD_clk: pioD_clk {
 560                                                 #clock-cells = <0>;
 561                                                 reg = <5>;
 562                                         };
 563
 564                                         usart0_clk: usart0_clk {
 565                                                 #clock-cells = <0>;
 566                                                 reg = <6>;
 567                                         };
 568
 569                                         usart1_clk: usart1_clk {
 570                                                 #clock-cells = <0>;
 571                                                 reg = <7>;
 572                                         };
 573
 574                                         icm_clk: icm_clk {
 575                                                 #clock-cells = <0>;
 576                                                 reg = <9>;
 577                                         };
 578
 579                                         aes_clk: aes_clk {
 580                                                 #clock-cells = <0>;
 581                                                 reg = <12>;
 582                                         };
 583
 584                                         tdes_clk: tdes_clk {
 585                                                 #clock-cells = <0>;
 586                                                 reg = <14>;
 587                                         };
 588
 589                                         sha_clk: sha_clk {
 590                                                 #clock-cells = <0>;
 591                                                 reg = <15>;
 592                                         };
 593
 594                                         matrix1_clk: matrix1_clk {
 595                                                 #clock-cells = <0>;
 596                                                 reg = <17>;
 597                                         };
 598
 599                                         hsmc_clk: hsmc_clk {
 600                                                 #clock-cells = <0>;
 601                                                 reg = <22>;
 602                                         };
 603
 604                                         pioA_clk: pioA_clk {
 605                                                 #clock-cells = <0>;
 606                                                 reg = <23>;
 607                                         };
 608
 609                                         pioB_clk: pioB_clk {
 610                                                 #clock-cells = <0>;
 611                                                 reg = <24>;
 612                                         };
 613
 614                                         pioC_clk: pioC_clk {
 615                                                 #clock-cells = <0>;
 616                                                 reg = <25>;
 617                                         };
 618
 619                                         pioE_clk: pioE_clk {
 620                                                 #clock-cells = <0>;
 621                                                 reg = <26>;
 622                                         };
 623
 624                                         uart0_clk: uart0_clk {
 625                                                 #clock-cells = <0>;
 626                                                 reg = <27>;
 627                                         };
 628
 629                                         uart1_clk: uart1_clk {
 630                                                 #clock-cells = <0>;
 631                                                 reg = <28>;
 632                                         };
 633
 634                                         usart2_clk: usart2_clk {
 635                                                 #clock-cells = <0>;
 636                                                 reg = <29>;
 637                                         };
 638
 639                                         usart3_clk: usart3_clk {
 640                                                 #clock-cells = <0>;
 641                                                 reg = <30>;
 642                                         };
 643
 644                                         usart4_clk: usart4_clk {
 645                                                 #clock-cells = <0>;
 646                                                 reg = <31>;
 647                                         };
 648
 649                                         twi0_clk: twi0_clk {
 650                                                 reg = <32>;
 651                                                 #clock-cells = <0>;
 652                                         };
 653
 654                                         twi1_clk: twi1_clk {
 655                                                 #clock-cells = <0>;
 656                                                 reg = <33>;
 657                                         };
 658
 659                                         twi2_clk: twi2_clk {
 660                                                 #clock-cells = <0>;
 661                                                 reg = <34>;
 662                                         };
 663
 664                                         mci0_clk: mci0_clk {
 665                                                 #clock-cells = <0>;
 666                                                 reg = <35>;
 667                                         };
 668
 669                                         mci1_clk: mci1_clk {
 670                                                 #clock-cells = <0>;
 671                                                 reg = <36>;
 672                                         };
 673
 674                                         spi0_clk: spi0_clk {
 675                                                 #clock-cells = <0>;
 676                                                 reg = <37>;
 677                                         };
 678
 679                                         spi1_clk: spi1_clk {
 680                                                 #clock-cells = <0>;
 681                                                 reg = <38>;
 682                                         };
 683
 684                                         spi2_clk: spi2_clk {
 685                                                 #clock-cells = <0>;
 686                                                 reg = <39>;
 687                                         };
 688
 689                                         tcb0_clk: tcb0_clk {
 690                                                 #clock-cells = <0>;
 691                                                 reg = <40>;
 692                                         };
 693
 694                                         tcb1_clk: tcb1_clk {
 695                                                 #clock-cells = <0>;
 696                                                 reg = <41>;
 697                                         };
 698
 699                                         tcb2_clk: tcb2_clk {
 700                                                 #clock-cells = <0>;
 701                                                 reg = <42>;
 702                                         };
 703
 704                                         pwm_clk: pwm_clk {
 705                                                 #clock-cells = <0>;
 706                                                 reg = <43>;
 707                                         };
 708
 709                                         adc_clk: adc_clk {
 710                                                 #clock-cells = <0>;
 711                                                 reg = <44>;
 712                                         };
 713
 714                                         dbgu_clk: dbgu_clk {
 715                                                 #clock-cells = <0>;
 716                                                 reg = <45>;
 717                                         };
 718
 719                                         uhphs_clk: uhphs_clk {
 720                                                 #clock-cells = <0>;
 721                                                 reg = <46>;
 722                                         };
 723
 724                                         udphs_clk: udphs_clk {
 725                                                 #clock-cells = <0>;
 726                                                 reg = <47>;
 727                                         };
 728
 729                                         ssc0_clk: ssc0_clk {
 730                                                 #clock-cells = <0>;
 731                                                 reg = <48>;
 732                                         };
 733
 734                                         ssc1_clk: ssc1_clk {
 735                                                 #clock-cells = <0>;
 736                                                 reg = <49>;
 737                                         };
 738
 739                                         trng_clk: trng_clk {
 740                                                 #clock-cells = <0>;
 741                                                 reg = <53>;
 742                                         };
 743
 744                                         macb0_clk: macb0_clk {
 745                                                 #clock-cells = <0>;
 746                                                 reg = <54>;
 747                                         };
 748
 749                                         macb1_clk: macb1_clk {
 750                                                 #clock-cells = <0>;
 751                                                 reg = <55>;
 752                                         };
 753
 754                                         fuse_clk: fuse_clk {
 755                                                 #clock-cells = <0>;
 756                                                 reg = <57>;
 757                                         };
 758
 759                                         securam_clk: securam_clk {
 760                                                 #clock-cells = <0>;
 761                                                 reg = <59>;
 762                                         };
 763
 764                                         smd_clk: smd_clk {
 765                                                 #clock-cells = <0>;
 766                                                 reg = <61>;
 767                                         };
 768
 769                                         twi3_clk: twi3_clk {
 770                                                 #clock-cells = <0>;
 771                                                 reg = <62>;
 772                                         };
 773
 774                                         catb_clk: catb_clk {
 775                                                 #clock-cells = <0>;
 776                                                 reg = <63>;
 777                                         };
 778                                 };
 779
 780                                 periph64ck {
 781                                         compatible = "atmel,at91sam9x5-clk-peripheral";
 782                                         #address-cells = <1>;
 783                                         #size-cells = <0>;
 784                                         clocks = <&mck>;
 785
 786                                         dma0_clk: dma0_clk {
 787                                                 #clock-cells = <0>;
 788                                                 reg = <8>;
 789                                         };
 790
 791                                         cpkcc_clk: cpkcc_clk {
 792                                                 #clock-cells = <0>;
 793                                                 reg = <10>;
 794                                         };
 795
 796                                         aesb_clk: aesb_clk {
 797                                                 #clock-cells = <0>;
 798                                                 reg = <13>;
 799                                         };
 800
 801                                         mpddr_clk: mpddr_clk {
 802                                                 #clock-cells = <0>;
 803                                                 reg = <16>;
 804                                         };
 805
 806                                         matrix0_clk: matrix0_clk {
 807                                                 #clock-cells = <0>;
 808                                                 reg = <18>;
 809                                         };
 810
 811                                         vdec_clk: vdec_clk {
 812                                                 #clock-cells = <0>;
 813                                                 reg = <19>;
 814                                         };
 815
 816                                         dma1_clk: dma1_clk {
 817                                                 #clock-cells = <0>;
 818                                                 reg = <50>;
 819                                         };
 820
 821                                         lcdc_clk: lcdc_clk {
 822                                                 #clock-cells = <0>;
 823                                                 reg = <51>;
 824                                         };
 825
 826                                         isi_clk: isi_clk {
 827                                                 #clock-cells = <0>;
 828                                                 reg = <52>;
 829                                         };
 830                                 };
 831                         };
 832
 833                         mmc0: mmc@f8000000 {
 834                                 compatible = "atmel,hsmci";
 835                                 reg = <0xf8000000 0x600>;
 836                                 interrupts = <35 IRQ_TYPE_LEVEL_HIGH 0>;
 837                                 dmas = <&dma1
 838                                         (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
 839                                         | AT91_XDMAC_DT_PERID(0))>;
 840                                 dma-names = "rxtx";
 841                                 pinctrl-names = "default";
 842                                 pinctrl-0 = <&pinctrl_mmc0_clk_cmd_dat0 &pinctrl_mmc0_dat1_3>;
 843                                 status = "disabled";
 844                                 #address-cells = <1>;
 845                                 #size-cells = <0>;
 846                                 clocks = <&mci0_clk>;
 847                                 clock-names = "mci_clk";
 848                         };
 849
 850                         ssc0: ssc@f8008000 {
 851                                 compatible = "atmel,at91sam9g45-ssc";
 852                                 reg = <0xf8008000 0x4000>;
 853                                 interrupts = <48 IRQ_TYPE_LEVEL_HIGH 0>;
 854                                 pinctrl-names = "default";
 855                                 pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
 856                                 dmas = <&dma1
 857                                         (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
 858                                         | AT91_XDMAC_DT_PERID(26))>,
 859                                        <&dma1
 860                                         (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
 861                                         | AT91_XDMAC_DT_PERID(27))>;
 862                                 dma-names = "tx", "rx";
 863                                 clocks = <&ssc0_clk>;
 864                                 clock-names = "pclk";
 865                                 status = "disabled";
 866                         };
 867
 868                         pwm0: pwm@f800c000 {
 869                                 compatible = "atmel,sama5d3-pwm";
 870                                 reg = <0xf800c000 0x300>;
 871                                 interrupts = <43 IRQ_TYPE_LEVEL_HIGH 4>;
 872                                 #pwm-cells = <3>;
 873                                 clocks = <&pwm_clk>;
 874                                 status = "disabled";
 875                         };
 876
 877                         spi0: spi@f8010000 {
 878                                 #address-cells = <1>;
 879                                 #size-cells = <0>;
 880                                 compatible = "atmel,at91rm9200-spi";
 881                                 reg = <0xf8010000 0x100>;
 882                                 interrupts = <37 IRQ_TYPE_LEVEL_HIGH 3>;
 883                                 dmas = <&dma1
 884                                         (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
 885                                         | AT91_XDMAC_DT_PERID(10))>,
 886                                        <&dma1
 887                                         (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
 888                                         | AT91_XDMAC_DT_PERID(11))>;
 889                                 dma-names = "tx", "rx";
 890                                 pinctrl-names = "default";
 891                                 pinctrl-0 = <&pinctrl_spi0>;
 892                                 clocks = <&spi0_clk>;
 893                                 clock-names = "spi_clk";
 894                                 status = "disabled";
 895                         };
 896
 897                         i2c0: i2c@f8014000 {
 898                                 compatible = "atmel,at91sam9x5-i2c";
 899                                 reg = <0xf8014000 0x4000>;
 900                                 interrupts = <32 IRQ_TYPE_LEVEL_HIGH 6>;
 901                                 dmas = <&dma1
 902                                         (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
 903                                         | AT91_XDMAC_DT_PERID(2))>,
 904                                        <&dma1
 905                                         (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
 906                                         | AT91_XDMAC_DT_PERID(3))>;
 907                                 dma-names = "tx", "rx";
 908                                 pinctrl-names = "default";
 909                                 pinctrl-0 = <&pinctrl_i2c0>;
 910                                 #address-cells = <1>;
 911                                 #size-cells = <0>;
 912                                 clocks = <&twi0_clk>;
 913                                 status = "disabled";
 914                         };
 915
 916                         i2c1: i2c@f8018000 {
 917                                 compatible = "atmel,at91sam9x5-i2c";
 918                                 reg = <0xf8018000 0x4000>;
 919                                 interrupts = <33 IRQ_TYPE_LEVEL_HIGH 6>;
 920                                 dmas = <&dma1
 921                                         (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1))
 922                                         AT91_XDMAC_DT_PERID(4)>,
 923                                        <&dma1
 924                                         (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1))
 925                                         AT91_XDMAC_DT_PERID(5)>;
 926                                 dma-names = "tx", "rx";
 927                                 pinctrl-names = "default";
 928                                 pinctrl-0 = <&pinctrl_i2c1>;
 929                                 #address-cells = <1>;
 930                                 #size-cells = <0>;
 931                                 clocks = <&twi1_clk>;
 932                                 status = "disabled";
 933                         };
 934
 935                         tcb0: timer@f801c000 {
 936                                 compatible = "atmel,at91sam9x5-tcb";
 937                                 reg = <0xf801c000 0x100>;
 938                                 interrupts = <40 IRQ_TYPE_LEVEL_HIGH 0>;
 939                                 clocks = <&tcb0_clk>;
 940                                 clock-names = "t0_clk";
 941                         };
 942
 943                         macb0: ethernet@f8020000 {
 944                                 compatible = "atmel,sama5d4-gem";
 945                                 reg = <0xf8020000 0x100>;
 946                                 interrupts = <54 IRQ_TYPE_LEVEL_HIGH 3>;
 947                                 pinctrl-names = "default";
 948                                 pinctrl-0 = <&pinctrl_macb0_rmii>;
 949                                 #address-cells = <1>;
 950                                 #size-cells = <0>;
 951                                 clocks = <&macb0_clk>, <&macb0_clk>;
 952                                 clock-names = "hclk", "pclk";
 953                                 status = "disabled";
 954                         };
 955
 956                         i2c2: i2c@f8024000 {
 957                                 compatible = "atmel,at91sam9x5-i2c";
 958                                 reg = <0xf8024000 0x4000>;
 959                                 interrupts = <34 IRQ_TYPE_LEVEL_HIGH 6>;
 960                                 dmas = <&dma1
 961                                         (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
 962                                         | AT91_XDMAC_DT_PERID(6))>,
 963                                        <&dma1
 964                                         (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
 965                                         | AT91_XDMAC_DT_PERID(7))>;
 966                                 dma-names = "tx", "rx";
 967                                 pinctrl-names = "default";
 968                                 pinctrl-0 = <&pinctrl_i2c2>;
 969                                 #address-cells = <1>;
 970                                 #size-cells = <0>;
 971                                 clocks = <&twi2_clk>;
 972                                 status = "disabled";
 973                         };
 974
 975                         sfr: sfr@f8028000 {
 976                                 compatible = "atmel,sama5d4-sfr", "syscon";
 977                                 reg = <0xf8028000 0x60>;
 978                         };
 979
 980                         mmc1: mmc@fc000000 {
 981                                 compatible = "atmel,hsmci";
 982                                 reg = <0xfc000000 0x600>;
 983                                 interrupts = <36 IRQ_TYPE_LEVEL_HIGH 0>;
 984                                 dmas = <&dma1
 985                                         (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
 986                                         | AT91_XDMAC_DT_PERID(1))>;
 987                                 dma-names = "rxtx";
 988                                 pinctrl-names = "default";
 989                                 pinctrl-0 = <&pinctrl_mmc1_clk_cmd_dat0 &pinctrl_mmc1_dat1_3>;
 990                                 status = "disabled";
 991                                 #address-cells = <1>;
 992                                 #size-cells = <0>;
 993                                 clocks = <&mci1_clk>;
 994                                 clock-names = "mci_clk";
 995                         };
 996
 997                         usart2: serial@fc008000 {
 998                                 compatible = "atmel,at91sam9260-usart";
 999                                 reg = <0xfc008000 0x100>;
1000                                 interrupts = <29 IRQ_TYPE_LEVEL_HIGH 5>;
1001                                 dmas = <&dma1
1002                                         (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
1003                                         | AT91_XDMAC_DT_PERID(16))>,
1004                                        <&dma1
1005                                         (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
1006                                         | AT91_XDMAC_DT_PERID(17))>;
1007                                 dma-names = "tx", "rx";
1008                                 pinctrl-names = "default";
1009                                 pinctrl-0 = <&pinctrl_usart2 &pinctrl_usart2_rts &pinctrl_usart2_cts>;
1010                                 clocks = <&usart2_clk>;
1011                                 clock-names = "usart";
1012                                 status = "disabled";
1013                         };
1014
1015                         usart3: serial@fc00c000 {
1016                                 compatible = "atmel,at91sam9260-usart";
1017                                 reg = <0xfc00c000 0x100>;
1018                                 interrupts = <30 IRQ_TYPE_LEVEL_HIGH 5>;
1019                                 dmas = <&dma1
1020                                         (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
1021                                         | AT91_XDMAC_DT_PERID(18))>,
1022                                        <&dma1
1023                                         (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
1024                                         | AT91_XDMAC_DT_PERID(19))>;
1025                                 dma-names = "tx", "rx";
1026                                 pinctrl-names = "default";
1027                                 pinctrl-0 = <&pinctrl_usart3>;
1028                                 clocks = <&usart3_clk>;
1029                                 clock-names = "usart";
1030                                 status = "disabled";
1031                         };
1032
1033                         usart4: serial@fc010000 {
1034                                 compatible = "atmel,at91sam9260-usart";
1035                                 reg = <0xfc010000 0x100>;
1036                                 interrupts = <31 IRQ_TYPE_LEVEL_HIGH 5>;
1037                                 dmas = <&dma1
1038                                         (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
1039                                         | AT91_XDMAC_DT_PERID(20))>,
1040                                        <&dma1
1041                                         (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
1042                                         | AT91_XDMAC_DT_PERID(21))>;
1043                                 dma-names = "tx", "rx";
1044                                 pinctrl-names = "default";
1045                                 pinctrl-0 = <&pinctrl_usart4>;
1046                                 clocks = <&usart4_clk>;
1047                                 clock-names = "usart";
1048                                 status = "disabled";
1049                         };
1050
1051                         ssc1: ssc@fc014000 {
1052                                 compatible = "atmel,at91sam9g45-ssc";
1053                                 reg = <0xfc014000 0x4000>;
1054                                 interrupts = <49 IRQ_TYPE_LEVEL_HIGH 0>;
1055                                 pinctrl-names = "default";
1056                                 pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>;
1057                                 dmas = <&dma1
1058                                         (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
1059                                         | AT91_XDMAC_DT_PERID(28))>,
1060                                        <&dma1
1061                                         (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
1062                                         | AT91_XDMAC_DT_PERID(29))>;
1063                                 dma-names = "tx", "rx";
1064                                 clocks = <&ssc1_clk>;
1065                                 clock-names = "pclk";
1066                                 status = "disabled";
1067                         };
1068
1069                         tcb1: timer@fc020000 {
1070                                 compatible = "atmel,at91sam9x5-tcb";
1071                                 reg = <0xfc020000 0x100>;
1072                                 interrupts = <41 IRQ_TYPE_LEVEL_HIGH 0>;
1073                                 clocks = <&tcb1_clk>;
1074                                 clock-names = "t0_clk";
1075                         };
1076
1077                         adc0: adc@fc034000 {
1078                                 compatible = "atmel,at91sam9x5-adc";
1079                                 reg = <0xfc034000 0x100>;
1080                                 interrupts = <44 IRQ_TYPE_LEVEL_HIGH 5>;
1081                                 pinctrl-names = "default";
1082                                 pinctrl-0 = <
1083                                         /* external trigger is conflict with USBA_VBUS */
1084                                         &pinctrl_adc0_ad0
1085                                         &pinctrl_adc0_ad1
1086                                         &pinctrl_adc0_ad2
1087                                         &pinctrl_adc0_ad3
1088                                         &pinctrl_adc0_ad4
1089                                         >;
1090                                 clocks = <&adc_clk>,
1091                                          <&adc_op_clk>;
1092                                 clock-names = "adc_clk", "adc_op_clk";
1093                                 atmel,adc-channels-used = <0x01f>;
1094                                 atmel,adc-startup-time = <40>;
1095                                 atmel,adc-use-external;
1096                                 atmel,adc-vref = <3000>;
1097                                 atmel,adc-res = <8 10>;
1098                                 atmel,adc-sample-hold-time = <11>;
1099                                 atmel,adc-res-names = "lowres", "highres";
1100                                 atmel,adc-ts-pressure-threshold = <10000>;
1101                                 status = "disabled";
1102
1103                                 trigger@0 {
1104                                         trigger-name = "external-rising";
1105                                         trigger-value = <0x1>;
1106                                         trigger-external;
1107                                 };
1108                                 trigger@1 {
1109                                         trigger-name = "external-falling";
1110                                         trigger-value = <0x2>;
1111                                         trigger-external;
1112                                 };
1113                                 trigger@2 {
1114                                         trigger-name = "external-any";
1115                                         trigger-value = <0x3>;
1116                                         trigger-external;
1117                                 };
1118                                 trigger@3 {
1119                                         trigger-name = "continuous";
1120                                         trigger-value = <0x6>;
1121                                 };
1122                         };
1123
1124                         aes@fc044000 {
1125                                 compatible = "atmel,at91sam9g46-aes";
1126                                 reg = <0xfc044000 0x100>;
1127                                 interrupts = <12 IRQ_TYPE_LEVEL_HIGH 0>;
1128                                 dmas = <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
1129                                         | AT91_XDMAC_DT_PERID(41))>,
1130                                        <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
1131                                         | AT91_XDMAC_DT_PERID(40))>;
1132                                 dma-names = "tx", "rx";
1133                                 clocks = <&aes_clk>;
1134                                 clock-names = "aes_clk";
1135                                 status = "disabled";
1136                         };
1137
1138                         tdes@fc04c000 {
1139                                 compatible = "atmel,at91sam9g46-tdes";
1140                                 reg = <0xfc04c000 0x100>;
1141                                 interrupts = <14 IRQ_TYPE_LEVEL_HIGH 0>;
1142                                 dmas = <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
1143                                         | AT91_XDMAC_DT_PERID(42))>,
1144                                        <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
1145                                         | AT91_XDMAC_DT_PERID(43))>;
1146                                 dma-names = "tx", "rx";
1147                                 clocks = <&tdes_clk>;
1148                                 clock-names = "tdes_clk";
1149                                 status = "disabled";
1150                         };
1151
1152                         sha@fc050000 {
1153                                 compatible = "atmel,at91sam9g46-sha";
1154                                 reg = <0xfc050000 0x100>;
1155                                 interrupts = <15 IRQ_TYPE_LEVEL_HIGH 0>;
1156                                 dmas = <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
1157                                         | AT91_XDMAC_DT_PERID(44))>;
1158                                 dma-names = "tx";
1159                                 clocks = <&sha_clk>;
1160                                 clock-names = "sha_clk";
1161                                 status = "disabled";
1162                         };
1163
1164                         rstc@fc068600 {
1165                                 compatible = "atmel,at91sam9g45-rstc";
1166                                 reg = <0xfc068600 0x10>;
1167                         };
1168
1169                         shdwc@fc068610 {
1170                                 compatible = "atmel,at91sam9x5-shdwc";
1171                                 reg = <0xfc068610 0x10>;
1172                         };
1173
1174                         pit: timer@fc068630 {
1175                                 compatible = "atmel,at91sam9260-pit";
1176                                 reg = <0xfc068630 0x10>;
1177                                 interrupts = <3 IRQ_TYPE_LEVEL_HIGH 5>;
1178                                 clocks = <&h32ck>;
1179                         };
1180
1181                         watchdog@fc068640 {
1182                                 compatible = "atmel,at91sam9260-wdt";
1183                                 reg = <0xfc068640 0x10>;
1184                                 status = "disabled";
1185                         };
1186
1187                         sckc@fc068650 {
1188                                 compatible = "atmel,at91sam9x5-sckc";
1189                                 reg = <0xfc068650 0x4>;
1190
1191                                 slow_rc_osc: slow_rc_osc {
1192                                         compatible = "atmel,at91sam9x5-clk-slow-rc-osc";
1193                                         #clock-cells = <0>;
1194                                         clock-frequency = <32768>;
1195                                         clock-accuracy = <250000000>;
1196                                         atmel,startup-time-usec = <75>;
1197                                 };
1198
1199                                 slow_osc: slow_osc {
1200                                         compatible = "atmel,at91sam9x5-clk-slow-osc";
1201                                         #clock-cells = <0>;
1202                                         clocks = <&slow_xtal>;
1203                                         atmel,startup-time-usec = <1200000>;
1204                                 };
1205
1206                                 clk32k: slowck {
1207                                         compatible = "atmel,at91sam9x5-clk-slow";
1208                                         #clock-cells = <0>;
1209                                         clocks = <&slow_rc_osc &slow_osc>;
1210                                 };
1211                         };
1212
1213                         rtc@fc0686b0 {
1214                                 compatible = "atmel,at91rm9200-rtc";
1215                                 reg = <0xfc0686b0 0x30>;
1216                                 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
1217                         };
1218
1219                         dbgu: serial@fc069000 {
1220                                 compatible = "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart";
1221                                 reg = <0xfc069000 0x200>;
1222                                 interrupts = <2 IRQ_TYPE_LEVEL_HIGH 7>;
1223                                 pinctrl-names = "default";
1224                                 pinctrl-0 = <&pinctrl_dbgu>;
1225                                 clocks = <&dbgu_clk>;
1226                                 clock-names = "usart";
1227                                 status = "disabled";
1228                         };
1229
1230
1231                         pinctrl@fc06a000 {
1232                                 #address-cells = <1>;
1233                                 #size-cells = <1>;
1234                                 compatible = "atmel,at91sam9x5-pinctrl", "atmel,at91rm9200-pinctrl", "simple-bus";
1235                                 ranges = <0xfc06a000 0xfc06a000 0x4000>;
1236                                 /* WARNING: revisit as pin spec has changed */
1237                                 atmel,mux-mask = <
1238                                         /*   A          B          C  */
1239                                         0xffffffff 0x3ffcfe7c 0x1c010101        /* pioA */
1240                                         0x7fffffff 0xfffccc3a 0x3f00cc3a        /* pioB */
1241                                         0xffffffff 0x3ff83fff 0xff00ffff        /* pioC */
1242                                         0x00000000 0x00000000 0x00000000        /* pioD */
1243                                         0xffffffff 0x7fffffff 0x76fff1bf        /* pioE */
1244                                         >;
1245
1246                                 pioA: gpio@fc06a000 {
1247                                         compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
1248                                         reg = <0xfc06a000 0x100>;
1249                                         interrupts = <23 IRQ_TYPE_LEVEL_HIGH 1>;
1250                                         #gpio-cells = <2>;
1251                                         gpio-controller;
1252                                         interrupt-controller;
1253                                         #interrupt-cells = <2>;
1254                                         clocks = <&pioA_clk>;
1255                                 };
1256
1257                                 pioB: gpio@fc06b000 {
1258                                         compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
1259                                         reg = <0xfc06b000 0x100>;
1260                                         interrupts = <24 IRQ_TYPE_LEVEL_HIGH 1>;
1261                                         #gpio-cells = <2>;
1262                                         gpio-controller;
1263                                         interrupt-controller;
1264                                         #interrupt-cells = <2>;
1265                                         clocks = <&pioB_clk>;
1266                                 };
1267
1268                                 pioC: gpio@fc06c000 {
1269                                         compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
1270                                         reg = <0xfc06c000 0x100>;
1271                                         interrupts = <25 IRQ_TYPE_LEVEL_HIGH 1>;
1272                                         #gpio-cells = <2>;
1273                                         gpio-controller;
1274                                         interrupt-controller;
1275                                         #interrupt-cells = <2>;
1276                                         clocks = <&pioC_clk>;
1277                                 };
1278
1279                                 pioD: gpio@fc068000 {
1280                                         compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
1281                                         reg = <0xfc068000 0x100>;
1282                                         interrupts = <5 IRQ_TYPE_LEVEL_HIGH 1>;
1283                                         #gpio-cells = <2>;
1284                                         gpio-controller;
1285                                         interrupt-controller;
1286                                         #interrupt-cells = <2>;
1287                                         clocks = <&pioD_clk>;
1288                                         status = "disabled";
1289                                 };
1290
1291                                 pioE: gpio@fc06d000 {
1292                                         compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
1293                                         reg = <0xfc06d000 0x100>;
1294                                         interrupts = <26 IRQ_TYPE_LEVEL_HIGH 1>;
1295                                         #gpio-cells = <2>;
1296                                         gpio-controller;
1297                                         interrupt-controller;
1298                                         #interrupt-cells = <2>;
1299                                         clocks = <&pioE_clk>;
1300                                 };
1301
1302                                 /* pinctrl pin settings */
1303                                 adc0 {
1304                                         pinctrl_adc0_adtrg: adc0_adtrg {
1305                                                 atmel,pins =
1306                                                         <AT91_PIOE 31 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* conflicts with USBA_VBUS */
1307                                         };
1308                                         pinctrl_adc0_ad0: adc0_ad0 {
1309                                                 atmel,pins =
1310                                                         <AT91_PIOC 27 AT91_PERIPH_A AT91_PINCTRL_NONE>;
1311                                         };
1312                                         pinctrl_adc0_ad1: adc0_ad1 {
1313                                                 atmel,pins =
1314                                                         <AT91_PIOC 28 AT91_PERIPH_A AT91_PINCTRL_NONE>;
1315                                         };
1316                                         pinctrl_adc0_ad2: adc0_ad2 {
1317                                                 atmel,pins =
1318                                                         <AT91_PIOC 29 AT91_PERIPH_A AT91_PINCTRL_NONE>;
1319                                         };
1320                                         pinctrl_adc0_ad3: adc0_ad3 {
1321                                                 atmel,pins =
1322                                                         <AT91_PIOC 30 AT91_PERIPH_A AT91_PINCTRL_NONE>;
1323                                         };
1324                                         pinctrl_adc0_ad4: adc0_ad4 {
1325                                                 atmel,pins =
1326                                                         <AT91_PIOC 31 AT91_PERIPH_A AT91_PINCTRL_NONE>;
1327                                         };
1328                                 };
1329
1330                                 dbgu {
1331                                         pinctrl_dbgu: dbgu-0 {
1332                                                 atmel,pins =
1333                                                         <AT91_PIOB 24 AT91_PERIPH_A AT91_PINCTRL_NONE>,     /* conflicts with D14 and TDI */
1334                                                         <AT91_PIOB 25 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;  /* conflicts with D15 and TDO */
1335                                         };
1336                                 };
1337
1338                                 i2c0 {
1339                                         pinctrl_i2c0: i2c0-0 {
1340                                                 atmel,pins =
1341                                                         <AT91_PIOA 30 AT91_PERIPH_A AT91_PINCTRL_NONE
1342                                                          AT91_PIOA 31 AT91_PERIPH_A AT91_PINCTRL_NONE>;
1343                                         };
1344                                 };
1345
1346                                 i2c1 {
1347                                         pinctrl_i2c1: i2c1-0 {
1348                                                 atmel,pins =
1349                                                         <AT91_PIOE 29 AT91_PERIPH_C AT91_PINCTRL_NONE   /* TWD1, conflicts with UART0 RX and DIBP */
1350                                                          AT91_PIOE 30 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* TWCK1, conflicts with UART0 TX and DIBN */
1351                                         };
1352                                 };
1353
1354                                 i2c2 {
1355                                         pinctrl_i2c2: i2c2-0 {
1356                                                 atmel,pins =
1357                                                         <AT91_PIOB 29 AT91_PERIPH_A AT91_PINCTRL_NONE   /* TWD2, conflicts with RD0 and PWML1 */
1358                                                          AT91_PIOB 30 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* TWCK2, conflicts with RF0 */
1359                                         };
1360                                 };
1361
1362                                 isi {
1363                                         pinctrl_isi_data_0_7: isi-0-data-0-7 {
1364                                                 atmel,pins =
1365                                                         <AT91_PIOC 19 AT91_PERIPH_A AT91_PINCTRL_NONE   /* ISI_D0 */
1366                                                          AT91_PIOC 20 AT91_PERIPH_A AT91_PINCTRL_NONE   /* ISI_D1 */
1367                                                          AT91_PIOC 21 AT91_PERIPH_A AT91_PINCTRL_NONE   /* ISI_D2 */
1368                                                          AT91_PIOC 22 AT91_PERIPH_A AT91_PINCTRL_NONE   /* ISI_D3 */
1369                                                          AT91_PIOC 23 AT91_PERIPH_A AT91_PINCTRL_NONE   /* ISI_D4 */
1370                                                          AT91_PIOC 24 AT91_PERIPH_A AT91_PINCTRL_NONE   /* ISI_D5 */
1371                                                          AT91_PIOC 25 AT91_PERIPH_A AT91_PINCTRL_NONE   /* ISI_D6 */
1372                                                          AT91_PIOC 26 AT91_PERIPH_A AT91_PINCTRL_NONE   /* ISI_D7 */
1373                                                          AT91_PIOB  1 AT91_PERIPH_C AT91_PINCTRL_NONE   /* ISI_PCK, conflict with G0_RXCK */
1374                                                          AT91_PIOB  3 AT91_PERIPH_C AT91_PINCTRL_NONE   /* ISI_VSYNC */
1375                                                          AT91_PIOB  4 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* ISI_HSYNC */
1376                                         };
1377                                         pinctrl_isi_data_8_9: isi-0-data-8-9 {
1378                                                 atmel,pins =
1379                                                         <AT91_PIOC 0 AT91_PERIPH_C AT91_PINCTRL_NONE    /* ISI_D8, conflicts with SPI0_MISO, PWMH2 */
1380                                                          AT91_PIOC 1 AT91_PERIPH_C AT91_PINCTRL_NONE>;  /* ISI_D9, conflicts with SPI0_MOSI, PWML2 */
1381                                         };
1382                                         pinctrl_isi_data_10_11: isi-0-data-10-11 {
1383                                                 atmel,pins =
1384                                                         <AT91_PIOC 2 AT91_PERIPH_C AT91_PINCTRL_NONE    /* ISI_D10, conflicts with SPI0_SPCK, PWMH3 */
1385                                                          AT91_PIOC 3 AT91_PERIPH_C AT91_PINCTRL_NONE>;  /* ISI_D11, conflicts with SPI0_NPCS0, PWML3 */
1386                                         };
1387                                 };
1388
1389                                 lcd {
1390                                         pinctrl_lcd_base: lcd-base-0 {
1391                                                 atmel,pins =
1392                                                         <AT91_PIOA 26 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDVSYNC */
1393                                                          AT91_PIOA 27 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDHSYNC */
1394                                                          AT91_PIOA 29 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDDEN */
1395                                                          AT91_PIOA 28 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* LCDPCK */
1396                                         };
1397                                         pinctrl_lcd_pwm: lcd-pwm-0 {
1398                                                 atmel,pins = <AT91_PIOA 24 AT91_PERIPH_A AT91_PINCTRL_NONE>;    /* LCDPWM */
1399                                         };
1400                                         pinctrl_lcd_rgb444: lcd-rgb-0 {
1401                                                 atmel,pins =
1402                                                         <AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD0 pin */
1403                                                          AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD1 pin */
1404                                                          AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD2 pin */
1405                                                          AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD3 pin */
1406                                                          AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD4 pin */
1407                                                          AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD5 pin */
1408                                                          AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD6 pin */
1409                                                          AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD7 pin */
1410                                                          AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD8 pin */
1411                                                          AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD9 pin */
1412                                                          AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD10 pin */
1413                                                          AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* LCDD11 pin */
1414                                         };
1415                                         pinctrl_lcd_rgb565: lcd-rgb-1 {
1416                                                 atmel,pins =
1417                                                         <AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD0 pin */
1418                                                          AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD1 pin */
1419                                                          AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD2 pin */
1420                                                          AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD3 pin */
1421                                                          AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD4 pin */
1422                                                          AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD5 pin */
1423                                                          AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD6 pin */
1424                                                          AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD7 pin */
1425                                                          AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD8 pin */
1426                                                          AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD9 pin */
1427                                                          AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD10 pin */
1428                                                          AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD11 pin */
1429                                                          AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD12 pin */
1430                                                          AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD13 pin */
1431                                                          AT91_PIOA 14 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD14 pin */
1432                                                          AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* LCDD15 pin */
1433                                         };
1434                                         pinctrl_lcd_rgb666: lcd-rgb-2 {
1435                                                 atmel,pins =
1436                                                         <AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD2 pin */
1437                                                          AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD3 pin */
1438                                                          AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD4 pin */
1439                                                          AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD5 pin */
1440                                                          AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD6 pin */
1441                                                          AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD7 pin */
1442                                                          AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD10 pin */
1443                                                          AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD11 pin */
1444                                                          AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD12 pin */
1445                                                          AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD13 pin */
1446                                                          AT91_PIOA 14 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD14 pin */
1447                                                          AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD15 pin */
1448                                                          AT91_PIOA 18 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD18 pin */
1449                                                          AT91_PIOA 19 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD19 pin */
1450                                                          AT91_PIOA 20 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD20 pin */
1451                                                          AT91_PIOA 21 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD21 pin */
1452                                                          AT91_PIOA 22 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD22 pin */
1453                                                          AT91_PIOA 23 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* LCDD23 pin */
1454                                         };
1455                                         pinctrl_lcd_rgb777: lcd-rgb-3 {
1456                                                 atmel,pins =
1457                                                          /* LCDDAT0 conflicts with TMS */
1458                                                         <AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD1 pin */
1459                                                          AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD2 pin */
1460                                                          AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD3 pin */
1461                                                          AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD4 pin */
1462                                                          AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD5 pin */
1463                                                          AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD6 pin */
1464                                                          AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD7 pin */
1465                                                          /* LCDDAT8 conflicts with TCK */
1466                                                          AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD9 pin */
1467                                                          AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD10 pin */
1468                                                          AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD11 pin */
1469                                                          AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD12 pin */
1470                                                          AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD13 pin */
1471                                                          AT91_PIOA 14 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD14 pin */
1472                                                          AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD15 pin */
1473                                                          /* LCDDAT16 conflicts with NTRST */
1474                                                          AT91_PIOA 17 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD17 pin */
1475                                                          AT91_PIOA 18 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD18 pin */
1476                                                          AT91_PIOA 19 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD19 pin */
1477                                                          AT91_PIOA 20 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD20 pin */
1478                                                          AT91_PIOA 21 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD21 pin */
1479                                                          AT91_PIOA 22 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD22 pin */
1480                                                          AT91_PIOA 23 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* LCDD23 pin */
1481                                         };
1482                                         pinctrl_lcd_rgb888: lcd-rgb-4 {
1483                                                 atmel,pins =
1484                                                         <AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD0 pin */
1485                                                          AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD1 pin */
1486                                                          AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD2 pin */
1487                                                          AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD3 pin */
1488                                                          AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD4 pin */
1489                                                          AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD5 pin */
1490                                                          AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD6 pin */
1491                                                          AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD7 pin */
1492                                                          AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD8 pin */
1493                                                          AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD9 pin */
1494                                                          AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD10 pin */
1495                                                          AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD11 pin */
1496                                                          AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD12 pin */
1497                                                          AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD13 pin */
1498                                                          AT91_PIOA 14 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD14 pin */
1499                                                          AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD15 pin */
1500                                                          AT91_PIOA 16 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD16 pin */
1501                                                          AT91_PIOA 17 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD17 pin */
1502                                                          AT91_PIOA 18 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD18 pin */
1503                                                          AT91_PIOA 19 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD19 pin */
1504                                                          AT91_PIOA 20 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD20 pin */
1505                                                          AT91_PIOA 21 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD21 pin */
1506                                                          AT91_PIOA 22 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD22 pin */
1507                                                          AT91_PIOA 23 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* LCDD23 pin */
1508                                         };
1509                                 };
1510
1511                                 macb0 {
1512                                         pinctrl_macb0_rmii: macb0_rmii-0 {
1513                                                 atmel,pins =
1514                                                         <AT91_PIOB 12 AT91_PERIPH_A AT91_PINCTRL_NONE   /* G0_TX0 */
1515                                                          AT91_PIOB 13 AT91_PERIPH_A AT91_PINCTRL_NONE   /* G0_TX1 */
1516                                                          AT91_PIOB  8 AT91_PERIPH_A AT91_PINCTRL_NONE   /* G0_RX0 */
1517                                                          AT91_PIOB  9 AT91_PERIPH_A AT91_PINCTRL_NONE   /* G0_RX1 */
1518                                                          AT91_PIOB  6 AT91_PERIPH_A AT91_PINCTRL_NONE   /* G0_RXDV */
1519                                                          AT91_PIOB  7 AT91_PERIPH_A AT91_PINCTRL_NONE   /* G0_RXER */
1520                                                          AT91_PIOB  2 AT91_PERIPH_A AT91_PINCTRL_NONE   /* G0_TXEN */
1521                                                          AT91_PIOB  0 AT91_PERIPH_A AT91_PINCTRL_NONE   /* G0_TXCK */
1522                                                          AT91_PIOB 16 AT91_PERIPH_A AT91_PINCTRL_NONE   /* G0_MDC */
1523                                                          AT91_PIOB 17 AT91_PERIPH_A AT91_PINCTRL_NONE   /* G0_MDIO */
1524                                                         >;
1525                                         };
1526                                 };
1527
1528                                 mmc0 {
1529                                         pinctrl_mmc0_clk_cmd_dat0: mmc0_clk_cmd_dat0 {
1530                                                 atmel,pins =
1531                                                         <AT91_PIOC 4 AT91_PERIPH_B AT91_PINCTRL_NONE    /* MCI0_CK, conflict with PCK1(ISI_MCK) */
1532                                                          AT91_PIOC 5 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* MCI0_CDB, conflict with NAND_D0 */
1533                                                          AT91_PIOC 6 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* MCI0_DB0, conflict with NAND_D1 */
1534                                                         >;
1535                                         };
1536                                         pinctrl_mmc0_dat1_3: mmc0_dat1_3 {
1537                                                 atmel,pins =
1538                                                         <AT91_PIOC 7 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* MCI0_DB1, conflict with NAND_D2 */
1539                                                          AT91_PIOC 8 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* MCI0_DB2, conflict with NAND_D3 */
1540                                                          AT91_PIOC 9 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* MCI0_DB3, conflict with NAND_D4 */
1541                                                         >;
1542                                         };
1543                                 };
1544
1545                                 mmc1 {
1546                                         pinctrl_mmc1_clk_cmd_dat0: mmc1_clk_cmd_dat0 {
1547                                                 atmel,pins =
1548                                                         <AT91_PIOE 18 AT91_PERIPH_C AT91_PINCTRL_NONE           /* MCI1_CK */
1549                                                          AT91_PIOE 19 AT91_PERIPH_C AT91_PINCTRL_PULL_UP        /* MCI1_CDA */
1550                                                          AT91_PIOE 20 AT91_PERIPH_C AT91_PINCTRL_PULL_UP        /* MCI1_DA0 */
1551                                                         >;
1552                                         };
1553                                         pinctrl_mmc1_dat1_3: mmc1_dat1_3 {
1554                                                 atmel,pins =
1555                                                         <AT91_PIOE 21 AT91_PERIPH_C AT91_PINCTRL_PULL_UP        /* MCI1_DA1 */
1556                                                          AT91_PIOE 22 AT91_PERIPH_C AT91_PINCTRL_PULL_UP        /* MCI1_DA2 */
1557                                                          AT91_PIOE 23 AT91_PERIPH_C AT91_PINCTRL_PULL_UP        /* MCI1_DA3 */
1558                                                         >;
1559                                         };
1560                                 };
1561
1562                                 nand0 {
1563                                         pinctrl_nand: nand-0 {
1564                                                 atmel,pins =
1565                                                         <AT91_PIOC 13 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PC13 periph A Read Enable */
1566                                                          AT91_PIOC 14 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PC14 periph A Write Enable */
1567
1568                                                          AT91_PIOC 17 AT91_PERIPH_A AT91_PINCTRL_PULL_UP        /* PC17 ALE */
1569                                                          AT91_PIOC 18 AT91_PERIPH_A AT91_PINCTRL_PULL_UP        /* PC18 CLE */
1570
1571                                                          AT91_PIOC 15 AT91_PERIPH_A AT91_PINCTRL_PULL_UP        /* PC15 NCS3/Chip Enable */
1572                                                          AT91_PIOC 16 AT91_PERIPH_A AT91_PINCTRL_PULL_UP        /* PC16 NANDRDY */
1573                                                          AT91_PIOC 5 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PC5 Data bit 0 */
1574                                                          AT91_PIOC 6 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PC6 Data bit 1 */
1575                                                          AT91_PIOC 7 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PC7 Data bit 2 */
1576                                                          AT91_PIOC 8 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PC8 Data bit 3 */
1577                                                          AT91_PIOC 9 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PC9 Data bit 4 */
1578                                                          AT91_PIOC 10 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PC10 Data bit 5 */
1579                                                          AT91_PIOC 11 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PC11 periph A Data bit 6 */
1580                                                          AT91_PIOC 12 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PC12 periph A Data bit 7 */
1581                                         };
1582                                 };
1583
1584                                 spi0 {
1585                                         pinctrl_spi0: spi0-0 {
1586                                                 atmel,pins =
1587                                                         <AT91_PIOC 0 AT91_PERIPH_A AT91_PINCTRL_NONE    /* SPI0_MISO */
1588                                                          AT91_PIOC 1 AT91_PERIPH_A AT91_PINCTRL_NONE    /* SPI0_MOSI */
1589                                                          AT91_PIOC 2 AT91_PERIPH_A AT91_PINCTRL_NONE    /* SPI0_SPCK */
1590                                                         >;
1591                                         };
1592                                 };
1593
1594                                 ssc0 {
1595                                         pinctrl_ssc0_tx: ssc0_tx {
1596                                                 atmel,pins =
1597                                                         <AT91_PIOB 27 AT91_PERIPH_B AT91_PINCTRL_NONE   /* TK0 */
1598                                                          AT91_PIOB 31 AT91_PERIPH_B AT91_PINCTRL_NONE   /* TF0 */
1599                                                          AT91_PIOB 28 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* TD0 */
1600                                         };
1601
1602                                         pinctrl_ssc0_rx: ssc0_rx {
1603                                                 atmel,pins =
1604                                                         <AT91_PIOB 26 AT91_PERIPH_B AT91_PINCTRL_NONE   /* RK0 */
1605                                                          AT91_PIOB 30 AT91_PERIPH_B AT91_PINCTRL_NONE   /* RF0 */
1606                                                          AT91_PIOB 29 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* RD0 */
1607                                         };
1608                                 };
1609
1610                                 ssc1 {
1611                                         pinctrl_ssc1_tx: ssc1_tx {
1612                                                 atmel,pins =
1613                                                         <AT91_PIOC 19 AT91_PERIPH_B AT91_PINCTRL_NONE   /* TK1 */
1614                                                          AT91_PIOC 20 AT91_PERIPH_B AT91_PINCTRL_NONE   /* TF1 */
1615                                                          AT91_PIOC 21 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* TD1 */
1616                                         };
1617
1618                                         pinctrl_ssc1_rx: ssc1_rx {
1619                                                 atmel,pins =
1620                                                         <AT91_PIOC 24 AT91_PERIPH_B AT91_PINCTRL_NONE   /* RK1 */
1621                                                          AT91_PIOC 22 AT91_PERIPH_B AT91_PINCTRL_NONE   /* RF1 */
1622                                                          AT91_PIOC 23 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* RD1 */
1623                                         };
1624                                 };
1625
1626                                 usart2 {
1627                                         pinctrl_usart2: usart2-0 {
1628                                                 atmel,pins =
1629                                                         <AT91_PIOB 4 AT91_PERIPH_B AT91_PINCTRL_NONE            /* RXD - conflicts with G0_CRS, ISI_HSYNC */
1630                                                          AT91_PIOB 5 AT91_PERIPH_B AT91_PINCTRL_PULL_UP         /* TXD - conflicts with G0_COL, PCK2 */
1631                                                         >;
1632                                         };
1633                                         pinctrl_usart2_rts: usart2_rts-0 {
1634                                                 atmel,pins = <AT91_PIOB 11 AT91_PERIPH_B AT91_PINCTRL_NONE>;    /* conflicts with G0_RX3, PWMH1 */
1635                                         };
1636                                         pinctrl_usart2_cts: usart2_cts-0 {
1637                                                 atmel,pins = <AT91_PIOB 3 AT91_PERIPH_B AT91_PINCTRL_NONE>;     /* conflicts with G0_TXER, ISI_VSYNC */
1638                                         };
1639                                 };
1640
1641                                 usart3 {
1642                                         pinctrl_usart3: usart3-0 {
1643                                                 atmel,pins =
1644                                                         <AT91_PIOE 16 AT91_PERIPH_B AT91_PINCTRL_NONE           /* RXD */
1645                                                          AT91_PIOE 17 AT91_PERIPH_B AT91_PINCTRL_PULL_UP        /* TXD */
1646                                                         >;
1647                                         };
1648                                 };
1649
1650                                 usart4 {
1651                                         pinctrl_usart4: usart4-0 {
1652                                                 atmel,pins =
1653                                                         <AT91_PIOE 26 AT91_PERIPH_B AT91_PINCTRL_NONE           /* RXD */
1654                                                          AT91_PIOE 27 AT91_PERIPH_B AT91_PINCTRL_PULL_UP        /* TXD */
1655                                                         >;
1656                                         };
1657                                         pinctrl_usart4_rts: usart4_rts-0 {
1658                                                 atmel,pins = <AT91_PIOE 28 AT91_PERIPH_B AT91_PINCTRL_NONE>;    /* conflicts with NWAIT, A19 */
1659                                         };
1660                                         pinctrl_usart4_cts: usart4_cts-0 {
1661                                                 atmel,pins = <AT91_PIOE 0 AT91_PERIPH_C AT91_PINCTRL_NONE>;     /* conflicts with A0/NBS0, MCI0_CDB */
1662                                         };
1663                                 };
1664                         };
1665
1666                         aic: interrupt-controller@fc06e000 {
1667                                 #interrupt-cells = <3>;
1668                                 compatible = "atmel,sama5d4-aic";
1669                                 interrupt-controller;
1670                                 reg = <0xfc06e000 0x200>;
1671                                 atmel,external-irqs = <56>;
1672                         };
1673                 };
1674         };
1675 };