kernel/arch/arm/boot/dts/rk3288.dtsi

   1 /*
   2  * This program is free software; you can redistribute it and/or modify
   3  * it under the terms of the GNU General Public License as published by
   4  * the Free Software Foundation; either version 2 of the License, or
   5  * (at your option) any later version.
   6  *
   7  * This program is distributed in the hope that it will be useful,
   8  * but WITHOUT ANY WARRANTY; without even the implied warranty of
   9  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  10  * GNU General Public License for more details.
  11  */
  12
  13 #include <dt-bindings/gpio/gpio.h>
  14 #include <dt-bindings/interrupt-controller/irq.h>
  15 #include <dt-bindings/interrupt-controller/arm-gic.h>
  16 #include <dt-bindings/pinctrl/rockchip.h>
  17 #include <dt-bindings/clock/rk3288-cru.h>
  18 #include <dt-bindings/thermal/thermal.h>
  19 #include "skeleton.dtsi"
  20
  21 / {
  22         compatible = "rockchip,rk3288";
  23
  24         interrupt-parent = <&gic>;
  25
  26         aliases {
  27                 i2c0 = &i2c0;
  28                 i2c1 = &i2c1;
  29                 i2c2 = &i2c2;
  30                 i2c3 = &i2c3;
  31                 i2c4 = &i2c4;
  32                 i2c5 = &i2c5;
  33                 mshc0 = &emmc;
  34                 mshc1 = &sdmmc;
  35                 mshc2 = &sdio0;
  36                 mshc3 = &sdio1;
  37                 serial0 = &uart0;
  38                 serial1 = &uart1;
  39                 serial2 = &uart2;
  40                 serial3 = &uart3;
  41                 serial4 = &uart4;
  42                 spi0 = &spi0;
  43                 spi1 = &spi1;
  44                 spi2 = &spi2;
  45         };
  46
  47         cpus {
  48                 #address-cells = <1>;
  49                 #size-cells = <0>;
  50                 enable-method = "rockchip,rk3066-smp";
  51                 rockchip,pmu = <&pmu>;
  52
  53                 cpu0: cpu@500 {
  54                         device_type = "cpu";
  55                         compatible = "arm,cortex-a12";
  56                         reg = <0x500>;
  57                         resets = <&cru SRST_CORE0>;
  58                         operating-points = <
  59                                 /* KHz    uV */
  60                                 1608000 1350000
  61                                 1512000 1300000
  62                                 1416000 1200000
  63                                 1200000 1100000
  64                                 1008000 1050000
  65                                  816000 1000000
  66                                  696000  950000
  67                                  600000  900000
  68                                  408000  900000
  69                                  312000  900000
  70                                  216000  900000
  71                                  126000  900000
  72                         >;
  73                         #cooling-cells = <2>; /* min followed by max */
  74                         clock-latency = <40000>;
  75                         clocks = <&cru ARMCLK>;
  76                 };
  77                 cpu@501 {
  78                         device_type = "cpu";
  79                         compatible = "arm,cortex-a12";
  80                         reg = <0x501>;
  81                         resets = <&cru SRST_CORE1>;
  82                 };
  83                 cpu@502 {
  84                         device_type = "cpu";
  85                         compatible = "arm,cortex-a12";
  86                         reg = <0x502>;
  87                         resets = <&cru SRST_CORE2>;
  88                 };
  89                 cpu@503 {
  90                         device_type = "cpu";
  91                         compatible = "arm,cortex-a12";
  92                         reg = <0x503>;
  93                         resets = <&cru SRST_CORE3>;
  94                 };
  95         };
  96
  97         amba {
  98                 compatible = "arm,amba-bus";
  99                 #address-cells = <1>;
 100                 #size-cells = <1>;
 101                 ranges;
 102
 103                 dmac_peri: dma-controller@ff250000 {
 104                         compatible = "arm,pl330", "arm,primecell";
 105                         reg = <0xff250000 0x4000>;
 106                         interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
 107                                      <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 108                         #dma-cells = <1>;
 109                         clocks = <&cru ACLK_DMAC2>;
 110                         clock-names = "apb_pclk";
 111                 };
 112
 113                 dmac_bus_ns: dma-controller@ff600000 {
 114                         compatible = "arm,pl330", "arm,primecell";
 115                         reg = <0xff600000 0x4000>;
 116                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 117                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 118                         #dma-cells = <1>;
 119                         clocks = <&cru ACLK_DMAC1>;
 120                         clock-names = "apb_pclk";
 121                         status = "disabled";
 122                 };
 123
 124                 dmac_bus_s: dma-controller@ffb20000 {
 125                         compatible = "arm,pl330", "arm,primecell";
 126                         reg = <0xffb20000 0x4000>;
 127                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 128                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 129                         #dma-cells = <1>;
 130                         clocks = <&cru ACLK_DMAC1>;
 131                         clock-names = "apb_pclk";
 132                 };
 133         };
 134
 135         xin24m: oscillator {
 136                 compatible = "fixed-clock";
 137                 clock-frequency = <24000000>;
 138                 clock-output-names = "xin24m";
 139                 #clock-cells = <0>;
 140         };
 141
 142         timer {
 143                 compatible = "arm,armv7-timer";
 144                 arm,cpu-registers-not-fw-configured;
 145                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 146                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 147                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 148                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 149                 clock-frequency = <24000000>;
 150         };
 151
 152         timer: timer@ff810000 {
 153                 compatible = "rockchip,rk3288-timer";
 154                 reg = <0xff810000 0x20>;
 155                 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
 156                 clocks = <&xin24m>, <&cru PCLK_TIMER>;
 157                 clock-names = "timer", "pclk";
 158         };
 159
 160         display-subsystem {
 161                 compatible = "rockchip,display-subsystem";
 162                 ports = <&vopl_out>, <&vopb_out>;
 163         };
 164
 165         sdmmc: dwmmc@ff0c0000 {
 166                 compatible = "rockchip,rk3288-dw-mshc";
 167                 clock-freq-min-max = <400000 150000000>;
 168                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
 169                 clock-names = "biu", "ciu";
 170                 fifo-depth = <0x100>;
 171                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 172                 reg = <0xff0c0000 0x4000>;
 173                 status = "disabled";
 174         };
 175
 176         sdio0: dwmmc@ff0d0000 {
 177                 compatible = "rockchip,rk3288-dw-mshc";
 178                 clock-freq-min-max = <400000 150000000>;
 179                 clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>;
 180                 clock-names = "biu", "ciu";
 181                 fifo-depth = <0x100>;
 182                 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 183                 reg = <0xff0d0000 0x4000>;
 184                 status = "disabled";
 185         };
 186
 187         sdio1: dwmmc@ff0e0000 {
 188                 compatible = "rockchip,rk3288-dw-mshc";
 189                 clock-freq-min-max = <400000 150000000>;
 190                 clocks = <&cru HCLK_SDIO1>, <&cru SCLK_SDIO1>;
 191                 clock-names = "biu", "ciu";
 192                 fifo-depth = <0x100>;
 193                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 194                 reg = <0xff0e0000 0x4000>;
 195                 status = "disabled";
 196         };
 197
 198         emmc: dwmmc@ff0f0000 {
 199                 compatible = "rockchip,rk3288-dw-mshc";
 200                 clock-freq-min-max = <400000 150000000>;
 201                 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>;
 202                 clock-names = "biu", "ciu";
 203                 fifo-depth = <0x100>;
 204                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 205                 reg = <0xff0f0000 0x4000>;
 206                 status = "disabled";
 207         };
 208
 209         saradc: saradc@ff100000 {
 210                 compatible = "rockchip,saradc";
 211                 reg = <0xff100000 0x100>;
 212                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 213                 #io-channel-cells = <1>;
 214                 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
 215                 clock-names = "saradc", "apb_pclk";
 216                 status = "disabled";
 217         };
 218
 219         spi0: spi@ff110000 {
 220                 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
 221                 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
 222                 clock-names = "spiclk", "apb_pclk";
 223                 dmas = <&dmac_peri 11>, <&dmac_peri 12>;
 224                 dma-names = "tx", "rx";
 225                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 226                 pinctrl-names = "default";
 227                 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
 228                 reg = <0xff110000 0x1000>;
 229                 #address-cells = <1>;
 230                 #size-cells = <0>;
 231                 status = "disabled";
 232         };
 233
 234         spi1: spi@ff120000 {
 235                 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
 236                 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
 237                 clock-names = "spiclk", "apb_pclk";
 238                 dmas = <&dmac_peri 13>, <&dmac_peri 14>;
 239                 dma-names = "tx", "rx";
 240                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 241                 pinctrl-names = "default";
 242                 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
 243                 reg = <0xff120000 0x1000>;
 244                 #address-cells = <1>;
 245                 #size-cells = <0>;
 246                 status = "disabled";
 247         };
 248
 249         spi2: spi@ff130000 {
 250                 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
 251                 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
 252                 clock-names = "spiclk", "apb_pclk";
 253                 dmas = <&dmac_peri 15>, <&dmac_peri 16>;
 254                 dma-names = "tx", "rx";
 255                 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 256                 pinctrl-names = "default";
 257                 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
 258                 reg = <0xff130000 0x1000>;
 259                 #address-cells = <1>;
 260                 #size-cells = <0>;
 261                 status = "disabled";
 262         };
 263
 264         i2c1: i2c@ff140000 {
 265                 compatible = "rockchip,rk3288-i2c";
 266                 reg = <0xff140000 0x1000>;
 267                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 268                 #address-cells = <1>;
 269                 #size-cells = <0>;
 270                 clock-names = "i2c";
 271                 clocks = <&cru PCLK_I2C1>;
 272                 pinctrl-names = "default";
 273                 pinctrl-0 = <&i2c1_xfer>;
 274                 status = "disabled";
 275         };
 276
 277         i2c3: i2c@ff150000 {
 278                 compatible = "rockchip,rk3288-i2c";
 279                 reg = <0xff150000 0x1000>;
 280                 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
 281                 #address-cells = <1>;
 282                 #size-cells = <0>;
 283                 clock-names = "i2c";
 284                 clocks = <&cru PCLK_I2C3>;
 285                 pinctrl-names = "default";
 286                 pinctrl-0 = <&i2c3_xfer>;
 287                 status = "disabled";
 288         };
 289
 290         i2c4: i2c@ff160000 {
 291                 compatible = "rockchip,rk3288-i2c";
 292                 reg = <0xff160000 0x1000>;
 293                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 294                 #address-cells = <1>;
 295                 #size-cells = <0>;
 296                 clock-names = "i2c";
 297                 clocks = <&cru PCLK_I2C4>;
 298                 pinctrl-names = "default";
 299                 pinctrl-0 = <&i2c4_xfer>;
 300                 status = "disabled";
 301         };
 302
 303         i2c5: i2c@ff170000 {
 304                 compatible = "rockchip,rk3288-i2c";
 305                 reg = <0xff170000 0x1000>;
 306                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 307                 #address-cells = <1>;
 308                 #size-cells = <0>;
 309                 clock-names = "i2c";
 310                 clocks = <&cru PCLK_I2C5>;
 311                 pinctrl-names = "default";
 312                 pinctrl-0 = <&i2c5_xfer>;
 313                 status = "disabled";
 314         };
 315
 316         uart0: serial@ff180000 {
 317                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 318                 reg = <0xff180000 0x100>;
 319                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 320                 reg-shift = <2>;
 321                 reg-io-width = <4>;
 322                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 323                 clock-names = "baudclk", "apb_pclk";
 324                 pinctrl-names = "default";
 325                 pinctrl-0 = <&uart0_xfer>;
 326                 status = "disabled";
 327         };
 328
 329         uart1: serial@ff190000 {
 330                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 331                 reg = <0xff190000 0x100>;
 332                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 333                 reg-shift = <2>;
 334                 reg-io-width = <4>;
 335                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
 336                 clock-names = "baudclk", "apb_pclk";
 337                 pinctrl-names = "default";
 338                 pinctrl-0 = <&uart1_xfer>;
 339                 status = "disabled";
 340         };
 341
 342         uart2: serial@ff690000 {
 343                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 344                 reg = <0xff690000 0x100>;
 345                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 346                 reg-shift = <2>;
 347                 reg-io-width = <4>;
 348                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 349                 clock-names = "baudclk", "apb_pclk";
 350                 pinctrl-names = "default";
 351                 pinctrl-0 = <&uart2_xfer>;
 352                 status = "disabled";
 353         };
 354
 355         uart3: serial@ff1b0000 {
 356                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 357                 reg = <0xff1b0000 0x100>;
 358                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
 359                 reg-shift = <2>;
 360                 reg-io-width = <4>;
 361                 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
 362                 clock-names = "baudclk", "apb_pclk";
 363                 pinctrl-names = "default";
 364                 pinctrl-0 = <&uart3_xfer>;
 365                 status = "disabled";
 366         };
 367
 368         uart4: serial@ff1c0000 {
 369                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 370                 reg = <0xff1c0000 0x100>;
 371                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 372                 reg-shift = <2>;
 373                 reg-io-width = <4>;
 374                 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
 375                 clock-names = "baudclk", "apb_pclk";
 376                 pinctrl-names = "default";
 377                 pinctrl-0 = <&uart4_xfer>;
 378                 status = "disabled";
 379         };
 380
 381         thermal-zones {
 382                 #include "rk3288-thermal.dtsi"
 383         };
 384
 385         tsadc: tsadc@ff280000 {
 386                 compatible = "rockchip,rk3288-tsadc";
 387                 reg = <0xff280000 0x100>;
 388                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 389                 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
 390                 clock-names = "tsadc", "apb_pclk";
 391                 resets = <&cru SRST_TSADC>;
 392                 reset-names = "tsadc-apb";
 393                 pinctrl-names = "default";
 394                 pinctrl-0 = <&otp_out>;
 395                 #thermal-sensor-cells = <1>;
 396                 rockchip,hw-tshut-temp = <95000>;
 397                 status = "disabled";
 398         };
 399
 400         gmac: ethernet@ff290000 {
 401                 compatible = "rockchip,rk3288-gmac";
 402                 reg = <0xff290000 0x10000>;
 403                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
 404                 interrupt-names = "macirq";
 405                 rockchip,grf = <&grf>;
 406                 clocks = <&cru SCLK_MAC>,
 407                         <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>,
 408                         <&cru SCLK_MACREF>, <&cru SCLK_MACREF_OUT>,
 409                         <&cru ACLK_GMAC>, <&cru PCLK_GMAC>;
 410                 clock-names = "stmmaceth",
 411                         "mac_clk_rx", "mac_clk_tx",
 412                         "clk_mac_ref", "clk_mac_refout",
 413                         "aclk_mac", "pclk_mac";
 414                 status = "disabled";
 415         };
 416
 417         usb_host0_ehci: usb@ff500000 {
 418                 compatible = "generic-ehci";
 419                 reg = <0xff500000 0x100>;
 420                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 421                 clocks = <&cru HCLK_USBHOST0>;
 422                 clock-names = "usbhost";
 423                 phys = <&usbphy1>;
 424                 phy-names = "usb";
 425                 status = "disabled";
 426         };
 427
 428         /* NOTE: ohci@ff520000 doesn't actually work on hardware */
 429
 430         usb_host1: usb@ff540000 {
 431                 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
 432                                 "snps,dwc2";
 433                 reg = <0xff540000 0x40000>;
 434                 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 435                 clocks = <&cru HCLK_USBHOST1>;
 436                 clock-names = "otg";
 437                 phys = <&usbphy2>;
 438                 phy-names = "usb2-phy";
 439                 status = "disabled";
 440         };
 441
 442         usb_otg: usb@ff580000 {
 443                 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
 444                                 "snps,dwc2";
 445                 reg = <0xff580000 0x40000>;
 446                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 447                 clocks = <&cru HCLK_OTG0>;
 448                 clock-names = "otg";
 449                 phys = <&usbphy0>;
 450                 phy-names = "usb2-phy";
 451                 status = "disabled";
 452         };
 453
 454         usb_hsic: usb@ff5c0000 {
 455                 compatible = "generic-ehci";
 456                 reg = <0xff5c0000 0x100>;
 457                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 458                 clocks = <&cru HCLK_HSIC>;
 459                 clock-names = "usbhost";
 460                 status = "disabled";
 461         };
 462
 463         i2c0: i2c@ff650000 {
 464                 compatible = "rockchip,rk3288-i2c";
 465                 reg = <0xff650000 0x1000>;
 466                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 467                 #address-cells = <1>;
 468                 #size-cells = <0>;
 469                 clock-names = "i2c";
 470                 clocks = <&cru PCLK_I2C0>;
 471                 pinctrl-names = "default";
 472                 pinctrl-0 = <&i2c0_xfer>;
 473                 status = "disabled";
 474         };
 475
 476         i2c2: i2c@ff660000 {
 477                 compatible = "rockchip,rk3288-i2c";
 478                 reg = <0xff660000 0x1000>;
 479                 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 480                 #address-cells = <1>;
 481                 #size-cells = <0>;
 482                 clock-names = "i2c";
 483                 clocks = <&cru PCLK_I2C2>;
 484                 pinctrl-names = "default";
 485                 pinctrl-0 = <&i2c2_xfer>;
 486                 status = "disabled";
 487         };
 488
 489         pwm0: pwm@ff680000 {
 490                 compatible = "rockchip,rk3288-pwm";
 491                 reg = <0xff680000 0x10>;
 492                 #pwm-cells = <3>;
 493                 pinctrl-names = "default";
 494                 pinctrl-0 = <&pwm0_pin>;
 495                 clocks = <&cru PCLK_PWM>;
 496                 clock-names = "pwm";
 497                 status = "disabled";
 498         };
 499
 500         pwm1: pwm@ff680010 {
 501                 compatible = "rockchip,rk3288-pwm";
 502                 reg = <0xff680010 0x10>;
 503                 #pwm-cells = <3>;
 504                 pinctrl-names = "default";
 505                 pinctrl-0 = <&pwm1_pin>;
 506                 clocks = <&cru PCLK_PWM>;
 507                 clock-names = "pwm";
 508                 status = "disabled";
 509         };
 510
 511         pwm2: pwm@ff680020 {
 512                 compatible = "rockchip,rk3288-pwm";
 513                 reg = <0xff680020 0x10>;
 514                 #pwm-cells = <3>;
 515                 pinctrl-names = "default";
 516                 pinctrl-0 = <&pwm2_pin>;
 517                 clocks = <&cru PCLK_PWM>;
 518                 clock-names = "pwm";
 519                 status = "disabled";
 520         };
 521
 522         pwm3: pwm@ff680030 {
 523                 compatible = "rockchip,rk3288-pwm";
 524                 reg = <0xff680030 0x10>;
 525                 #pwm-cells = <2>;
 526                 pinctrl-names = "default";
 527                 pinctrl-0 = <&pwm3_pin>;
 528                 clocks = <&cru PCLK_PWM>;
 529                 clock-names = "pwm";
 530                 status = "disabled";
 531         };
 532
 533         bus_intmem@ff700000 {
 534                 compatible = "mmio-sram";
 535                 reg = <0xff700000 0x18000>;
 536                 #address-cells = <1>;
 537                 #size-cells = <1>;
 538                 ranges = <0 0xff700000 0x18000>;
 539                 smp-sram@0 {
 540                         compatible = "rockchip,rk3066-smp-sram";
 541                         reg = <0x00 0x10>;
 542                 };
 543         };
 544
 545         sram@ff720000 {
 546                 compatible = "rockchip,rk3288-pmu-sram", "mmio-sram";
 547                 reg = <0xff720000 0x1000>;
 548         };
 549
 550         pmu: power-management@ff730000 {
 551                 compatible = "rockchip,rk3288-pmu", "syscon";
 552                 reg = <0xff730000 0x100>;
 553         };
 554
 555         sgrf: syscon@ff740000 {
 556                 compatible = "rockchip,rk3288-sgrf", "syscon";
 557                 reg = <0xff740000 0x1000>;
 558         };
 559
 560         cru: clock-controller@ff760000 {
 561                 compatible = "rockchip,rk3288-cru";
 562                 reg = <0xff760000 0x1000>;
 563                 rockchip,grf = <&grf>;
 564                 #clock-cells = <1>;
 565                 #reset-cells = <1>;
 566                 assigned-clocks = <&cru PLL_GPLL>, <&cru PLL_CPLL>,
 567                                   <&cru PLL_NPLL>, <&cru ACLK_CPU>,
 568                                   <&cru HCLK_CPU>, <&cru PCLK_CPU>,
 569                                   <&cru ACLK_PERI>, <&cru HCLK_PERI>,
 570                                   <&cru PCLK_PERI>;
 571                 assigned-clock-rates = <594000000>, <400000000>,
 572                                        <500000000>, <300000000>,
 573                                        <150000000>, <75000000>,
 574                                        <300000000>, <150000000>,
 575                                        <75000000>;
 576         };
 577
 578         grf: syscon@ff770000 {
 579                 compatible = "rockchip,rk3288-grf", "syscon";
 580                 reg = <0xff770000 0x1000>;
 581         };
 582
 583         wdt: watchdog@ff800000 {
 584                 compatible = "rockchip,rk3288-wdt", "snps,dw-wdt";
 585                 reg = <0xff800000 0x100>;
 586                 clocks = <&cru PCLK_WDT>;
 587                 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
 588                 status = "disabled";
 589         };
 590
 591         i2s: i2s@ff890000 {
 592                 compatible = "rockchip,rk3288-i2s", "rockchip,rk3066-i2s";
 593                 reg = <0xff890000 0x10000>;
 594                 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
 595                 #address-cells = <1>;
 596                 #size-cells = <0>;
 597                 dmas = <&dmac_bus_s 0>, <&dmac_bus_s 1>;
 598                 dma-names = "tx", "rx";
 599                 clock-names = "i2s_hclk", "i2s_clk";
 600                 clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>;
 601                 pinctrl-names = "default";
 602                 pinctrl-0 = <&i2s0_bus>;
 603                 status = "disabled";
 604         };
 605
 606         vopb: vop@ff930000 {
 607                 compatible = "rockchip,rk3288-vop";
 608                 reg = <0xff930000 0x19c>;
 609                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 610                 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
 611                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
 612                 resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>;
 613                 reset-names = "axi", "ahb", "dclk";
 614                 iommus = <&vopb_mmu>;
 615                 status = "disabled";
 616
 617                 vopb_out: port {
 618                         #address-cells = <1>;
 619                         #size-cells = <0>;
 620
 621                         vopb_out_hdmi: endpoint@0 {
 622                                 reg = <0>;
 623                                 remote-endpoint = <&hdmi_in_vopb>;
 624                         };
 625                 };
 626         };
 627
 628         vopb_mmu: iommu@ff930300 {
 629                 compatible = "rockchip,iommu";
 630                 reg = <0xff930300 0x100>;
 631                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 632                 interrupt-names = "vopb_mmu";
 633                 #iommu-cells = <0>;
 634                 status = "disabled";
 635         };
 636
 637         vopl: vop@ff940000 {
 638                 compatible = "rockchip,rk3288-vop";
 639                 reg = <0xff940000 0x19c>;
 640                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 641                 clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
 642                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
 643                 resets = <&cru SRST_LCDC1_AXI>, <&cru SRST_LCDC1_AHB>, <&cru SRST_LCDC1_DCLK>;
 644                 reset-names = "axi", "ahb", "dclk";
 645                 iommus = <&vopl_mmu>;
 646                 status = "disabled";
 647
 648                 vopl_out: port {
 649                         #address-cells = <1>;
 650                         #size-cells = <0>;
 651
 652                         vopl_out_hdmi: endpoint@0 {
 653                                 reg = <0>;
 654                                 remote-endpoint = <&hdmi_in_vopl>;
 655                         };
 656                 };
 657         };
 658
 659         vopl_mmu: iommu@ff940300 {
 660                 compatible = "rockchip,iommu";
 661                 reg = <0xff940300 0x100>;
 662                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 663                 interrupt-names = "vopl_mmu";
 664                 #iommu-cells = <0>;
 665                 status = "disabled";
 666         };
 667
 668         hdmi: hdmi@ff980000 {
 669                 compatible = "rockchip,rk3288-dw-hdmi";
 670                 reg = <0xff980000 0x20000>;
 671                 reg-io-width = <4>;
 672                 rockchip,grf = <&grf>;
 673                 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
 674                 clocks = <&cru  PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>;
 675                 clock-names = "iahb", "isfr";
 676                 status = "disabled";
 677
 678                 ports {
 679                         hdmi_in: port {
 680                                 #address-cells = <1>;
 681                                 #size-cells = <0>;
 682                                 hdmi_in_vopb: endpoint@0 {
 683                                         reg = <0>;
 684                                         remote-endpoint = <&vopb_out_hdmi>;
 685                                 };
 686                                 hdmi_in_vopl: endpoint@1 {
 687                                         reg = <1>;
 688                                         remote-endpoint = <&vopl_out_hdmi>;
 689                                 };
 690                         };
 691                 };
 692         };
 693
 694         gic: interrupt-controller@ffc01000 {
 695                 compatible = "arm,gic-400";
 696                 interrupt-controller;
 697                 #interrupt-cells = <3>;
 698                 #address-cells = <0>;
 699
 700                 reg = <0xffc01000 0x1000>,
 701                       <0xffc02000 0x1000>,
 702                       <0xffc04000 0x2000>,
 703                       <0xffc06000 0x2000>;
 704                 interrupts = <GIC_PPI 9 0xf04>;
 705         };
 706
 707         usbphy: phy {
 708                 compatible = "rockchip,rk3288-usb-phy";
 709                 rockchip,grf = <&grf>;
 710                 #address-cells = <1>;
 711                 #size-cells = <0>;
 712                 status = "disabled";
 713
 714                 usbphy0: usb-phy0 {
 715                         #phy-cells = <0>;
 716                         reg = <0x320>;
 717                         clocks = <&cru SCLK_OTGPHY0>;
 718                         clock-names = "phyclk";
 719                 };
 720
 721                 usbphy1: usb-phy1 {
 722                         #phy-cells = <0>;
 723                         reg = <0x334>;
 724                         clocks = <&cru SCLK_OTGPHY1>;
 725                         clock-names = "phyclk";
 726                 };
 727
 728                 usbphy2: usb-phy2 {
 729                         #phy-cells = <0>;
 730                         reg = <0x348>;
 731                         clocks = <&cru SCLK_OTGPHY2>;
 732                         clock-names = "phyclk";
 733                 };
 734         };
 735
 736         pinctrl: pinctrl {
 737                 compatible = "rockchip,rk3288-pinctrl";
 738                 rockchip,grf = <&grf>;
 739                 rockchip,pmu = <&pmu>;
 740                 #address-cells = <1>;
 741                 #size-cells = <1>;
 742                 ranges;
 743
 744                 gpio0: gpio0@ff750000 {
 745                         compatible = "rockchip,gpio-bank";
 746                         reg =   <0xff750000 0x100>;
 747                         interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
 748                         clocks = <&cru PCLK_GPIO0>;
 749
 750                         gpio-controller;
 751                         #gpio-cells = <2>;
 752
 753                         interrupt-controller;
 754                         #interrupt-cells = <2>;
 755                 };
 756
 757                 gpio1: gpio1@ff780000 {
 758                         compatible = "rockchip,gpio-bank";
 759                         reg = <0xff780000 0x100>;
 760                         interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
 761                         clocks = <&cru PCLK_GPIO1>;
 762
 763                         gpio-controller;
 764                         #gpio-cells = <2>;
 765
 766                         interrupt-controller;
 767                         #interrupt-cells = <2>;
 768                 };
 769
 770                 gpio2: gpio2@ff790000 {
 771                         compatible = "rockchip,gpio-bank";
 772                         reg = <0xff790000 0x100>;
 773                         interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
 774                         clocks = <&cru PCLK_GPIO2>;
 775
 776                         gpio-controller;
 777                         #gpio-cells = <2>;
 778
 779                         interrupt-controller;
 780                         #interrupt-cells = <2>;
 781                 };
 782
 783                 gpio3: gpio3@ff7a0000 {
 784                         compatible = "rockchip,gpio-bank";
 785                         reg = <0xff7a0000 0x100>;
 786                         interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
 787                         clocks = <&cru PCLK_GPIO3>;
 788
 789                         gpio-controller;
 790                         #gpio-cells = <2>;
 791
 792                         interrupt-controller;
 793                         #interrupt-cells = <2>;
 794                 };
 795
 796                 gpio4: gpio4@ff7b0000 {
 797                         compatible = "rockchip,gpio-bank";
 798                         reg = <0xff7b0000 0x100>;
 799                         interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
 800                         clocks = <&cru PCLK_GPIO4>;
 801
 802                         gpio-controller;
 803                         #gpio-cells = <2>;
 804
 805                         interrupt-controller;
 806                         #interrupt-cells = <2>;
 807                 };
 808
 809                 gpio5: gpio5@ff7c0000 {
 810                         compatible = "rockchip,gpio-bank";
 811                         reg = <0xff7c0000 0x100>;
 812                         interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 813                         clocks = <&cru PCLK_GPIO5>;
 814
 815                         gpio-controller;
 816                         #gpio-cells = <2>;
 817
 818                         interrupt-controller;
 819                         #interrupt-cells = <2>;
 820                 };
 821
 822                 gpio6: gpio6@ff7d0000 {
 823                         compatible = "rockchip,gpio-bank";
 824                         reg = <0xff7d0000 0x100>;
 825                         interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
 826                         clocks = <&cru PCLK_GPIO6>;
 827
 828                         gpio-controller;
 829                         #gpio-cells = <2>;
 830
 831                         interrupt-controller;
 832                         #interrupt-cells = <2>;
 833                 };
 834
 835                 gpio7: gpio7@ff7e0000 {
 836                         compatible = "rockchip,gpio-bank";
 837                         reg = <0xff7e0000 0x100>;
 838                         interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
 839                         clocks = <&cru PCLK_GPIO7>;
 840
 841                         gpio-controller;
 842                         #gpio-cells = <2>;
 843
 844                         interrupt-controller;
 845                         #interrupt-cells = <2>;
 846                 };
 847
 848                 gpio8: gpio8@ff7f0000 {
 849                         compatible = "rockchip,gpio-bank";
 850                         reg = <0xff7f0000 0x100>;
 851                         interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
 852                         clocks = <&cru PCLK_GPIO8>;
 853
 854                         gpio-controller;
 855                         #gpio-cells = <2>;
 856
 857                         interrupt-controller;
 858                         #interrupt-cells = <2>;
 859                 };
 860
 861                 pcfg_pull_up: pcfg-pull-up {
 862                         bias-pull-up;
 863                 };
 864
 865                 pcfg_pull_down: pcfg-pull-down {
 866                         bias-pull-down;
 867                 };
 868
 869                 pcfg_pull_none: pcfg-pull-none {
 870                         bias-disable;
 871                 };
 872
 873                 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
 874                         bias-disable;
 875                         drive-strength = <12>;
 876                 };
 877
 878                 sleep {
 879                         global_pwroff: global-pwroff {
 880                                 rockchip,pins = <0 0 RK_FUNC_1 &pcfg_pull_none>;
 881                         };
 882
 883                         ddrio_pwroff: ddrio-pwroff {
 884                                 rockchip,pins = <0 1 RK_FUNC_1 &pcfg_pull_none>;
 885                         };
 886
 887                         ddr0_retention: ddr0-retention {
 888                                 rockchip,pins = <0 2 RK_FUNC_1 &pcfg_pull_up>;
 889                         };
 890
 891                         ddr1_retention: ddr1-retention {
 892                                 rockchip,pins = <0 3 RK_FUNC_1 &pcfg_pull_up>;
 893                         };
 894                 };
 895
 896                 i2c0 {
 897                         i2c0_xfer: i2c0-xfer {
 898                                 rockchip,pins = <0 15 RK_FUNC_1 &pcfg_pull_none>,
 899                                                 <0 16 RK_FUNC_1 &pcfg_pull_none>;
 900                         };
 901                 };
 902
 903                 i2c1 {
 904                         i2c1_xfer: i2c1-xfer {
 905                                 rockchip,pins = <8 4 RK_FUNC_1 &pcfg_pull_none>,
 906                                                 <8 5 RK_FUNC_1 &pcfg_pull_none>;
 907                         };
 908                 };
 909
 910                 i2c2 {
 911                         i2c2_xfer: i2c2-xfer {
 912                                 rockchip,pins = <6 9 RK_FUNC_1 &pcfg_pull_none>,
 913                                                 <6 10 RK_FUNC_1 &pcfg_pull_none>;
 914                         };
 915                 };
 916
 917                 i2c3 {
 918                         i2c3_xfer: i2c3-xfer {
 919                                 rockchip,pins = <2 16 RK_FUNC_1 &pcfg_pull_none>,
 920                                                 <2 17 RK_FUNC_1 &pcfg_pull_none>;
 921                         };
 922                 };
 923
 924                 i2c4 {
 925                         i2c4_xfer: i2c4-xfer {
 926                                 rockchip,pins = <7 17 RK_FUNC_1 &pcfg_pull_none>,
 927                                                 <7 18 RK_FUNC_1 &pcfg_pull_none>;
 928                         };
 929                 };
 930
 931                 i2c5 {
 932                         i2c5_xfer: i2c5-xfer {
 933                                 rockchip,pins = <7 19 RK_FUNC_1 &pcfg_pull_none>,
 934                                                 <7 20 RK_FUNC_1 &pcfg_pull_none>;
 935                         };
 936                 };
 937
 938                 i2s0 {
 939                         i2s0_bus: i2s0-bus {
 940                                 rockchip,pins = <6 0 RK_FUNC_1 &pcfg_pull_none>,
 941                                                 <6 1 RK_FUNC_1 &pcfg_pull_none>,
 942                                                 <6 2 RK_FUNC_1 &pcfg_pull_none>,
 943                                                 <6 3 RK_FUNC_1 &pcfg_pull_none>,
 944                                                 <6 4 RK_FUNC_1 &pcfg_pull_none>,
 945                                                 <6 8 RK_FUNC_1 &pcfg_pull_none>;
 946                         };
 947                 };
 948
 949                 sdmmc {
 950                         sdmmc_clk: sdmmc-clk {
 951                                 rockchip,pins = <6 20 RK_FUNC_1 &pcfg_pull_none>;
 952                         };
 953
 954                         sdmmc_cmd: sdmmc-cmd {
 955                                 rockchip,pins = <6 21 RK_FUNC_1 &pcfg_pull_up>;
 956                         };
 957
 958                         sdmmc_cd: sdmcc-cd {
 959                                 rockchip,pins = <6 22 RK_FUNC_1 &pcfg_pull_up>;
 960                         };
 961
 962                         sdmmc_bus1: sdmmc-bus1 {
 963                                 rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>;
 964                         };
 965
 966                         sdmmc_bus4: sdmmc-bus4 {
 967                                 rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>,
 968                                                 <6 17 RK_FUNC_1 &pcfg_pull_up>,
 969                                                 <6 18 RK_FUNC_1 &pcfg_pull_up>,
 970                                                 <6 19 RK_FUNC_1 &pcfg_pull_up>;
 971                         };
 972                 };
 973
 974                 sdio0 {
 975                         sdio0_bus1: sdio0-bus1 {
 976                                 rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>;
 977                         };
 978
 979                         sdio0_bus4: sdio0-bus4 {
 980                                 rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>,
 981                                                 <4 21 RK_FUNC_1 &pcfg_pull_up>,
 982                                                 <4 22 RK_FUNC_1 &pcfg_pull_up>,
 983                                                 <4 23 RK_FUNC_1 &pcfg_pull_up>;
 984                         };
 985
 986                         sdio0_cmd: sdio0-cmd {
 987                                 rockchip,pins = <4 24 RK_FUNC_1 &pcfg_pull_up>;
 988                         };
 989
 990                         sdio0_clk: sdio0-clk {
 991                                 rockchip,pins = <4 25 RK_FUNC_1 &pcfg_pull_none>;
 992                         };
 993
 994                         sdio0_cd: sdio0-cd {
 995                                 rockchip,pins = <4 26 RK_FUNC_1 &pcfg_pull_up>;
 996                         };
 997
 998                         sdio0_wp: sdio0-wp {
 999                                 rockchip,pins = <4 27 RK_FUNC_1 &pcfg_pull_up>;
1000                         };
1001
1002                         sdio0_pwr: sdio0-pwr {
1003                                 rockchip,pins = <4 28 RK_FUNC_1 &pcfg_pull_up>;
1004                         };
1005
1006                         sdio0_bkpwr: sdio0-bkpwr {
1007                                 rockchip,pins = <4 29 RK_FUNC_1 &pcfg_pull_up>;
1008                         };
1009
1010                         sdio0_int: sdio0-int {
1011                                 rockchip,pins = <4 30 RK_FUNC_1 &pcfg_pull_up>;
1012                         };
1013                 };
1014
1015                 sdio1 {
1016                         sdio1_bus1: sdio1-bus1 {
1017                                 rockchip,pins = <3 24 4 &pcfg_pull_up>;
1018                         };
1019
1020                         sdio1_bus4: sdio1-bus4 {
1021                                 rockchip,pins = <3 24 4 &pcfg_pull_up>,
1022                                                 <3 25 4 &pcfg_pull_up>,
1023                                                 <3 26 4 &pcfg_pull_up>,
1024                                                 <3 27 4 &pcfg_pull_up>;
1025                         };
1026
1027                         sdio1_cd: sdio1-cd {
1028                                 rockchip,pins = <3 28 4 &pcfg_pull_up>;
1029                         };
1030
1031                         sdio1_wp: sdio1-wp {
1032                                 rockchip,pins = <3 29 4 &pcfg_pull_up>;
1033                         };
1034
1035                         sdio1_bkpwr: sdio1-bkpwr {
1036                                 rockchip,pins = <3 30 4 &pcfg_pull_up>;
1037                         };
1038
1039                         sdio1_int: sdio1-int {
1040                                 rockchip,pins = <3 31 4 &pcfg_pull_up>;
1041                         };
1042
1043                         sdio1_cmd: sdio1-cmd {
1044                                 rockchip,pins = <4 6 4 &pcfg_pull_up>;
1045                         };
1046
1047                         sdio1_clk: sdio1-clk {
1048                                 rockchip,pins = <4 7 4 &pcfg_pull_none>;
1049                         };
1050
1051                         sdio1_pwr: sdio1-pwr {
1052                                 rockchip,pins = <4 9 4 &pcfg_pull_up>;
1053                         };
1054                 };
1055
1056                 emmc {
1057                         emmc_clk: emmc-clk {
1058                                 rockchip,pins = <3 18 RK_FUNC_2 &pcfg_pull_none>;
1059                         };
1060
1061                         emmc_cmd: emmc-cmd {
1062                                 rockchip,pins = <3 16 RK_FUNC_2 &pcfg_pull_up>;
1063                         };
1064
1065                         emmc_pwr: emmc-pwr {
1066                                 rockchip,pins = <3 9 RK_FUNC_2 &pcfg_pull_up>;
1067                         };
1068
1069                         emmc_bus1: emmc-bus1 {
1070                                 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>;
1071                         };
1072
1073                         emmc_bus4: emmc-bus4 {
1074                                 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>,
1075                                                 <3 1 RK_FUNC_2 &pcfg_pull_up>,
1076                                                 <3 2 RK_FUNC_2 &pcfg_pull_up>,
1077                                                 <3 3 RK_FUNC_2 &pcfg_pull_up>;
1078                         };
1079
1080                         emmc_bus8: emmc-bus8 {
1081                                 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>,
1082                                                 <3 1 RK_FUNC_2 &pcfg_pull_up>,
1083                                                 <3 2 RK_FUNC_2 &pcfg_pull_up>,
1084                                                 <3 3 RK_FUNC_2 &pcfg_pull_up>,
1085                                                 <3 4 RK_FUNC_2 &pcfg_pull_up>,
1086                                                 <3 5 RK_FUNC_2 &pcfg_pull_up>,
1087                                                 <3 6 RK_FUNC_2 &pcfg_pull_up>,
1088                                                 <3 7 RK_FUNC_2 &pcfg_pull_up>;
1089                         };
1090                 };
1091
1092                 spi0 {
1093                         spi0_clk: spi0-clk {
1094                                 rockchip,pins = <5 12 RK_FUNC_1 &pcfg_pull_up>;
1095                         };
1096                         spi0_cs0: spi0-cs0 {
1097                                 rockchip,pins = <5 13 RK_FUNC_1 &pcfg_pull_up>;
1098                         };
1099                         spi0_tx: spi0-tx {
1100                                 rockchip,pins = <5 14 RK_FUNC_1 &pcfg_pull_up>;
1101                         };
1102                         spi0_rx: spi0-rx {
1103                                 rockchip,pins = <5 15 RK_FUNC_1 &pcfg_pull_up>;
1104                         };
1105                         spi0_cs1: spi0-cs1 {
1106                                 rockchip,pins = <5 16 RK_FUNC_1 &pcfg_pull_up>;
1107                         };
1108                 };
1109                 spi1 {
1110                         spi1_clk: spi1-clk {
1111                                 rockchip,pins = <7 12 RK_FUNC_2 &pcfg_pull_up>;
1112                         };
1113                         spi1_cs0: spi1-cs0 {
1114                                 rockchip,pins = <7 13 RK_FUNC_2 &pcfg_pull_up>;
1115                         };
1116                         spi1_rx: spi1-rx {
1117                                 rockchip,pins = <7 14 RK_FUNC_2 &pcfg_pull_up>;
1118                         };
1119                         spi1_tx: spi1-tx {
1120                                 rockchip,pins = <7 15 RK_FUNC_2 &pcfg_pull_up>;
1121                         };
1122                 };
1123
1124                 spi2 {
1125                         spi2_cs1: spi2-cs1 {
1126                                 rockchip,pins = <8 3 RK_FUNC_1 &pcfg_pull_up>;
1127                         };
1128                         spi2_clk: spi2-clk {
1129                                 rockchip,pins = <8 6 RK_FUNC_1 &pcfg_pull_up>;
1130                         };
1131                         spi2_cs0: spi2-cs0 {
1132                                 rockchip,pins = <8 7 RK_FUNC_1 &pcfg_pull_up>;
1133                         };
1134                         spi2_rx: spi2-rx {
1135                                 rockchip,pins = <8 8 RK_FUNC_1 &pcfg_pull_up>;
1136                         };
1137                         spi2_tx: spi2-tx {
1138                                 rockchip,pins = <8 9 RK_FUNC_1 &pcfg_pull_up>;
1139                         };
1140                 };
1141
1142                 uart0 {
1143                         uart0_xfer: uart0-xfer {
1144                                 rockchip,pins = <4 16 RK_FUNC_1 &pcfg_pull_up>,
1145                                                 <4 17 RK_FUNC_1 &pcfg_pull_none>;
1146                         };
1147
1148                         uart0_cts: uart0-cts {
1149                                 rockchip,pins = <4 18 RK_FUNC_1 &pcfg_pull_none>;
1150                         };
1151
1152                         uart0_rts: uart0-rts {
1153                                 rockchip,pins = <4 19 RK_FUNC_1 &pcfg_pull_none>;
1154                         };
1155                 };
1156
1157                 uart1 {
1158                         uart1_xfer: uart1-xfer {
1159                                 rockchip,pins = <5 8 RK_FUNC_1 &pcfg_pull_up>,
1160                                                 <5 9 RK_FUNC_1 &pcfg_pull_none>;
1161                         };
1162
1163                         uart1_cts: uart1-cts {
1164                                 rockchip,pins = <5 10 RK_FUNC_1 &pcfg_pull_none>;
1165                         };
1166
1167                         uart1_rts: uart1-rts {
1168                                 rockchip,pins = <5 11 RK_FUNC_1 &pcfg_pull_none>;
1169                         };
1170                 };
1171
1172                 uart2 {
1173                         uart2_xfer: uart2-xfer {
1174                                 rockchip,pins = <7 22 RK_FUNC_1 &pcfg_pull_up>,
1175                                                 <7 23 RK_FUNC_1 &pcfg_pull_none>;
1176                         };
1177                         /* no rts / cts for uart2 */
1178                 };
1179
1180                 uart3 {
1181                         uart3_xfer: uart3-xfer {
1182                                 rockchip,pins = <7 7 RK_FUNC_1 &pcfg_pull_up>,
1183                                                 <7 8 RK_FUNC_1 &pcfg_pull_none>;
1184                         };
1185
1186                         uart3_cts: uart3-cts {
1187                                 rockchip,pins = <7 9 RK_FUNC_1 &pcfg_pull_none>;
1188                         };
1189
1190                         uart3_rts: uart3-rts {
1191                                 rockchip,pins = <7 10 RK_FUNC_1 &pcfg_pull_none>;
1192                         };
1193                 };
1194
1195                 uart4 {
1196                         uart4_xfer: uart4-xfer {
1197                                 rockchip,pins = <5 12 3 &pcfg_pull_up>,
1198                                                 <5 13 3 &pcfg_pull_none>;
1199                         };
1200
1201                         uart4_cts: uart4-cts {
1202                                 rockchip,pins = <5 14 3 &pcfg_pull_none>;
1203                         };
1204
1205                         uart4_rts: uart4-rts {
1206                                 rockchip,pins = <5 15 3 &pcfg_pull_none>;
1207                         };
1208                 };
1209
1210                 tsadc {
1211                         otp_out: otp-out {
1212                                 rockchip,pins = <0 10 RK_FUNC_1 &pcfg_pull_none>;
1213                         };
1214                 };
1215
1216                 pwm0 {
1217                         pwm0_pin: pwm0-pin {
1218                                 rockchip,pins = <7 0 RK_FUNC_1 &pcfg_pull_none>;
1219                         };
1220                 };
1221
1222                 pwm1 {
1223                         pwm1_pin: pwm1-pin {
1224                                 rockchip,pins = <7 1 RK_FUNC_1 &pcfg_pull_none>;
1225                         };
1226                 };
1227
1228                 pwm2 {
1229                         pwm2_pin: pwm2-pin {
1230                                 rockchip,pins = <7 22 3 &pcfg_pull_none>;
1231                         };
1232                 };
1233
1234                 pwm3 {
1235                         pwm3_pin: pwm3-pin {
1236                                 rockchip,pins = <7 23 3 &pcfg_pull_none>;
1237                         };
1238                 };
1239
1240                 gmac {
1241                         rgmii_pins: rgmii-pins {
1242                                 rockchip,pins = <3 30 3 &pcfg_pull_none>,
1243                                                 <3 31 3 &pcfg_pull_none>,
1244                                                 <3 26 3 &pcfg_pull_none>,
1245                                                 <3 27 3 &pcfg_pull_none>,
1246                                                 <3 28 3 &pcfg_pull_none_12ma>,
1247                                                 <3 29 3 &pcfg_pull_none_12ma>,
1248                                                 <3 24 3 &pcfg_pull_none_12ma>,
1249                                                 <3 25 3 &pcfg_pull_none_12ma>,
1250                                                 <4 0 3 &pcfg_pull_none>,
1251                                                 <4 5 3 &pcfg_pull_none>,
1252                                                 <4 6 3 &pcfg_pull_none>,
1253                                                 <4 9 3 &pcfg_pull_none_12ma>,
1254                                                 <4 4 3 &pcfg_pull_none_12ma>,
1255                                                 <4 1 3 &pcfg_pull_none>,
1256                                                 <4 3 3 &pcfg_pull_none>;
1257                         };
1258
1259                         rmii_pins: rmii-pins {
1260                                 rockchip,pins = <3 30 3 &pcfg_pull_none>,
1261                                                 <3 31 3 &pcfg_pull_none>,
1262                                                 <3 28 3 &pcfg_pull_none>,
1263                                                 <3 29 3 &pcfg_pull_none>,
1264                                                 <4 0 3 &pcfg_pull_none>,
1265                                                 <4 5 3 &pcfg_pull_none>,
1266                                                 <4 4 3 &pcfg_pull_none>,
1267                                                 <4 1 3 &pcfg_pull_none>,
1268                                                 <4 2 3 &pcfg_pull_none>,
1269                                                 <4 3 3 &pcfg_pull_none>;
1270                         };
1271                 };
1272         };
1273 };