kernel/arch/arm/boot/dts/r8a7794.dtsi

   1 /*
   2  * Device Tree Source for the r8a7794 SoC
   3  *
   4  * Copyright (C) 2014 Renesas Electronics Corporation
   5  * Copyright (C) 2014 Ulrich Hecht
   6  *
   7  * This file is licensed under the terms of the GNU General Public License
   8  * version 2.  This program is licensed "as is" without any warranty of any
   9  * kind, whether express or implied.
  10  */
  11
  12 #include <dt-bindings/clock/r8a7794-clock.h>
  13 #include <dt-bindings/interrupt-controller/arm-gic.h>
  14 #include <dt-bindings/interrupt-controller/irq.h>
  15
  16 / {
  17         compatible = "renesas,r8a7794";
  18         interrupt-parent = <&gic>;
  19         #address-cells = <2>;
  20         #size-cells = <2>;
  21
  22         cpus {
  23                 #address-cells = <1>;
  24                 #size-cells = <0>;
  25
  26                 cpu0: cpu@0 {
  27                         device_type = "cpu";
  28                         compatible = "arm,cortex-a7";
  29                         reg = <0>;
  30                         clock-frequency = <1000000000>;
  31                 };
  32
  33                 cpu1: cpu@1 {
  34                         device_type = "cpu";
  35                         compatible = "arm,cortex-a7";
  36                         reg = <1>;
  37                         clock-frequency = <1000000000>;
  38                 };
  39         };
  40
  41         gic: interrupt-controller@f1001000 {
  42                 compatible = "arm,cortex-a7-gic";
  43                 #interrupt-cells = <3>;
  44                 #address-cells = <0>;
  45                 interrupt-controller;
  46                 reg = <0 0xf1001000 0 0x1000>,
  47                         <0 0xf1002000 0 0x1000>,
  48                         <0 0xf1004000 0 0x2000>,
  49                         <0 0xf1006000 0 0x2000>;
  50                 interrupts = <1 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
  51         };
  52
  53         cmt0: timer@ffca0000 {
  54                 compatible = "renesas,cmt-48-gen2";
  55                 reg = <0 0xffca0000 0 0x1004>;
  56                 interrupts = <0 142 IRQ_TYPE_LEVEL_HIGH>,
  57                              <0 143 IRQ_TYPE_LEVEL_HIGH>;
  58                 clocks = <&mstp1_clks R8A7794_CLK_CMT0>;
  59                 clock-names = "fck";
  60
  61                 renesas,channels-mask = <0x60>;
  62
  63                 status = "disabled";
  64         };
  65
  66         cmt1: timer@e6130000 {
  67                 compatible = "renesas,cmt-48-gen2";
  68                 reg = <0 0xe6130000 0 0x1004>;
  69                 interrupts = <0 120 IRQ_TYPE_LEVEL_HIGH>,
  70                              <0 121 IRQ_TYPE_LEVEL_HIGH>,
  71                              <0 122 IRQ_TYPE_LEVEL_HIGH>,
  72                              <0 123 IRQ_TYPE_LEVEL_HIGH>,
  73                              <0 124 IRQ_TYPE_LEVEL_HIGH>,
  74                              <0 125 IRQ_TYPE_LEVEL_HIGH>,
  75                              <0 126 IRQ_TYPE_LEVEL_HIGH>,
  76                              <0 127 IRQ_TYPE_LEVEL_HIGH>;
  77                 clocks = <&mstp3_clks R8A7794_CLK_CMT1>;
  78                 clock-names = "fck";
  79
  80                 renesas,channels-mask = <0xff>;
  81
  82                 status = "disabled";
  83         };
  84
  85         timer {
  86                 compatible = "arm,armv7-timer";
  87                 interrupts = <1 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
  88                              <1 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
  89                              <1 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
  90                              <1 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
  91         };
  92
  93         irqc0: interrupt-controller@e61c0000 {
  94                 compatible = "renesas,irqc-r8a7794", "renesas,irqc";
  95                 #interrupt-cells = <2>;
  96                 interrupt-controller;
  97                 reg = <0 0xe61c0000 0 0x200>;
  98                 interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>,
  99                              <0 1 IRQ_TYPE_LEVEL_HIGH>,
 100                              <0 2 IRQ_TYPE_LEVEL_HIGH>,
 101                              <0 3 IRQ_TYPE_LEVEL_HIGH>,
 102                              <0 12 IRQ_TYPE_LEVEL_HIGH>,
 103                              <0 13 IRQ_TYPE_LEVEL_HIGH>,
 104                              <0 14 IRQ_TYPE_LEVEL_HIGH>,
 105                              <0 15 IRQ_TYPE_LEVEL_HIGH>,
 106                              <0 16 IRQ_TYPE_LEVEL_HIGH>,
 107                              <0 17 IRQ_TYPE_LEVEL_HIGH>;
 108         };
 109
 110         dmac0: dma-controller@e6700000 {
 111                 compatible = "renesas,rcar-dmac";
 112                 reg = <0 0xe6700000 0 0x20000>;
 113                 interrupts = <0 197 IRQ_TYPE_LEVEL_HIGH
 114                               0 200 IRQ_TYPE_LEVEL_HIGH
 115                               0 201 IRQ_TYPE_LEVEL_HIGH
 116                               0 202 IRQ_TYPE_LEVEL_HIGH
 117                               0 203 IRQ_TYPE_LEVEL_HIGH
 118                               0 204 IRQ_TYPE_LEVEL_HIGH
 119                               0 205 IRQ_TYPE_LEVEL_HIGH
 120                               0 206 IRQ_TYPE_LEVEL_HIGH
 121                               0 207 IRQ_TYPE_LEVEL_HIGH
 122                               0 208 IRQ_TYPE_LEVEL_HIGH
 123                               0 209 IRQ_TYPE_LEVEL_HIGH
 124                               0 210 IRQ_TYPE_LEVEL_HIGH
 125                               0 211 IRQ_TYPE_LEVEL_HIGH
 126                               0 212 IRQ_TYPE_LEVEL_HIGH
 127                               0 213 IRQ_TYPE_LEVEL_HIGH
 128                               0 214 IRQ_TYPE_LEVEL_HIGH>;
 129                 interrupt-names = "error",
 130                                 "ch0", "ch1", "ch2", "ch3",
 131                                 "ch4", "ch5", "ch6", "ch7",
 132                                 "ch8", "ch9", "ch10", "ch11",
 133                                 "ch12", "ch13", "ch14";
 134                 clocks = <&mstp2_clks R8A7794_CLK_SYS_DMAC0>;
 135                 clock-names = "fck";
 136                 #dma-cells = <1>;
 137                 dma-channels = <15>;
 138         };
 139
 140         dmac1: dma-controller@e6720000 {
 141                 compatible = "renesas,rcar-dmac";
 142                 reg = <0 0xe6720000 0 0x20000>;
 143                 interrupts = <0 220 IRQ_TYPE_LEVEL_HIGH
 144                               0 216 IRQ_TYPE_LEVEL_HIGH
 145                               0 217 IRQ_TYPE_LEVEL_HIGH
 146                               0 218 IRQ_TYPE_LEVEL_HIGH
 147                               0 219 IRQ_TYPE_LEVEL_HIGH
 148                               0 308 IRQ_TYPE_LEVEL_HIGH
 149                               0 309 IRQ_TYPE_LEVEL_HIGH
 150                               0 310 IRQ_TYPE_LEVEL_HIGH
 151                               0 311 IRQ_TYPE_LEVEL_HIGH
 152                               0 312 IRQ_TYPE_LEVEL_HIGH
 153                               0 313 IRQ_TYPE_LEVEL_HIGH
 154                               0 314 IRQ_TYPE_LEVEL_HIGH
 155                               0 315 IRQ_TYPE_LEVEL_HIGH
 156                               0 316 IRQ_TYPE_LEVEL_HIGH
 157                               0 317 IRQ_TYPE_LEVEL_HIGH
 158                               0 318 IRQ_TYPE_LEVEL_HIGH>;
 159                 interrupt-names = "error",
 160                                 "ch0", "ch1", "ch2", "ch3",
 161                                 "ch4", "ch5", "ch6", "ch7",
 162                                 "ch8", "ch9", "ch10", "ch11",
 163                                 "ch12", "ch13", "ch14";
 164                 clocks = <&mstp2_clks R8A7794_CLK_SYS_DMAC1>;
 165                 clock-names = "fck";
 166                 #dma-cells = <1>;
 167                 dma-channels = <15>;
 168         };
 169
 170         scifa0: serial@e6c40000 {
 171                 compatible = "renesas,scifa-r8a7794", "renesas,scifa";
 172                 reg = <0 0xe6c40000 0 64>;
 173                 interrupts = <0 144 IRQ_TYPE_LEVEL_HIGH>;
 174                 clocks = <&mstp2_clks R8A7794_CLK_SCIFA0>;
 175                 clock-names = "sci_ick";
 176                 status = "disabled";
 177         };
 178
 179         scifa1: serial@e6c50000 {
 180                 compatible = "renesas,scifa-r8a7794", "renesas,scifa";
 181                 reg = <0 0xe6c50000 0 64>;
 182                 interrupts = <0 145 IRQ_TYPE_LEVEL_HIGH>;
 183                 clocks = <&mstp2_clks R8A7794_CLK_SCIFA1>;
 184                 clock-names = "sci_ick";
 185                 status = "disabled";
 186         };
 187
 188         scifa2: serial@e6c60000 {
 189                 compatible = "renesas,scifa-r8a7794", "renesas,scifa";
 190                 reg = <0 0xe6c60000 0 64>;
 191                 interrupts = <0 151 IRQ_TYPE_LEVEL_HIGH>;
 192                 clocks = <&mstp2_clks R8A7794_CLK_SCIFA2>;
 193                 clock-names = "sci_ick";
 194                 status = "disabled";
 195         };
 196
 197         scifa3: serial@e6c70000 {
 198                 compatible = "renesas,scifa-r8a7794", "renesas,scifa";
 199                 reg = <0 0xe6c70000 0 64>;
 200                 interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>;
 201                 clocks = <&mstp11_clks R8A7794_CLK_SCIFA3>;
 202                 clock-names = "sci_ick";
 203                 status = "disabled";
 204         };
 205
 206         scifa4: serial@e6c78000 {
 207                 compatible = "renesas,scifa-r8a7794", "renesas,scifa";
 208                 reg = <0 0xe6c78000 0 64>;
 209                 interrupts = <0 30 IRQ_TYPE_LEVEL_HIGH>;
 210                 clocks = <&mstp11_clks R8A7794_CLK_SCIFA4>;
 211                 clock-names = "sci_ick";
 212                 status = "disabled";
 213         };
 214
 215         scifa5: serial@e6c80000 {
 216                 compatible = "renesas,scifa-r8a7794", "renesas,scifa";
 217                 reg = <0 0xe6c80000 0 64>;
 218                 interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>;
 219                 clocks = <&mstp11_clks R8A7794_CLK_SCIFA5>;
 220                 clock-names = "sci_ick";
 221                 status = "disabled";
 222         };
 223
 224         scifb0: serial@e6c20000 {
 225                 compatible = "renesas,scifb-r8a7794", "renesas,scifb";
 226                 reg = <0 0xe6c20000 0 64>;
 227                 interrupts = <0 148 IRQ_TYPE_LEVEL_HIGH>;
 228                 clocks = <&mstp2_clks R8A7794_CLK_SCIFB0>;
 229                 clock-names = "sci_ick";
 230                 status = "disabled";
 231         };
 232
 233         scifb1: serial@e6c30000 {
 234                 compatible = "renesas,scifb-r8a7794", "renesas,scifb";
 235                 reg = <0 0xe6c30000 0 64>;
 236                 interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH>;
 237                 clocks = <&mstp2_clks R8A7794_CLK_SCIFB1>;
 238                 clock-names = "sci_ick";
 239                 status = "disabled";
 240         };
 241
 242         scifb2: serial@e6ce0000 {
 243                 compatible = "renesas,scifb-r8a7794", "renesas,scifb";
 244                 reg = <0 0xe6ce0000 0 64>;
 245                 interrupts = <0 150 IRQ_TYPE_LEVEL_HIGH>;
 246                 clocks = <&mstp2_clks R8A7794_CLK_SCIFB2>;
 247                 clock-names = "sci_ick";
 248                 status = "disabled";
 249         };
 250
 251         scif0: serial@e6e60000 {
 252                 compatible = "renesas,scif-r8a7794", "renesas,scif";
 253                 reg = <0 0xe6e60000 0 64>;
 254                 interrupts = <0 152 IRQ_TYPE_LEVEL_HIGH>;
 255                 clocks = <&mstp7_clks R8A7794_CLK_SCIF0>;
 256                 clock-names = "sci_ick";
 257                 status = "disabled";
 258         };
 259
 260         scif1: serial@e6e68000 {
 261                 compatible = "renesas,scif-r8a7794", "renesas,scif";
 262                 reg = <0 0xe6e68000 0 64>;
 263                 interrupts = <0 153 IRQ_TYPE_LEVEL_HIGH>;
 264                 clocks = <&mstp7_clks R8A7794_CLK_SCIF1>;
 265                 clock-names = "sci_ick";
 266                 status = "disabled";
 267         };
 268
 269         scif2: serial@e6e58000 {
 270                 compatible = "renesas,scif-r8a7794", "renesas,scif";
 271                 reg = <0 0xe6e58000 0 64>;
 272                 interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>;
 273                 clocks = <&mstp7_clks R8A7794_CLK_SCIF2>;
 274                 clock-names = "sci_ick";
 275                 status = "disabled";
 276         };
 277
 278         scif3: serial@e6ea8000 {
 279                 compatible = "renesas,scif-r8a7794", "renesas,scif";
 280                 reg = <0 0xe6ea8000 0 64>;
 281                 interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>;
 282                 clocks = <&mstp7_clks R8A7794_CLK_SCIF3>;
 283                 clock-names = "sci_ick";
 284                 status = "disabled";
 285         };
 286
 287         scif4: serial@e6ee0000 {
 288                 compatible = "renesas,scif-r8a7794", "renesas,scif";
 289                 reg = <0 0xe6ee0000 0 64>;
 290                 interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>;
 291                 clocks = <&mstp7_clks R8A7794_CLK_SCIF4>;
 292                 clock-names = "sci_ick";
 293                 status = "disabled";
 294         };
 295
 296         scif5: serial@e6ee8000 {
 297                 compatible = "renesas,scif-r8a7794", "renesas,scif";
 298                 reg = <0 0xe6ee8000 0 64>;
 299                 interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>;
 300                 clocks = <&mstp7_clks R8A7794_CLK_SCIF5>;
 301                 clock-names = "sci_ick";
 302                 status = "disabled";
 303         };
 304
 305         hscif0: serial@e62c0000 {
 306                 compatible = "renesas,hscif-r8a7794", "renesas,hscif";
 307                 reg = <0 0xe62c0000 0 96>;
 308                 interrupts = <0 154 IRQ_TYPE_LEVEL_HIGH>;
 309                 clocks = <&mstp7_clks R8A7794_CLK_HSCIF0>;
 310                 clock-names = "sci_ick";
 311                 status = "disabled";
 312         };
 313
 314         hscif1: serial@e62c8000 {
 315                 compatible = "renesas,hscif-r8a7794", "renesas,hscif";
 316                 reg = <0 0xe62c8000 0 96>;
 317                 interrupts = <0 155 IRQ_TYPE_LEVEL_HIGH>;
 318                 clocks = <&mstp7_clks R8A7794_CLK_HSCIF1>;
 319                 clock-names = "sci_ick";
 320                 status = "disabled";
 321         };
 322
 323         hscif2: serial@e62d0000 {
 324                 compatible = "renesas,hscif-r8a7794", "renesas,hscif";
 325                 reg = <0 0xe62d0000 0 96>;
 326                 interrupts = <0 21 IRQ_TYPE_LEVEL_HIGH>;
 327                 clocks = <&mstp7_clks R8A7794_CLK_HSCIF2>;
 328                 clock-names = "sci_ick";
 329                 status = "disabled";
 330         };
 331
 332         ether: ethernet@ee700000 {
 333                 compatible = "renesas,ether-r8a7794";
 334                 reg = <0 0xee700000 0 0x400>;
 335                 interrupts = <0 162 IRQ_TYPE_LEVEL_HIGH>;
 336                 clocks = <&mstp8_clks R8A7794_CLK_ETHER>;
 337                 phy-mode = "rmii";
 338                 #address-cells = <1>;
 339                 #size-cells = <0>;
 340                 status = "disabled";
 341         };
 342
 343         sdhi0: sd@ee100000 {
 344                 compatible = "renesas,sdhi-r8a7794";
 345                 reg = <0 0xee100000 0 0x200>;
 346                 interrupts = <0 165 IRQ_TYPE_LEVEL_HIGH>;
 347                 clocks = <&mstp3_clks R8A7794_CLK_SDHI0>;
 348                 status = "disabled";
 349         };
 350
 351         sdhi1: sd@ee140000 {
 352                 compatible = "renesas,sdhi-r8a7794";
 353                 reg = <0 0xee140000 0 0x100>;
 354                 interrupts = <0 167 IRQ_TYPE_LEVEL_HIGH>;
 355                 clocks = <&mstp3_clks R8A7794_CLK_SDHI1>;
 356                 status = "disabled";
 357         };
 358
 359         sdhi2: sd@ee160000 {
 360                 compatible = "renesas,sdhi-r8a7794";
 361                 reg = <0 0xee160000 0 0x100>;
 362                 interrupts = <0 168 IRQ_TYPE_LEVEL_HIGH>;
 363                 clocks = <&mstp3_clks R8A7794_CLK_SDHI2>;
 364                 status = "disabled";
 365         };
 366
 367         clocks {
 368                 #address-cells = <2>;
 369                 #size-cells = <2>;
 370                 ranges;
 371
 372                 /* External root clock */
 373                 extal_clk: extal_clk {
 374                         compatible = "fixed-clock";
 375                         #clock-cells = <0>;
 376                         /* This value must be overriden by the board. */
 377                         clock-frequency = <0>;
 378                         clock-output-names = "extal";
 379                 };
 380
 381                 /* Special CPG clocks */
 382                 cpg_clocks: cpg_clocks@e6150000 {
 383                         compatible = "renesas,r8a7794-cpg-clocks",
 384                                      "renesas,rcar-gen2-cpg-clocks";
 385                         reg = <0 0xe6150000 0 0x1000>;
 386                         clocks = <&extal_clk>;
 387                         #clock-cells = <1>;
 388                         clock-output-names = "main", "pll0", "pll1", "pll3",
 389                                              "lb", "qspi", "sdh", "sd0", "z";
 390                 };
 391                 /* Variable factor clocks */
 392                 sd2_clk: sd2_clk@e6150078 {
 393                         compatible = "renesas,r8a7794-div6-clock", "renesas,cpg-div6-clock";
 394                         reg = <0 0xe6150078 0 4>;
 395                         clocks = <&pll1_div2_clk>;
 396                         #clock-cells = <0>;
 397                         clock-output-names = "sd2";
 398                 };
 399                 sd3_clk: sd3_clk@e615026c {
 400                         compatible = "renesas,r8a7794-div6-clock", "renesas,cpg-div6-clock";
 401                         reg = <0 0xe615026c 0 4>;
 402                         clocks = <&pll1_div2_clk>;
 403                         #clock-cells = <0>;
 404                         clock-output-names = "sd3";
 405                 };
 406                 mmc0_clk: mmc0_clk@e6150240 {
 407                         compatible = "renesas,r8a7794-div6-clock", "renesas,cpg-div6-clock";
 408                         reg = <0 0xe6150240 0 4>;
 409                         clocks = <&pll1_div2_clk>;
 410                         #clock-cells = <0>;
 411                         clock-output-names = "mmc0";
 412                 };
 413
 414                 /* Fixed factor clocks */
 415                 pll1_div2_clk: pll1_div2_clk {
 416                         compatible = "fixed-factor-clock";
 417                         clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
 418                         #clock-cells = <0>;
 419                         clock-div = <2>;
 420                         clock-mult = <1>;
 421                         clock-output-names = "pll1_div2";
 422                 };
 423                 zg_clk: zg_clk {
 424                         compatible = "fixed-factor-clock";
 425                         clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
 426                         #clock-cells = <0>;
 427                         clock-div = <6>;
 428                         clock-mult = <1>;
 429                         clock-output-names = "zg";
 430                 };
 431                 zx_clk: zx_clk {
 432                         compatible = "fixed-factor-clock";
 433                         clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
 434                         #clock-cells = <0>;
 435                         clock-div = <3>;
 436                         clock-mult = <1>;
 437                         clock-output-names = "zx";
 438                 };
 439                 zs_clk: zs_clk {
 440                         compatible = "fixed-factor-clock";
 441                         clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
 442                         #clock-cells = <0>;
 443                         clock-div = <6>;
 444                         clock-mult = <1>;
 445                         clock-output-names = "zs";
 446                 };
 447                 hp_clk: hp_clk {
 448                         compatible = "fixed-factor-clock";
 449                         clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
 450                         #clock-cells = <0>;
 451                         clock-div = <12>;
 452                         clock-mult = <1>;
 453                         clock-output-names = "hp";
 454                 };
 455                 i_clk: i_clk {
 456                         compatible = "fixed-factor-clock";
 457                         clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
 458                         #clock-cells = <0>;
 459                         clock-div = <2>;
 460                         clock-mult = <1>;
 461                         clock-output-names = "i";
 462                 };
 463                 b_clk: b_clk {
 464                         compatible = "fixed-factor-clock";
 465                         clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
 466                         #clock-cells = <0>;
 467                         clock-div = <12>;
 468                         clock-mult = <1>;
 469                         clock-output-names = "b";
 470                 };
 471                 p_clk: p_clk {
 472                         compatible = "fixed-factor-clock";
 473                         clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
 474                         #clock-cells = <0>;
 475                         clock-div = <24>;
 476                         clock-mult = <1>;
 477                         clock-output-names = "p";
 478                 };
 479                 cl_clk: cl_clk {
 480                         compatible = "fixed-factor-clock";
 481                         clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
 482                         #clock-cells = <0>;
 483                         clock-div = <48>;
 484                         clock-mult = <1>;
 485                         clock-output-names = "cl";
 486                 };
 487                 m2_clk: m2_clk {
 488                         compatible = "fixed-factor-clock";
 489                         clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
 490                         #clock-cells = <0>;
 491                         clock-div = <8>;
 492                         clock-mult = <1>;
 493                         clock-output-names = "m2";
 494                 };
 495                 imp_clk: imp_clk {
 496                         compatible = "fixed-factor-clock";
 497                         clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
 498                         #clock-cells = <0>;
 499                         clock-div = <4>;
 500                         clock-mult = <1>;
 501                         clock-output-names = "imp";
 502                 };
 503                 rclk_clk: rclk_clk {
 504                         compatible = "fixed-factor-clock";
 505                         clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
 506                         #clock-cells = <0>;
 507                         clock-div = <(48 * 1024)>;
 508                         clock-mult = <1>;
 509                         clock-output-names = "rclk";
 510                 };
 511                 oscclk_clk: oscclk_clk {
 512                         compatible = "fixed-factor-clock";
 513                         clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
 514                         #clock-cells = <0>;
 515                         clock-div = <(12 * 1024)>;
 516                         clock-mult = <1>;
 517                         clock-output-names = "oscclk";
 518                 };
 519                 zb3_clk: zb3_clk {
 520                         compatible = "fixed-factor-clock";
 521                         clocks = <&cpg_clocks R8A7794_CLK_PLL3>;
 522                         #clock-cells = <0>;
 523                         clock-div = <4>;
 524                         clock-mult = <1>;
 525                         clock-output-names = "zb3";
 526                 };
 527                 zb3d2_clk: zb3d2_clk {
 528                         compatible = "fixed-factor-clock";
 529                         clocks = <&cpg_clocks R8A7794_CLK_PLL3>;
 530                         #clock-cells = <0>;
 531                         clock-div = <8>;
 532                         clock-mult = <1>;
 533                         clock-output-names = "zb3d2";
 534                 };
 535                 ddr_clk: ddr_clk {
 536                         compatible = "fixed-factor-clock";
 537                         clocks = <&cpg_clocks R8A7794_CLK_PLL3>;
 538                         #clock-cells = <0>;
 539                         clock-div = <8>;
 540                         clock-mult = <1>;
 541                         clock-output-names = "ddr";
 542                 };
 543                 mp_clk: mp_clk {
 544                         compatible = "fixed-factor-clock";
 545                         clocks = <&pll1_div2_clk>;
 546                         #clock-cells = <0>;
 547                         clock-div = <15>;
 548                         clock-mult = <1>;
 549                         clock-output-names = "mp";
 550                 };
 551                 cp_clk: cp_clk {
 552                         compatible = "fixed-factor-clock";
 553                         clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
 554                         #clock-cells = <0>;
 555                         clock-div = <48>;
 556                         clock-mult = <1>;
 557                         clock-output-names = "cp";
 558                 };
 559
 560                 acp_clk: acp_clk {
 561                         compatible = "fixed-factor-clock";
 562                         clocks = <&extal_clk>;
 563                         #clock-cells = <0>;
 564                         clock-div = <2>;
 565                         clock-mult = <1>;
 566                         clock-output-names = "acp";
 567                 };
 568
 569                 /* Gate clocks */
 570                 mstp0_clks: mstp0_clks@e6150130 {
 571                         compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
 572                         reg = <0 0xe6150130 0 4>, <0 0xe6150030 0 4>;
 573                         clocks = <&mp_clk>;
 574                         #clock-cells = <1>;
 575                         clock-indices = <R8A7794_CLK_MSIOF0>;
 576                         clock-output-names = "msiof0";
 577                 };
 578                 mstp1_clks: mstp1_clks@e6150134 {
 579                         compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
 580                         reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>;
 581                         clocks = <&zs_clk>, <&zs_clk>, <&p_clk>, <&zg_clk>, <&zs_clk>,
 582                                  <&zs_clk>, <&p_clk>, <&p_clk>, <&rclk_clk>, <&cp_clk>,
 583                                  <&zs_clk>, <&zs_clk>;
 584                         #clock-cells = <1>;
 585                         clock-indices = <
 586                                 R8A7794_CLK_VCP0 R8A7794_CLK_VPC0 R8A7794_CLK_TMU1
 587                                 R8A7794_CLK_3DG R8A7794_CLK_2DDMAC R8A7794_CLK_FDP1_0
 588                                 R8A7794_CLK_TMU3 R8A7794_CLK_TMU2 R8A7794_CLK_CMT0
 589                                 R8A7794_CLK_TMU0 R8A7794_CLK_VSP1_DU0 R8A7794_CLK_VSP1_S
 590                         >;
 591                         clock-output-names =
 592                                 "vcp0", "vpc0", "tmu1", "3dg", "2ddmac", "fdp1-0",
 593                                 "tmu3", "tmu2", "cmt0", "tmu0", "vsp1-du0", "vsps";
 594                 };
 595                 mstp2_clks: mstp2_clks@e6150138 {
 596                         compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
 597                         reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>;
 598                         clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>,
 599                                  <&mp_clk>, <&mp_clk>, <&mp_clk>,
 600                                  <&zs_clk>, <&zs_clk>;
 601                         #clock-cells = <1>;
 602                         clock-indices = <
 603                                 R8A7794_CLK_SCIFA2 R8A7794_CLK_SCIFA1 R8A7794_CLK_SCIFA0
 604                                 R8A7794_CLK_MSIOF2 R8A7794_CLK_SCIFB0 R8A7794_CLK_SCIFB1
 605                                 R8A7794_CLK_MSIOF1 R8A7794_CLK_SCIFB2
 606                                 R8A7794_CLK_SYS_DMAC1 R8A7794_CLK_SYS_DMAC0
 607                         >;
 608                         clock-output-names =
 609                                 "scifa2", "scifa1", "scifa0", "msiof2", "scifb0",
 610                                 "scifb1", "msiof1", "scifb2",
 611                                 "sys-dmac1", "sys-dmac0";
 612                 };
 613                 mstp3_clks: mstp3_clks@e615013c {
 614                         compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
 615                         reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>;
 616                         clocks = <&sd3_clk>, <&sd2_clk>, <&cpg_clocks R8A7794_CLK_SD0>,
 617                                  <&mmc0_clk>, <&rclk_clk>, <&hp_clk>, <&hp_clk>;
 618                         #clock-cells = <1>;
 619                         clock-indices = <
 620                                 R8A7794_CLK_SDHI2 R8A7794_CLK_SDHI1 R8A7794_CLK_SDHI0
 621                                 R8A7794_CLK_MMCIF0 R8A7794_CLK_CMT1
 622                                 R8A7794_CLK_USBDMAC0 R8A7794_CLK_USBDMAC1
 623                         >;
 624                         clock-output-names =
 625                                 "sdhi2", "sdhi1", "sdhi0",
 626                                 "mmcif0", "cmt1", "usbdmac0", "usbdmac1";
 627                 };
 628                 mstp7_clks: mstp7_clks@e615014c {
 629                         compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
 630                         reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>;
 631                         clocks = <&mp_clk>, <&mp_clk>,
 632                                  <&zs_clk>, <&p_clk>, <&p_clk>, <&zs_clk>,
 633                                  <&zs_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>;
 634                         #clock-cells = <1>;
 635                         clock-indices = <
 636                                 R8A7794_CLK_EHCI R8A7794_CLK_HSUSB
 637                                 R8A7794_CLK_HSCIF2 R8A7794_CLK_SCIF5
 638                                 R8A7794_CLK_SCIF4 R8A7794_CLK_HSCIF1 R8A7794_CLK_HSCIF0
 639                                 R8A7794_CLK_SCIF3 R8A7794_CLK_SCIF2 R8A7794_CLK_SCIF1
 640                                 R8A7794_CLK_SCIF0
 641                         >;
 642                         clock-output-names =
 643                                 "ehci", "hsusb",
 644                                 "hscif2", "scif5", "scif4", "hscif1", "hscif0",
 645                                 "scif3", "scif2", "scif1", "scif0";
 646                 };
 647                 mstp8_clks: mstp8_clks@e6150990 {
 648                         compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
 649                         reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>;
 650                         clocks = <&zg_clk>, <&zg_clk>, <&p_clk>;
 651                         #clock-cells = <1>;
 652                         clock-indices = <
 653                                 R8A7794_CLK_VIN1 R8A7794_CLK_VIN0 R8A7794_CLK_ETHER
 654                         >;
 655                         clock-output-names =
 656                                 "vin1", "vin0", "ether";
 657                 };
 658                 mstp9_clks: mstp9_clks@e6150994 {
 659                         compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
 660                         reg = <0 0xe6150994 0 4>, <0 0xe61509a4 0 4>;
 661                         clocks = <&cpg_clocks R8A7794_CLK_QSPI>, <&hp_clk>, <&hp_clk>,
 662                                 <&hp_clk>, <&hp_clk>, <&hp_clk>, <&hp_clk>;
 663                         #clock-cells = <1>;
 664                         clock-indices = <
 665                                 R8A7794_CLK_QSPI_MOD R8A7794_CLK_I2C5 R8A7794_CLK_I2C4
 666                                 R8A7794_CLK_I2C3 R8A7794_CLK_I2C2 R8A7794_CLK_I2C1
 667                                 R8A7794_CLK_I2C0
 668                         >;
 669                         clock-output-names =
 670                                 "qspi_mod", "i2c5", "i2c4", "i2c3", "i2c2", "i2c1", "i2c0";
 671                 };
 672                 mstp11_clks: mstp11_clks@e615099c {
 673                         compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
 674                         reg = <0 0xe615099c 0 4>, <0 0xe61509ac 0 4>;
 675                         clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>;
 676                         #clock-cells = <1>;
 677                         clock-indices = <
 678                                 R8A7794_CLK_SCIFA3 R8A7794_CLK_SCIFA4 R8A7794_CLK_SCIFA5
 679                         >;
 680                         clock-output-names = "scifa3", "scifa4", "scifa5";
 681                 };
 682         };
 683
 684         ipmmu_sy0: mmu@e6280000 {
 685                 compatible = "renesas,ipmmu-vmsa";
 686                 reg = <0 0xe6280000 0 0x1000>;
 687                 interrupts = <0 223 IRQ_TYPE_LEVEL_HIGH>,
 688                              <0 224 IRQ_TYPE_LEVEL_HIGH>;
 689                 #iommu-cells = <1>;
 690                 status = "disabled";
 691         };
 692
 693         ipmmu_sy1: mmu@e6290000 {
 694                 compatible = "renesas,ipmmu-vmsa";
 695                 reg = <0 0xe6290000 0 0x1000>;
 696                 interrupts = <0 225 IRQ_TYPE_LEVEL_HIGH>;
 697                 #iommu-cells = <1>;
 698                 status = "disabled";
 699         };
 700
 701         ipmmu_ds: mmu@e6740000 {
 702                 compatible = "renesas,ipmmu-vmsa";
 703                 reg = <0 0xe6740000 0 0x1000>;
 704                 interrupts = <0 198 IRQ_TYPE_LEVEL_HIGH>,
 705                              <0 199 IRQ_TYPE_LEVEL_HIGH>;
 706                 #iommu-cells = <1>;
 707         };
 708
 709         ipmmu_mp: mmu@ec680000 {
 710                 compatible = "renesas,ipmmu-vmsa";
 711                 reg = <0 0xec680000 0 0x1000>;
 712                 interrupts = <0 226 IRQ_TYPE_LEVEL_HIGH>;
 713                 #iommu-cells = <1>;
 714                 status = "disabled";
 715         };
 716
 717         ipmmu_mx: mmu@fe951000 {
 718                 compatible = "renesas,ipmmu-vmsa";
 719                 reg = <0 0xfe951000 0 0x1000>;
 720                 interrupts = <0 222 IRQ_TYPE_LEVEL_HIGH>,
 721                              <0 221 IRQ_TYPE_LEVEL_HIGH>;
 722                 #iommu-cells = <1>;
 723         };
 724
 725         ipmmu_gp: mmu@e62a0000 {
 726                 compatible = "renesas,ipmmu-vmsa";
 727                 reg = <0 0xe62a0000 0 0x1000>;
 728                 interrupts = <0 260 IRQ_TYPE_LEVEL_HIGH>,
 729                              <0 261 IRQ_TYPE_LEVEL_HIGH>;
 730                 #iommu-cells = <1>;
 731                 status = "disabled";
 732         };
 733 };