kernel/arch/arm/boot/dts/imx6qdl.dtsi

   1 /*
   2  * Copyright 2011 Freescale Semiconductor, Inc.
   3  * Copyright 2011 Linaro Ltd.
   4  *
   5  * The code contained herein is licensed under the GNU General Public
   6  * License. You may obtain a copy of the GNU General Public License
   7  * Version 2 or later at the following locations:
   8  *
   9  * http://www.opensource.org/licenses/gpl-license.html
  10  * http://www.gnu.org/copyleft/gpl.html
  11  */
  12
  13 #include <dt-bindings/clock/imx6qdl-clock.h>
  14 #include <dt-bindings/interrupt-controller/arm-gic.h>
  15
  16 #include "skeleton.dtsi"
  17
  18 / {
  19         aliases {
  20                 ethernet0 = &fec;
  21                 can0 = &can1;
  22                 can1 = &can2;
  23                 gpio0 = &gpio1;
  24                 gpio1 = &gpio2;
  25                 gpio2 = &gpio3;
  26                 gpio3 = &gpio4;
  27                 gpio4 = &gpio5;
  28                 gpio5 = &gpio6;
  29                 gpio6 = &gpio7;
  30                 i2c0 = &i2c1;
  31                 i2c1 = &i2c2;
  32                 i2c2 = &i2c3;
  33                 mmc0 = &usdhc1;
  34                 mmc1 = &usdhc2;
  35                 mmc2 = &usdhc3;
  36                 mmc3 = &usdhc4;
  37                 serial0 = &uart1;
  38                 serial1 = &uart2;
  39                 serial2 = &uart3;
  40                 serial3 = &uart4;
  41                 serial4 = &uart5;
  42                 spi0 = &ecspi1;
  43                 spi1 = &ecspi2;
  44                 spi2 = &ecspi3;
  45                 spi3 = &ecspi4;
  46                 usbphy0 = &usbphy1;
  47                 usbphy1 = &usbphy2;
  48         };
  49
  50         intc: interrupt-controller@00a01000 {
  51                 compatible = "arm,cortex-a9-gic";
  52                 #interrupt-cells = <3>;
  53                 interrupt-controller;
  54                 reg = <0x00a01000 0x1000>,
  55                       <0x00a00100 0x100>;
  56                 interrupt-parent = <&intc>;
  57         };
  58
  59         clocks {
  60                 #address-cells = <1>;
  61                 #size-cells = <0>;
  62
  63                 ckil {
  64                         compatible = "fsl,imx-ckil", "fixed-clock";
  65                         #clock-cells = <0>;
  66                         clock-frequency = <32768>;
  67                 };
  68
  69                 ckih1 {
  70                         compatible = "fsl,imx-ckih1", "fixed-clock";
  71                         #clock-cells = <0>;
  72                         clock-frequency = <0>;
  73                 };
  74
  75                 osc {
  76                         compatible = "fsl,imx-osc", "fixed-clock";
  77                         #clock-cells = <0>;
  78                         clock-frequency = <24000000>;
  79                 };
  80         };
  81
  82         soc {
  83                 #address-cells = <1>;
  84                 #size-cells = <1>;
  85                 compatible = "simple-bus";
  86                 interrupt-parent = <&gpc>;
  87                 ranges;
  88
  89                 dma_apbh: dma-apbh@00110000 {
  90                         compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh";
  91                         reg = <0x00110000 0x2000>;
  92                         interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>,
  93                                      <0 13 IRQ_TYPE_LEVEL_HIGH>,
  94                                      <0 13 IRQ_TYPE_LEVEL_HIGH>,
  95                                      <0 13 IRQ_TYPE_LEVEL_HIGH>;
  96                         interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
  97                         #dma-cells = <1>;
  98                         dma-channels = <4>;
  99                         clocks = <&clks IMX6QDL_CLK_APBH_DMA>;
 100                 };
 101
 102                 gpmi: gpmi-nand@00112000 {
 103                         compatible = "fsl,imx6q-gpmi-nand";
 104                         #address-cells = <1>;
 105                         #size-cells = <1>;
 106                         reg = <0x00112000 0x2000>, <0x00114000 0x2000>;
 107                         reg-names = "gpmi-nand", "bch";
 108                         interrupts = <0 15 IRQ_TYPE_LEVEL_HIGH>;
 109                         interrupt-names = "bch";
 110                         clocks = <&clks IMX6QDL_CLK_GPMI_IO>,
 111                                  <&clks IMX6QDL_CLK_GPMI_APB>,
 112                                  <&clks IMX6QDL_CLK_GPMI_BCH>,
 113                                  <&clks IMX6QDL_CLK_GPMI_BCH_APB>,
 114                                  <&clks IMX6QDL_CLK_PER1_BCH>;
 115                         clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch",
 116                                       "gpmi_bch_apb", "per1_bch";
 117                         dmas = <&dma_apbh 0>;
 118                         dma-names = "rx-tx";
 119                         status = "disabled";
 120                 };
 121
 122                 timer@00a00600 {
 123                         compatible = "arm,cortex-a9-twd-timer";
 124                         reg = <0x00a00600 0x20>;
 125                         interrupts = <1 13 0xf01>;
 126                         interrupt-parent = <&intc>;
 127                         clocks = <&clks IMX6QDL_CLK_TWD>;
 128                 };
 129
 130                 L2: l2-cache@00a02000 {
 131                         compatible = "arm,pl310-cache";
 132                         reg = <0x00a02000 0x1000>;
 133                         interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>;
 134                         cache-unified;
 135                         cache-level = <2>;
 136                         arm,tag-latency = <4 2 3>;
 137                         arm,data-latency = <4 2 3>;
 138                 };
 139
 140                 pcie: pcie@0x01000000 {
 141                         compatible = "fsl,imx6q-pcie", "snps,dw-pcie";
 142                         reg = <0x01ffc000 0x04000>,
 143                               <0x01f00000 0x80000>;
 144                         reg-names = "dbi", "config";
 145                         #address-cells = <3>;
 146                         #size-cells = <2>;
 147                         device_type = "pci";
 148                         ranges = <0x00000800 0 0x01f00000 0x01f00000 0 0x00080000 /* configuration space */
 149                                   0x81000000 0 0          0x01f80000 0 0x00010000 /* downstream I/O */
 150                                   0x82000000 0 0x01000000 0x01000000 0 0x00f00000>; /* non-prefetchable memory */
 151                         num-lanes = <1>;
 152                         interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
 153                         interrupt-names = "msi";
 154                         #interrupt-cells = <1>;
 155                         interrupt-map-mask = <0 0 0 0x7>;
 156                         interrupt-map = <0 0 0 1 &intc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
 157                                         <0 0 0 2 &intc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
 158                                         <0 0 0 3 &intc GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
 159                                         <0 0 0 4 &intc GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
 160                         clocks = <&clks IMX6QDL_CLK_PCIE_AXI>,
 161                                  <&clks IMX6QDL_CLK_LVDS1_GATE>,
 162                                  <&clks IMX6QDL_CLK_PCIE_REF_125M>;
 163                         clock-names = "pcie", "pcie_bus", "pcie_phy";
 164                         status = "disabled";
 165                 };
 166
 167                 pmu {
 168                         compatible = "arm,cortex-a9-pmu";
 169                         interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>;
 170                 };
 171
 172                 aips-bus@02000000 { /* AIPS1 */
 173                         compatible = "fsl,aips-bus", "simple-bus";
 174                         #address-cells = <1>;
 175                         #size-cells = <1>;
 176                         reg = <0x02000000 0x100000>;
 177                         ranges;
 178
 179                         spba-bus@02000000 {
 180                                 compatible = "fsl,spba-bus", "simple-bus";
 181                                 #address-cells = <1>;
 182                                 #size-cells = <1>;
 183                                 reg = <0x02000000 0x40000>;
 184                                 ranges;
 185
 186                                 spdif: spdif@02004000 {
 187                                         compatible = "fsl,imx35-spdif";
 188                                         reg = <0x02004000 0x4000>;
 189                                         interrupts = <0 52 IRQ_TYPE_LEVEL_HIGH>;
 190                                         dmas = <&sdma 14 18 0>,
 191                                                <&sdma 15 18 0>;
 192                                         dma-names = "rx", "tx";
 193                                         clocks = <&clks IMX6QDL_CLK_SPDIF>, <&clks IMX6QDL_CLK_OSC>,
 194                                                  <&clks IMX6QDL_CLK_SPDIF>, <&clks IMX6QDL_CLK_DUMMY>,
 195                                                  <&clks IMX6QDL_CLK_DUMMY>, <&clks IMX6QDL_CLK_DUMMY>,
 196                                                  <&clks IMX6QDL_CLK_DUMMY>, <&clks IMX6QDL_CLK_DUMMY>,
 197                                                  <&clks IMX6QDL_CLK_DUMMY>;
 198                                         clock-names = "core",  "rxtx0",
 199                                                       "rxtx1", "rxtx2",
 200                                                       "rxtx3", "rxtx4",
 201                                                       "rxtx5", "rxtx6",
 202                                                       "rxtx7";
 203                                         status = "disabled";
 204                                 };
 205
 206                                 ecspi1: ecspi@02008000 {
 207                                         #address-cells = <1>;
 208                                         #size-cells = <0>;
 209                                         compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
 210                                         reg = <0x02008000 0x4000>;
 211                                         interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>;
 212                                         clocks = <&clks IMX6QDL_CLK_ECSPI1>,
 213                                                  <&clks IMX6QDL_CLK_ECSPI1>;
 214                                         clock-names = "ipg", "per";
 215                                         dmas = <&sdma 3 7 1>, <&sdma 4 7 2>;
 216                                         dma-names = "rx", "tx";
 217                                         status = "disabled";
 218                                 };
 219
 220                                 ecspi2: ecspi@0200c000 {
 221                                         #address-cells = <1>;
 222                                         #size-cells = <0>;
 223                                         compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
 224                                         reg = <0x0200c000 0x4000>;
 225                                         interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>;
 226                                         clocks = <&clks IMX6QDL_CLK_ECSPI2>,
 227                                                  <&clks IMX6QDL_CLK_ECSPI2>;
 228                                         clock-names = "ipg", "per";
 229                                         dmas = <&sdma 5 7 1>, <&sdma 6 7 2>;
 230                                         dma-names = "rx", "tx";
 231                                         status = "disabled";
 232                                 };
 233
 234                                 ecspi3: ecspi@02010000 {
 235                                         #address-cells = <1>;
 236                                         #size-cells = <0>;
 237                                         compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
 238                                         reg = <0x02010000 0x4000>;
 239                                         interrupts = <0 33 IRQ_TYPE_LEVEL_HIGH>;
 240                                         clocks = <&clks IMX6QDL_CLK_ECSPI3>,
 241                                                  <&clks IMX6QDL_CLK_ECSPI3>;
 242                                         clock-names = "ipg", "per";
 243                                         dmas = <&sdma 7 7 1>, <&sdma 8 7 2>;
 244                                         dma-names = "rx", "tx";
 245                                         status = "disabled";
 246                                 };
 247
 248                                 ecspi4: ecspi@02014000 {
 249                                         #address-cells = <1>;
 250                                         #size-cells = <0>;
 251                                         compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
 252                                         reg = <0x02014000 0x4000>;
 253                                         interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>;
 254                                         clocks = <&clks IMX6QDL_CLK_ECSPI4>,
 255                                                  <&clks IMX6QDL_CLK_ECSPI4>;
 256                                         clock-names = "ipg", "per";
 257                                         dmas = <&sdma 9 7 1>, <&sdma 10 7 2>;
 258                                         dma-names = "rx", "tx";
 259                                         status = "disabled";
 260                                 };
 261
 262                                 uart1: serial@02020000 {
 263                                         compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
 264                                         reg = <0x02020000 0x4000>;
 265                                         interrupts = <0 26 IRQ_TYPE_LEVEL_HIGH>;
 266                                         clocks = <&clks IMX6QDL_CLK_UART_IPG>,
 267                                                  <&clks IMX6QDL_CLK_UART_SERIAL>;
 268                                         clock-names = "ipg", "per";
 269                                         dmas = <&sdma 25 4 0>, <&sdma 26 4 0>;
 270                                         dma-names = "rx", "tx";
 271                                         status = "disabled";
 272                                 };
 273
 274                                 esai: esai@02024000 {
 275                                         reg = <0x02024000 0x4000>;
 276                                         interrupts = <0 51 IRQ_TYPE_LEVEL_HIGH>;
 277                                 };
 278
 279                                 ssi1: ssi@02028000 {
 280                                         #sound-dai-cells = <0>;
 281                                         compatible = "fsl,imx6q-ssi",
 282                                                         "fsl,imx51-ssi";
 283                                         reg = <0x02028000 0x4000>;
 284                                         interrupts = <0 46 IRQ_TYPE_LEVEL_HIGH>;
 285                                         clocks = <&clks IMX6QDL_CLK_SSI1_IPG>,
 286                                                  <&clks IMX6QDL_CLK_SSI1>;
 287                                         clock-names = "ipg", "baud";
 288                                         dmas = <&sdma 37 1 0>,
 289                                                <&sdma 38 1 0>;
 290                                         dma-names = "rx", "tx";
 291                                         fsl,fifo-depth = <15>;
 292                                         status = "disabled";
 293                                 };
 294
 295                                 ssi2: ssi@0202c000 {
 296                                         #sound-dai-cells = <0>;
 297                                         compatible = "fsl,imx6q-ssi",
 298                                                         "fsl,imx51-ssi";
 299                                         reg = <0x0202c000 0x4000>;
 300                                         interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>;
 301                                         clocks = <&clks IMX6QDL_CLK_SSI2_IPG>,
 302                                                  <&clks IMX6QDL_CLK_SSI2>;
 303                                         clock-names = "ipg", "baud";
 304                                         dmas = <&sdma 41 1 0>,
 305                                                <&sdma 42 1 0>;
 306                                         dma-names = "rx", "tx";
 307                                         fsl,fifo-depth = <15>;
 308                                         status = "disabled";
 309                                 };
 310
 311                                 ssi3: ssi@02030000 {
 312                                         #sound-dai-cells = <0>;
 313                                         compatible = "fsl,imx6q-ssi",
 314                                                         "fsl,imx51-ssi";
 315                                         reg = <0x02030000 0x4000>;
 316                                         interrupts = <0 48 IRQ_TYPE_LEVEL_HIGH>;
 317                                         clocks = <&clks IMX6QDL_CLK_SSI3_IPG>,
 318                                                  <&clks IMX6QDL_CLK_SSI3>;
 319                                         clock-names = "ipg", "baud";
 320                                         dmas = <&sdma 45 1 0>,
 321                                                <&sdma 46 1 0>;
 322                                         dma-names = "rx", "tx";
 323                                         fsl,fifo-depth = <15>;
 324                                         status = "disabled";
 325                                 };
 326
 327                                 asrc: asrc@02034000 {
 328                                         reg = <0x02034000 0x4000>;
 329                                         interrupts = <0 50 IRQ_TYPE_LEVEL_HIGH>;
 330                                 };
 331
 332                                 spba@0203c000 {
 333                                         reg = <0x0203c000 0x4000>;
 334                                 };
 335                         };
 336
 337                         vpu: vpu@02040000 {
 338                                 compatible = "cnm,coda960";
 339                                 reg = <0x02040000 0x3c000>;
 340                                 interrupts = <0 12 IRQ_TYPE_LEVEL_HIGH>,
 341                                              <0 3 IRQ_TYPE_LEVEL_HIGH>;
 342                                 interrupt-names = "bit", "jpeg";
 343                                 clocks = <&clks IMX6QDL_CLK_VPU_AXI>,
 344                                          <&clks IMX6QDL_CLK_MMDC_CH0_AXI>;
 345                                 clock-names = "per", "ahb";
 346                                 resets = <&src 1>;
 347                                 iram = <&ocram>;
 348                         };
 349
 350                         aipstz@0207c000 { /* AIPSTZ1 */
 351                                 reg = <0x0207c000 0x4000>;
 352                         };
 353
 354                         pwm1: pwm@02080000 {
 355                                 #pwm-cells = <2>;
 356                                 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
 357                                 reg = <0x02080000 0x4000>;
 358                                 interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>;
 359                                 clocks = <&clks IMX6QDL_CLK_IPG>,
 360                                          <&clks IMX6QDL_CLK_PWM1>;
 361                                 clock-names = "ipg", "per";
 362                                 status = "disabled";
 363                         };
 364
 365                         pwm2: pwm@02084000 {
 366                                 #pwm-cells = <2>;
 367                                 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
 368                                 reg = <0x02084000 0x4000>;
 369                                 interrupts = <0 84 IRQ_TYPE_LEVEL_HIGH>;
 370                                 clocks = <&clks IMX6QDL_CLK_IPG>,
 371                                          <&clks IMX6QDL_CLK_PWM2>;
 372                                 clock-names = "ipg", "per";
 373                                 status = "disabled";
 374                         };
 375
 376                         pwm3: pwm@02088000 {
 377                                 #pwm-cells = <2>;
 378                                 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
 379                                 reg = <0x02088000 0x4000>;
 380                                 interrupts = <0 85 IRQ_TYPE_LEVEL_HIGH>;
 381                                 clocks = <&clks IMX6QDL_CLK_IPG>,
 382                                          <&clks IMX6QDL_CLK_PWM3>;
 383                                 clock-names = "ipg", "per";
 384                                 status = "disabled";
 385                         };
 386
 387                         pwm4: pwm@0208c000 {
 388                                 #pwm-cells = <2>;
 389                                 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
 390                                 reg = <0x0208c000 0x4000>;
 391                                 interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>;
 392                                 clocks = <&clks IMX6QDL_CLK_IPG>,
 393                                          <&clks IMX6QDL_CLK_PWM4>;
 394                                 clock-names = "ipg", "per";
 395                                 status = "disabled";
 396                         };
 397
 398                         can1: flexcan@02090000 {
 399                                 compatible = "fsl,imx6q-flexcan";
 400                                 reg = <0x02090000 0x4000>;
 401                                 interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH>;
 402                                 clocks = <&clks IMX6QDL_CLK_CAN1_IPG>,
 403                                          <&clks IMX6QDL_CLK_CAN1_SERIAL>;
 404                                 clock-names = "ipg", "per";
 405                                 status = "disabled";
 406                         };
 407
 408                         can2: flexcan@02094000 {
 409                                 compatible = "fsl,imx6q-flexcan";
 410                                 reg = <0x02094000 0x4000>;
 411                                 interrupts = <0 111 IRQ_TYPE_LEVEL_HIGH>;
 412                                 clocks = <&clks IMX6QDL_CLK_CAN2_IPG>,
 413                                          <&clks IMX6QDL_CLK_CAN2_SERIAL>;
 414                                 clock-names = "ipg", "per";
 415                                 status = "disabled";
 416                         };
 417
 418                         gpt: gpt@02098000 {
 419                                 compatible = "fsl,imx6q-gpt", "fsl,imx31-gpt";
 420                                 reg = <0x02098000 0x4000>;
 421                                 interrupts = <0 55 IRQ_TYPE_LEVEL_HIGH>;
 422                                 clocks = <&clks IMX6QDL_CLK_GPT_IPG>,
 423                                          <&clks IMX6QDL_CLK_GPT_IPG_PER>,
 424                                          <&clks IMX6QDL_CLK_GPT_3M>;
 425                                 clock-names = "ipg", "per", "osc_per";
 426                         };
 427
 428                         gpio1: gpio@0209c000 {
 429                                 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
 430                                 reg = <0x0209c000 0x4000>;
 431                                 interrupts = <0 66 IRQ_TYPE_LEVEL_HIGH>,
 432                                              <0 67 IRQ_TYPE_LEVEL_HIGH>;
 433                                 gpio-controller;
 434                                 #gpio-cells = <2>;
 435                                 interrupt-controller;
 436                                 #interrupt-cells = <2>;
 437                         };
 438
 439                         gpio2: gpio@020a0000 {
 440                                 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
 441                                 reg = <0x020a0000 0x4000>;
 442                                 interrupts = <0 68 IRQ_TYPE_LEVEL_HIGH>,
 443                                              <0 69 IRQ_TYPE_LEVEL_HIGH>;
 444                                 gpio-controller;
 445                                 #gpio-cells = <2>;
 446                                 interrupt-controller;
 447                                 #interrupt-cells = <2>;
 448                         };
 449
 450                         gpio3: gpio@020a4000 {
 451                                 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
 452                                 reg = <0x020a4000 0x4000>;
 453                                 interrupts = <0 70 IRQ_TYPE_LEVEL_HIGH>,
 454                                              <0 71 IRQ_TYPE_LEVEL_HIGH>;
 455                                 gpio-controller;
 456                                 #gpio-cells = <2>;
 457                                 interrupt-controller;
 458                                 #interrupt-cells = <2>;
 459                         };
 460
 461                         gpio4: gpio@020a8000 {
 462                                 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
 463                                 reg = <0x020a8000 0x4000>;
 464                                 interrupts = <0 72 IRQ_TYPE_LEVEL_HIGH>,
 465                                              <0 73 IRQ_TYPE_LEVEL_HIGH>;
 466                                 gpio-controller;
 467                                 #gpio-cells = <2>;
 468                                 interrupt-controller;
 469                                 #interrupt-cells = <2>;
 470                         };
 471
 472                         gpio5: gpio@020ac000 {
 473                                 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
 474                                 reg = <0x020ac000 0x4000>;
 475                                 interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>,
 476                                              <0 75 IRQ_TYPE_LEVEL_HIGH>;
 477                                 gpio-controller;
 478                                 #gpio-cells = <2>;
 479                                 interrupt-controller;
 480                                 #interrupt-cells = <2>;
 481                         };
 482
 483                         gpio6: gpio@020b0000 {
 484                                 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
 485                                 reg = <0x020b0000 0x4000>;
 486                                 interrupts = <0 76 IRQ_TYPE_LEVEL_HIGH>,
 487                                              <0 77 IRQ_TYPE_LEVEL_HIGH>;
 488                                 gpio-controller;
 489                                 #gpio-cells = <2>;
 490                                 interrupt-controller;
 491                                 #interrupt-cells = <2>;
 492                         };
 493
 494                         gpio7: gpio@020b4000 {
 495                                 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
 496                                 reg = <0x020b4000 0x4000>;
 497                                 interrupts = <0 78 IRQ_TYPE_LEVEL_HIGH>,
 498                                              <0 79 IRQ_TYPE_LEVEL_HIGH>;
 499                                 gpio-controller;
 500                                 #gpio-cells = <2>;
 501                                 interrupt-controller;
 502                                 #interrupt-cells = <2>;
 503                         };
 504
 505                         kpp: kpp@020b8000 {
 506                                 compatible = "fsl,imx6q-kpp", "fsl,imx21-kpp";
 507                                 reg = <0x020b8000 0x4000>;
 508                                 interrupts = <0 82 IRQ_TYPE_LEVEL_HIGH>;
 509                                 clocks = <&clks IMX6QDL_CLK_IPG>;
 510                                 status = "disabled";
 511                         };
 512
 513                         wdog1: wdog@020bc000 {
 514                                 compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
 515                                 reg = <0x020bc000 0x4000>;
 516                                 interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>;
 517                                 clocks = <&clks IMX6QDL_CLK_DUMMY>;
 518                         };
 519
 520                         wdog2: wdog@020c0000 {
 521                                 compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
 522                                 reg = <0x020c0000 0x4000>;
 523                                 interrupts = <0 81 IRQ_TYPE_LEVEL_HIGH>;
 524                                 clocks = <&clks IMX6QDL_CLK_DUMMY>;
 525                                 status = "disabled";
 526                         };
 527
 528                         clks: ccm@020c4000 {
 529                                 compatible = "fsl,imx6q-ccm";
 530                                 reg = <0x020c4000 0x4000>;
 531                                 interrupts = <0 87 IRQ_TYPE_LEVEL_HIGH>,
 532                                              <0 88 IRQ_TYPE_LEVEL_HIGH>;
 533                                 #clock-cells = <1>;
 534                         };
 535
 536                         anatop: anatop@020c8000 {
 537                                 compatible = "fsl,imx6q-anatop", "syscon", "simple-bus";
 538                                 reg = <0x020c8000 0x1000>;
 539                                 interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>,
 540                                              <0 54 IRQ_TYPE_LEVEL_HIGH>,
 541                                              <0 127 IRQ_TYPE_LEVEL_HIGH>;
 542
 543                                 regulator-1p1@110 {
 544                                         compatible = "fsl,anatop-regulator";
 545                                         regulator-name = "vdd1p1";
 546                                         regulator-min-microvolt = <800000>;
 547                                         regulator-max-microvolt = <1375000>;
 548                                         regulator-always-on;
 549                                         anatop-reg-offset = <0x110>;
 550                                         anatop-vol-bit-shift = <8>;
 551                                         anatop-vol-bit-width = <5>;
 552                                         anatop-min-bit-val = <4>;
 553                                         anatop-min-voltage = <800000>;
 554                                         anatop-max-voltage = <1375000>;
 555                                 };
 556
 557                                 regulator-3p0@120 {
 558                                         compatible = "fsl,anatop-regulator";
 559                                         regulator-name = "vdd3p0";
 560                                         regulator-min-microvolt = <2800000>;
 561                                         regulator-max-microvolt = <3150000>;
 562                                         regulator-always-on;
 563                                         anatop-reg-offset = <0x120>;
 564                                         anatop-vol-bit-shift = <8>;
 565                                         anatop-vol-bit-width = <5>;
 566                                         anatop-min-bit-val = <0>;
 567                                         anatop-min-voltage = <2625000>;
 568                                         anatop-max-voltage = <3400000>;
 569                                 };
 570
 571                                 regulator-2p5@130 {
 572                                         compatible = "fsl,anatop-regulator";
 573                                         regulator-name = "vdd2p5";
 574                                         regulator-min-microvolt = <2000000>;
 575                                         regulator-max-microvolt = <2750000>;
 576                                         regulator-always-on;
 577                                         anatop-reg-offset = <0x130>;
 578                                         anatop-vol-bit-shift = <8>;
 579                                         anatop-vol-bit-width = <5>;
 580                                         anatop-min-bit-val = <0>;
 581                                         anatop-min-voltage = <2000000>;
 582                                         anatop-max-voltage = <2750000>;
 583                                 };
 584
 585                                 reg_arm: regulator-vddcore@140 {
 586                                         compatible = "fsl,anatop-regulator";
 587                                         regulator-name = "vddarm";
 588                                         regulator-min-microvolt = <725000>;
 589                                         regulator-max-microvolt = <1450000>;
 590                                         regulator-always-on;
 591                                         anatop-reg-offset = <0x140>;
 592                                         anatop-vol-bit-shift = <0>;
 593                                         anatop-vol-bit-width = <5>;
 594                                         anatop-delay-reg-offset = <0x170>;
 595                                         anatop-delay-bit-shift = <24>;
 596                                         anatop-delay-bit-width = <2>;
 597                                         anatop-min-bit-val = <1>;
 598                                         anatop-min-voltage = <725000>;
 599                                         anatop-max-voltage = <1450000>;
 600                                 };
 601
 602                                 reg_pu: regulator-vddpu@140 {
 603                                         compatible = "fsl,anatop-regulator";
 604                                         regulator-name = "vddpu";
 605                                         regulator-min-microvolt = <725000>;
 606                                         regulator-max-microvolt = <1450000>;
 607                                         regulator-enable-ramp-delay = <150>;
 608                                         anatop-reg-offset = <0x140>;
 609                                         anatop-vol-bit-shift = <9>;
 610                                         anatop-vol-bit-width = <5>;
 611                                         anatop-delay-reg-offset = <0x170>;
 612                                         anatop-delay-bit-shift = <26>;
 613                                         anatop-delay-bit-width = <2>;
 614                                         anatop-min-bit-val = <1>;
 615                                         anatop-min-voltage = <725000>;
 616                                         anatop-max-voltage = <1450000>;
 617                                 };
 618
 619                                 reg_soc: regulator-vddsoc@140 {
 620                                         compatible = "fsl,anatop-regulator";
 621                                         regulator-name = "vddsoc";
 622                                         regulator-min-microvolt = <725000>;
 623                                         regulator-max-microvolt = <1450000>;
 624                                         regulator-always-on;
 625                                         anatop-reg-offset = <0x140>;
 626                                         anatop-vol-bit-shift = <18>;
 627                                         anatop-vol-bit-width = <5>;
 628                                         anatop-delay-reg-offset = <0x170>;
 629                                         anatop-delay-bit-shift = <28>;
 630                                         anatop-delay-bit-width = <2>;
 631                                         anatop-min-bit-val = <1>;
 632                                         anatop-min-voltage = <725000>;
 633                                         anatop-max-voltage = <1450000>;
 634                                 };
 635                         };
 636
 637                         tempmon: tempmon {
 638                                 compatible = "fsl,imx6q-tempmon";
 639                                 interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>;
 640                                 fsl,tempmon = <&anatop>;
 641                                 fsl,tempmon-data = <&ocotp>;
 642                                 clocks = <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
 643                         };
 644
 645                         usbphy1: usbphy@020c9000 {
 646                                 compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
 647                                 reg = <0x020c9000 0x1000>;
 648                                 interrupts = <0 44 IRQ_TYPE_LEVEL_HIGH>;
 649                                 clocks = <&clks IMX6QDL_CLK_USBPHY1>;
 650                                 fsl,anatop = <&anatop>;
 651                         };
 652
 653                         usbphy2: usbphy@020ca000 {
 654                                 compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
 655                                 reg = <0x020ca000 0x1000>;
 656                                 interrupts = <0 45 IRQ_TYPE_LEVEL_HIGH>;
 657                                 clocks = <&clks IMX6QDL_CLK_USBPHY2>;
 658                                 fsl,anatop = <&anatop>;
 659                         };
 660
 661                         snvs@020cc000 {
 662                                 compatible = "fsl,sec-v4.0-mon", "simple-bus";
 663                                 #address-cells = <1>;
 664                                 #size-cells = <1>;
 665                                 ranges = <0 0x020cc000 0x4000>;
 666
 667                                 snvs_rtc: snvs-rtc-lp@34 {
 668                                         compatible = "fsl,sec-v4.0-mon-rtc-lp";
 669                                         reg = <0x34 0x58>;
 670                                         interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>,
 671                                                      <0 20 IRQ_TYPE_LEVEL_HIGH>;
 672                                 };
 673
 674                                 snvs_poweroff: snvs-poweroff@38 {
 675                                         compatible = "fsl,sec-v4.0-poweroff";
 676                                         reg = <0x38 0x4>;
 677                                         status = "disabled";
 678                                 };
 679                         };
 680
 681                         epit1: epit@020d0000 { /* EPIT1 */
 682                                 reg = <0x020d0000 0x4000>;
 683                                 interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH>;
 684                         };
 685
 686                         epit2: epit@020d4000 { /* EPIT2 */
 687                                 reg = <0x020d4000 0x4000>;
 688                                 interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>;
 689                         };
 690
 691                         src: src@020d8000 {
 692                                 compatible = "fsl,imx6q-src", "fsl,imx51-src";
 693                                 reg = <0x020d8000 0x4000>;
 694                                 interrupts = <0 91 IRQ_TYPE_LEVEL_HIGH>,
 695                                              <0 96 IRQ_TYPE_LEVEL_HIGH>;
 696                                 #reset-cells = <1>;
 697                         };
 698
 699                         gpc: gpc@020dc000 {
 700                                 compatible = "fsl,imx6q-gpc";
 701                                 reg = <0x020dc000 0x4000>;
 702                                 interrupt-controller;
 703                                 #interrupt-cells = <3>;
 704                                 interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>,
 705                                              <0 90 IRQ_TYPE_LEVEL_HIGH>;
 706                                 interrupt-parent = <&intc>;
 707                                 pu-supply = <&reg_pu>;
 708                                 clocks = <&clks IMX6QDL_CLK_GPU3D_CORE>,
 709                                          <&clks IMX6QDL_CLK_GPU3D_SHADER>,
 710                                          <&clks IMX6QDL_CLK_GPU2D_CORE>,
 711                                          <&clks IMX6QDL_CLK_GPU2D_AXI>,
 712                                          <&clks IMX6QDL_CLK_OPENVG_AXI>,
 713                                          <&clks IMX6QDL_CLK_VPU_AXI>;
 714                                 #power-domain-cells = <1>;
 715                         };
 716
 717                         gpr: iomuxc-gpr@020e0000 {
 718                                 compatible = "fsl,imx6q-iomuxc-gpr", "syscon";
 719                                 reg = <0x020e0000 0x38>;
 720                         };
 721
 722                         iomuxc: iomuxc@020e0000 {
 723                                 compatible = "fsl,imx6dl-iomuxc", "fsl,imx6q-iomuxc";
 724                                 reg = <0x020e0000 0x4000>;
 725                         };
 726
 727                         ldb: ldb@020e0008 {
 728                                 #address-cells = <1>;
 729                                 #size-cells = <0>;
 730                                 compatible = "fsl,imx6q-ldb", "fsl,imx53-ldb";
 731                                 gpr = <&gpr>;
 732                                 status = "disabled";
 733
 734                                 lvds-channel@0 {
 735                                         #address-cells = <1>;
 736                                         #size-cells = <0>;
 737                                         reg = <0>;
 738                                         status = "disabled";
 739
 740                                         port@0 {
 741                                                 reg = <0>;
 742
 743                                                 lvds0_mux_0: endpoint {
 744                                                         remote-endpoint = <&ipu1_di0_lvds0>;
 745                                                 };
 746                                         };
 747
 748                                         port@1 {
 749                                                 reg = <1>;
 750
 751                                                 lvds0_mux_1: endpoint {
 752                                                         remote-endpoint = <&ipu1_di1_lvds0>;
 753                                                 };
 754                                         };
 755                                 };
 756
 757                                 lvds-channel@1 {
 758                                         #address-cells = <1>;
 759                                         #size-cells = <0>;
 760                                         reg = <1>;
 761                                         status = "disabled";
 762
 763                                         port@0 {
 764                                                 reg = <0>;
 765
 766                                                 lvds1_mux_0: endpoint {
 767                                                         remote-endpoint = <&ipu1_di0_lvds1>;
 768                                                 };
 769                                         };
 770
 771                                         port@1 {
 772                                                 reg = <1>;
 773
 774                                                 lvds1_mux_1: endpoint {
 775                                                         remote-endpoint = <&ipu1_di1_lvds1>;
 776                                                 };
 777                                         };
 778                                 };
 779                         };
 780
 781                         hdmi: hdmi@0120000 {
 782                                 #address-cells = <1>;
 783                                 #size-cells = <0>;
 784                                 reg = <0x00120000 0x9000>;
 785                                 interrupts = <0 115 0x04>;
 786                                 gpr = <&gpr>;
 787                                 clocks = <&clks IMX6QDL_CLK_HDMI_IAHB>,
 788                                          <&clks IMX6QDL_CLK_HDMI_ISFR>;
 789                                 clock-names = "iahb", "isfr";
 790                                 status = "disabled";
 791
 792                                 port@0 {
 793                                         reg = <0>;
 794
 795                                         hdmi_mux_0: endpoint {
 796                                                 remote-endpoint = <&ipu1_di0_hdmi>;
 797                                         };
 798                                 };
 799
 800                                 port@1 {
 801                                         reg = <1>;
 802
 803                                         hdmi_mux_1: endpoint {
 804                                                 remote-endpoint = <&ipu1_di1_hdmi>;
 805                                         };
 806                                 };
 807                         };
 808
 809                         dcic1: dcic@020e4000 {
 810                                 reg = <0x020e4000 0x4000>;
 811                                 interrupts = <0 124 IRQ_TYPE_LEVEL_HIGH>;
 812                         };
 813
 814                         dcic2: dcic@020e8000 {
 815                                 reg = <0x020e8000 0x4000>;
 816                                 interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH>;
 817                         };
 818
 819                         sdma: sdma@020ec000 {
 820                                 compatible = "fsl,imx6q-sdma", "fsl,imx35-sdma";
 821                                 reg = <0x020ec000 0x4000>;
 822                                 interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>;
 823                                 clocks = <&clks IMX6QDL_CLK_SDMA>,
 824                                          <&clks IMX6QDL_CLK_SDMA>;
 825                                 clock-names = "ipg", "ahb";
 826                                 #dma-cells = <3>;
 827                                 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
 828                         };
 829                 };
 830
 831                 aips-bus@02100000 { /* AIPS2 */
 832                         compatible = "fsl,aips-bus", "simple-bus";
 833                         #address-cells = <1>;
 834                         #size-cells = <1>;
 835                         reg = <0x02100000 0x100000>;
 836                         ranges;
 837
 838                         caam@02100000 {
 839                                 reg = <0x02100000 0x40000>;
 840                                 interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>,
 841                                              <0 106 IRQ_TYPE_LEVEL_HIGH>;
 842                         };
 843
 844                         aipstz@0217c000 { /* AIPSTZ2 */
 845                                 reg = <0x0217c000 0x4000>;
 846                         };
 847
 848                         usbotg: usb@02184000 {
 849                                 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
 850                                 reg = <0x02184000 0x200>;
 851                                 interrupts = <0 43 IRQ_TYPE_LEVEL_HIGH>;
 852                                 clocks = <&clks IMX6QDL_CLK_USBOH3>;
 853                                 fsl,usbphy = <&usbphy1>;
 854                                 fsl,usbmisc = <&usbmisc 0>;
 855                                 status = "disabled";
 856                         };
 857
 858                         usbh1: usb@02184200 {
 859                                 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
 860                                 reg = <0x02184200 0x200>;
 861                                 interrupts = <0 40 IRQ_TYPE_LEVEL_HIGH>;
 862                                 clocks = <&clks IMX6QDL_CLK_USBOH3>;
 863                                 fsl,usbphy = <&usbphy2>;
 864                                 fsl,usbmisc = <&usbmisc 1>;
 865                                 dr_mode = "host";
 866                                 status = "disabled";
 867                         };
 868
 869                         usbh2: usb@02184400 {
 870                                 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
 871                                 reg = <0x02184400 0x200>;
 872                                 interrupts = <0 41 IRQ_TYPE_LEVEL_HIGH>;
 873                                 clocks = <&clks IMX6QDL_CLK_USBOH3>;
 874                                 fsl,usbmisc = <&usbmisc 2>;
 875                                 dr_mode = "host";
 876                                 status = "disabled";
 877                         };
 878
 879                         usbh3: usb@02184600 {
 880                                 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
 881                                 reg = <0x02184600 0x200>;
 882                                 interrupts = <0 42 IRQ_TYPE_LEVEL_HIGH>;
 883                                 clocks = <&clks IMX6QDL_CLK_USBOH3>;
 884                                 fsl,usbmisc = <&usbmisc 3>;
 885                                 dr_mode = "host";
 886                                 status = "disabled";
 887                         };
 888
 889                         usbmisc: usbmisc@02184800 {
 890                                 #index-cells = <1>;
 891                                 compatible = "fsl,imx6q-usbmisc";
 892                                 reg = <0x02184800 0x200>;
 893                                 clocks = <&clks IMX6QDL_CLK_USBOH3>;
 894                         };
 895
 896                         fec: ethernet@02188000 {
 897                                 compatible = "fsl,imx6q-fec";
 898                                 reg = <0x02188000 0x4000>;
 899                                 interrupts-extended =
 900                                         <&intc 0 118 IRQ_TYPE_LEVEL_HIGH>,
 901                                         <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>;
 902                                 clocks = <&clks IMX6QDL_CLK_ENET>,
 903                                          <&clks IMX6QDL_CLK_ENET>,
 904                                          <&clks IMX6QDL_CLK_ENET_REF>;
 905                                 clock-names = "ipg", "ahb", "ptp";
 906                                 status = "disabled";
 907                         };
 908
 909                         mlb@0218c000 {
 910                                 reg = <0x0218c000 0x4000>;
 911                                 interrupts = <0 53 IRQ_TYPE_LEVEL_HIGH>,
 912                                              <0 117 IRQ_TYPE_LEVEL_HIGH>,
 913                                              <0 126 IRQ_TYPE_LEVEL_HIGH>;
 914                         };
 915
 916                         usdhc1: usdhc@02190000 {
 917                                 compatible = "fsl,imx6q-usdhc";
 918                                 reg = <0x02190000 0x4000>;
 919                                 interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>;
 920                                 clocks = <&clks IMX6QDL_CLK_USDHC1>,
 921                                          <&clks IMX6QDL_CLK_USDHC1>,
 922                                          <&clks IMX6QDL_CLK_USDHC1>;
 923                                 clock-names = "ipg", "ahb", "per";
 924                                 bus-width = <4>;
 925                                 status = "disabled";
 926                         };
 927
 928                         usdhc2: usdhc@02194000 {
 929                                 compatible = "fsl,imx6q-usdhc";
 930                                 reg = <0x02194000 0x4000>;
 931                                 interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>;
 932                                 clocks = <&clks IMX6QDL_CLK_USDHC2>,
 933                                          <&clks IMX6QDL_CLK_USDHC2>,
 934                                          <&clks IMX6QDL_CLK_USDHC2>;
 935                                 clock-names = "ipg", "ahb", "per";
 936                                 bus-width = <4>;
 937                                 status = "disabled";
 938                         };
 939
 940                         usdhc3: usdhc@02198000 {
 941                                 compatible = "fsl,imx6q-usdhc";
 942                                 reg = <0x02198000 0x4000>;
 943                                 interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>;
 944                                 clocks = <&clks IMX6QDL_CLK_USDHC3>,
 945                                          <&clks IMX6QDL_CLK_USDHC3>,
 946                                          <&clks IMX6QDL_CLK_USDHC3>;
 947                                 clock-names = "ipg", "ahb", "per";
 948                                 bus-width = <4>;
 949                                 status = "disabled";
 950                         };
 951
 952                         usdhc4: usdhc@0219c000 {
 953                                 compatible = "fsl,imx6q-usdhc";
 954                                 reg = <0x0219c000 0x4000>;
 955                                 interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>;
 956                                 clocks = <&clks IMX6QDL_CLK_USDHC4>,
 957                                          <&clks IMX6QDL_CLK_USDHC4>,
 958                                          <&clks IMX6QDL_CLK_USDHC4>;
 959                                 clock-names = "ipg", "ahb", "per";
 960                                 bus-width = <4>;
 961                                 status = "disabled";
 962                         };
 963
 964                         i2c1: i2c@021a0000 {
 965                                 #address-cells = <1>;
 966                                 #size-cells = <0>;
 967                                 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
 968                                 reg = <0x021a0000 0x4000>;
 969                                 interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>;
 970                                 clocks = <&clks IMX6QDL_CLK_I2C1>;
 971                                 status = "disabled";
 972                         };
 973
 974                         i2c2: i2c@021a4000 {
 975                                 #address-cells = <1>;
 976                                 #size-cells = <0>;
 977                                 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
 978                                 reg = <0x021a4000 0x4000>;
 979                                 interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>;
 980                                 clocks = <&clks IMX6QDL_CLK_I2C2>;
 981                                 status = "disabled";
 982                         };
 983
 984                         i2c3: i2c@021a8000 {
 985                                 #address-cells = <1>;
 986                                 #size-cells = <0>;
 987                                 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
 988                                 reg = <0x021a8000 0x4000>;
 989                                 interrupts = <0 38 IRQ_TYPE_LEVEL_HIGH>;
 990                                 clocks = <&clks IMX6QDL_CLK_I2C3>;
 991                                 status = "disabled";
 992                         };
 993
 994                         romcp@021ac000 {
 995                                 reg = <0x021ac000 0x4000>;
 996                         };
 997
 998                         mmdc0: mmdc@021b0000 { /* MMDC0 */
 999                                 compatible = "fsl,imx6q-mmdc";
1000                                 reg = <0x021b0000 0x4000>;
1001                         };
1002
1003                         mmdc1: mmdc@021b4000 { /* MMDC1 */
1004                                 reg = <0x021b4000 0x4000>;
1005                         };
1006
1007                         weim: weim@021b8000 {
1008                                 compatible = "fsl,imx6q-weim";
1009                                 reg = <0x021b8000 0x4000>;
1010                                 interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>;
1011                                 clocks = <&clks IMX6QDL_CLK_EIM_SLOW>;
1012                         };
1013
1014                         ocotp: ocotp@021bc000 {
1015                                 compatible = "fsl,imx6q-ocotp", "syscon";
1016                                 reg = <0x021bc000 0x4000>;
1017                         };
1018
1019                         tzasc@021d0000 { /* TZASC1 */
1020                                 reg = <0x021d0000 0x4000>;
1021                                 interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>;
1022                         };
1023
1024                         tzasc@021d4000 { /* TZASC2 */
1025                                 reg = <0x021d4000 0x4000>;
1026                                 interrupts = <0 109 IRQ_TYPE_LEVEL_HIGH>;
1027                         };
1028
1029                         audmux: audmux@021d8000 {
1030                                 compatible = "fsl,imx6q-audmux", "fsl,imx31-audmux";
1031                                 reg = <0x021d8000 0x4000>;
1032                                 status = "disabled";
1033                         };
1034
1035                         mipi_csi: mipi@021dc000 {
1036                                 reg = <0x021dc000 0x4000>;
1037                         };
1038
1039                         mipi_dsi: mipi@021e0000 {
1040                                 #address-cells = <1>;
1041                                 #size-cells = <0>;
1042                                 reg = <0x021e0000 0x4000>;
1043                                 status = "disabled";
1044
1045                                 ports {
1046                                         #address-cells = <1>;
1047                                         #size-cells = <0>;
1048
1049                                         port@0 {
1050                                                 reg = <0>;
1051
1052                                                 mipi_mux_0: endpoint {
1053                                                         remote-endpoint = <&ipu1_di0_mipi>;
1054                                                 };
1055                                         };
1056
1057                                         port@1 {
1058                                                 reg = <1>;
1059
1060                                                 mipi_mux_1: endpoint {
1061                                                         remote-endpoint = <&ipu1_di1_mipi>;
1062                                                 };
1063                                         };
1064                                 };
1065                         };
1066
1067                         vdoa@021e4000 {
1068                                 reg = <0x021e4000 0x4000>;
1069                                 interrupts = <0 18 IRQ_TYPE_LEVEL_HIGH>;
1070                         };
1071
1072                         uart2: serial@021e8000 {
1073                                 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1074                                 reg = <0x021e8000 0x4000>;
1075                                 interrupts = <0 27 IRQ_TYPE_LEVEL_HIGH>;
1076                                 clocks = <&clks IMX6QDL_CLK_UART_IPG>,
1077                                          <&clks IMX6QDL_CLK_UART_SERIAL>;
1078                                 clock-names = "ipg", "per";
1079                                 dmas = <&sdma 27 4 0>, <&sdma 28 4 0>;
1080                                 dma-names = "rx", "tx";
1081                                 status = "disabled";
1082                         };
1083
1084                         uart3: serial@021ec000 {
1085                                 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1086                                 reg = <0x021ec000 0x4000>;
1087                                 interrupts = <0 28 IRQ_TYPE_LEVEL_HIGH>;
1088                                 clocks = <&clks IMX6QDL_CLK_UART_IPG>,
1089                                          <&clks IMX6QDL_CLK_UART_SERIAL>;
1090                                 clock-names = "ipg", "per";
1091                                 dmas = <&sdma 29 4 0>, <&sdma 30 4 0>;
1092                                 dma-names = "rx", "tx";
1093                                 status = "disabled";
1094                         };
1095
1096                         uart4: serial@021f0000 {
1097                                 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1098                                 reg = <0x021f0000 0x4000>;
1099                                 interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>;
1100                                 clocks = <&clks IMX6QDL_CLK_UART_IPG>,
1101                                          <&clks IMX6QDL_CLK_UART_SERIAL>;
1102                                 clock-names = "ipg", "per";
1103                                 dmas = <&sdma 31 4 0>, <&sdma 32 4 0>;
1104                                 dma-names = "rx", "tx";
1105                                 status = "disabled";
1106                         };
1107
1108                         uart5: serial@021f4000 {
1109                                 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1110                                 reg = <0x021f4000 0x4000>;
1111                                 interrupts = <0 30 IRQ_TYPE_LEVEL_HIGH>;
1112                                 clocks = <&clks IMX6QDL_CLK_UART_IPG>,
1113                                          <&clks IMX6QDL_CLK_UART_SERIAL>;
1114                                 clock-names = "ipg", "per";
1115                                 dmas = <&sdma 33 4 0>, <&sdma 34 4 0>;
1116                                 dma-names = "rx", "tx";
1117                                 status = "disabled";
1118                         };
1119                 };
1120
1121                 ipu1: ipu@02400000 {
1122                         #address-cells = <1>;
1123                         #size-cells = <0>;
1124                         compatible = "fsl,imx6q-ipu";
1125                         reg = <0x02400000 0x400000>;
1126                         interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>,
1127                                      <0 5 IRQ_TYPE_LEVEL_HIGH>;
1128                         clocks = <&clks IMX6QDL_CLK_IPU1>,
1129                                  <&clks IMX6QDL_CLK_IPU1_DI0>,
1130                                  <&clks IMX6QDL_CLK_IPU1_DI1>;
1131                         clock-names = "bus", "di0", "di1";
1132                         resets = <&src 2>;
1133
1134                         ipu1_csi0: port@0 {
1135                                 reg = <0>;
1136                         };
1137
1138                         ipu1_csi1: port@1 {
1139                                 reg = <1>;
1140                         };
1141
1142                         ipu1_di0: port@2 {
1143                                 #address-cells = <1>;
1144                                 #size-cells = <0>;
1145                                 reg = <2>;
1146
1147                                 ipu1_di0_disp0: endpoint@0 {
1148                                 };
1149
1150                                 ipu1_di0_hdmi: endpoint@1 {
1151                                         remote-endpoint = <&hdmi_mux_0>;
1152                                 };
1153
1154                                 ipu1_di0_mipi: endpoint@2 {
1155                                         remote-endpoint = <&mipi_mux_0>;
1156                                 };
1157
1158                                 ipu1_di0_lvds0: endpoint@3 {
1159                                         remote-endpoint = <&lvds0_mux_0>;
1160                                 };
1161
1162                                 ipu1_di0_lvds1: endpoint@4 {
1163                                         remote-endpoint = <&lvds1_mux_0>;
1164                                 };
1165                         };
1166
1167                         ipu1_di1: port@3 {
1168                                 #address-cells = <1>;
1169                                 #size-cells = <0>;
1170                                 reg = <3>;
1171
1172                                 ipu1_di0_disp1: endpoint@0 {
1173                                 };
1174
1175                                 ipu1_di1_hdmi: endpoint@1 {
1176                                         remote-endpoint = <&hdmi_mux_1>;
1177                                 };
1178
1179                                 ipu1_di1_mipi: endpoint@2 {
1180                                         remote-endpoint = <&mipi_mux_1>;
1181                                 };
1182
1183                                 ipu1_di1_lvds0: endpoint@3 {
1184                                         remote-endpoint = <&lvds0_mux_1>;
1185                                 };
1186
1187                                 ipu1_di1_lvds1: endpoint@4 {
1188                                         remote-endpoint = <&lvds1_mux_1>;
1189                                 };
1190                         };
1191                 };
1192         };
1193 };