kernel/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi

   1 /*
   2  * Copyright 2012 Freescale Semiconductor, Inc.
   3  * Copyright 2011 Linaro Ltd.
   4  *
   5  * The code contained herein is licensed under the GNU General Public
   6  * License. You may obtain a copy of the GNU General Public License
   7  * Version 2 or later at the following locations:
   8  *
   9  * http://www.opensource.org/licenses/gpl-license.html
  10  * http://www.gnu.org/copyleft/gpl.html
  11  */
  12
  13 #include <dt-bindings/gpio/gpio.h>
  14
  15 / {
  16         memory {
  17                 reg = <0x10000000 0x80000000>;
  18         };
  19
  20         leds {
  21                 compatible = "gpio-leds";
  22                 pinctrl-names = "default";
  23                 pinctrl-0 = <&pinctrl_gpio_leds>;
  24
  25                 user {
  26                         label = "debug";
  27                         gpios = <&gpio5 15 GPIO_ACTIVE_HIGH>;
  28                 };
  29         };
  30
  31         sound-spdif {
  32                 compatible = "fsl,imx-audio-spdif",
  33                            "fsl,imx-sabreauto-spdif";
  34                 model = "imx-spdif";
  35                 spdif-controller = <&spdif>;
  36                 spdif-in;
  37         };
  38
  39         backlight {
  40                 compatible = "pwm-backlight";
  41                 pwms = <&pwm3 0 5000000>;
  42                 brightness-levels = <0 4 8 16 32 64 128 255>;
  43                 default-brightness-level = <7>;
  44                 status = "okay";
  45         };
  46 };
  47
  48 &ecspi1 {
  49         fsl,spi-num-chipselects = <1>;
  50         cs-gpios = <&gpio3 19 0>;
  51         pinctrl-names = "default";
  52         pinctrl-0 = <&pinctrl_ecspi1 &pinctrl_ecspi1_cs>;
  53         status = "disabled"; /* pin conflict with WEIM NOR */
  54
  55         flash: m25p80@0 {
  56                 #address-cells = <1>;
  57                 #size-cells = <1>;
  58                 compatible = "st,m25p32";
  59                 spi-max-frequency = <20000000>;
  60                 reg = <0>;
  61         };
  62 };
  63
  64 &fec {
  65         pinctrl-names = "default";
  66         pinctrl-0 = <&pinctrl_enet>;
  67         phy-mode = "rgmii";
  68         interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>,
  69                               <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>;
  70         status = "okay";
  71 };
  72
  73 &gpmi {
  74         pinctrl-names = "default";
  75         pinctrl-0 = <&pinctrl_gpmi_nand>;
  76         status = "okay";
  77 };
  78
  79 &i2c2 {
  80         clock-frequency = <100000>;
  81         pinctrl-names = "default";
  82         pinctrl-0 = <&pinctrl_i2c2>;
  83         status = "okay";
  84
  85         pmic: pfuze100@08 {
  86                 compatible = "fsl,pfuze100";
  87                 reg = <0x08>;
  88
  89                 regulators {
  90                         sw1a_reg: sw1ab {
  91                                 regulator-min-microvolt = <300000>;
  92                                 regulator-max-microvolt = <1875000>;
  93                                 regulator-boot-on;
  94                                 regulator-always-on;
  95                                 regulator-ramp-delay = <6250>;
  96                         };
  97
  98                         sw1c_reg: sw1c {
  99                                 regulator-min-microvolt = <300000>;
 100                                 regulator-max-microvolt = <1875000>;
 101                                 regulator-boot-on;
 102                                 regulator-always-on;
 103                                 regulator-ramp-delay = <6250>;
 104                         };
 105
 106                         sw2_reg: sw2 {
 107                                 regulator-min-microvolt = <800000>;
 108                                 regulator-max-microvolt = <3300000>;
 109                                 regulator-boot-on;
 110                                 regulator-always-on;
 111                         };
 112
 113                         sw3a_reg: sw3a {
 114                                 regulator-min-microvolt = <400000>;
 115                                 regulator-max-microvolt = <1975000>;
 116                                 regulator-boot-on;
 117                                 regulator-always-on;
 118                         };
 119
 120                         sw3b_reg: sw3b {
 121                                 regulator-min-microvolt = <400000>;
 122                                 regulator-max-microvolt = <1975000>;
 123                                 regulator-boot-on;
 124                                 regulator-always-on;
 125                         };
 126
 127                         sw4_reg: sw4 {
 128                                 regulator-min-microvolt = <800000>;
 129                                 regulator-max-microvolt = <3300000>;
 130                         };
 131
 132                         swbst_reg: swbst {
 133                                 regulator-min-microvolt = <5000000>;
 134                                 regulator-max-microvolt = <5150000>;
 135                         };
 136
 137                         snvs_reg: vsnvs {
 138                                 regulator-min-microvolt = <1000000>;
 139                                 regulator-max-microvolt = <3000000>;
 140                                 regulator-boot-on;
 141                                 regulator-always-on;
 142                         };
 143
 144                         vref_reg: vrefddr {
 145                                 regulator-boot-on;
 146                                 regulator-always-on;
 147                         };
 148
 149                         vgen1_reg: vgen1 {
 150                                 regulator-min-microvolt = <800000>;
 151                                 regulator-max-microvolt = <1550000>;
 152                         };
 153
 154                         vgen2_reg: vgen2 {
 155                                 regulator-min-microvolt = <800000>;
 156                                 regulator-max-microvolt = <1550000>;
 157                         };
 158
 159                         vgen3_reg: vgen3 {
 160                                 regulator-min-microvolt = <1800000>;
 161                                 regulator-max-microvolt = <3300000>;
 162                         };
 163
 164                         vgen4_reg: vgen4 {
 165                                 regulator-min-microvolt = <1800000>;
 166                                 regulator-max-microvolt = <3300000>;
 167                                 regulator-always-on;
 168                         };
 169
 170                         vgen5_reg: vgen5 {
 171                                 regulator-min-microvolt = <1800000>;
 172                                 regulator-max-microvolt = <3300000>;
 173                                 regulator-always-on;
 174                         };
 175
 176                         vgen6_reg: vgen6 {
 177                                 regulator-min-microvolt = <1800000>;
 178                                 regulator-max-microvolt = <3300000>;
 179                                 regulator-always-on;
 180                         };
 181                 };
 182         };
 183 };
 184
 185 &i2c3 {
 186         pinctrl-names = "default";
 187         pinctrl-0 = <&pinctrl_i2c3>;
 188         status = "okay";
 189
 190         max7310_a: gpio@30 {
 191                 compatible = "maxim,max7310";
 192                 reg = <0x30>;
 193                 gpio-controller;
 194                 #gpio-cells = <2>;
 195         };
 196
 197         max7310_b: gpio@32 {
 198                 compatible = "maxim,max7310";
 199                 reg = <0x32>;
 200                 gpio-controller;
 201                 #gpio-cells = <2>;
 202         };
 203
 204         max7310_c: gpio@34 {
 205                 compatible = "maxim,max7310";
 206                 reg = <0x34>;
 207                 gpio-controller;
 208                 #gpio-cells = <2>;
 209         };
 210 };
 211
 212 &iomuxc {
 213         pinctrl-names = "default";
 214         pinctrl-0 = <&pinctrl_hog>;
 215
 216         imx6qdl-sabreauto {
 217                 pinctrl_hog: hoggrp {
 218                         fsl,pins = <
 219                                 MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x80000000
 220                                 MX6QDL_PAD_SD2_DAT2__GPIO1_IO13  0x80000000
 221                                 MX6QDL_PAD_GPIO_18__SD3_VSELECT 0x17059
 222                         >;
 223                 };
 224
 225                 pinctrl_ecspi1: ecspi1grp {
 226                         fsl,pins = <
 227                                 MX6QDL_PAD_EIM_D17__ECSPI1_MISO         0x100b1
 228                                 MX6QDL_PAD_EIM_D18__ECSPI1_MOSI         0x100b1
 229                                 MX6QDL_PAD_EIM_D16__ECSPI1_SCLK         0x100b1
 230                         >;
 231                 };
 232
 233                 pinctrl_ecspi1_cs: ecspi1cs {
 234                         fsl,pins = <
 235                                 MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x80000000
 236                         >;
 237                 };
 238
 239                 pinctrl_enet: enetgrp {
 240                         fsl,pins = <
 241                                 MX6QDL_PAD_KEY_COL1__ENET_MDIO          0x1b0b0
 242                                 MX6QDL_PAD_KEY_COL2__ENET_MDC           0x1b0b0
 243                                 MX6QDL_PAD_RGMII_TXC__RGMII_TXC         0x1b0b0
 244                                 MX6QDL_PAD_RGMII_TD0__RGMII_TD0         0x1b0b0
 245                                 MX6QDL_PAD_RGMII_TD1__RGMII_TD1         0x1b0b0
 246                                 MX6QDL_PAD_RGMII_TD2__RGMII_TD2         0x1b0b0
 247                                 MX6QDL_PAD_RGMII_TD3__RGMII_TD3         0x1b0b0
 248                                 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL   0x1b0b0
 249                                 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK    0x1b0b0
 250                                 MX6QDL_PAD_RGMII_RXC__RGMII_RXC         0x1b0b0
 251                                 MX6QDL_PAD_RGMII_RD0__RGMII_RD0         0x1b0b0
 252                                 MX6QDL_PAD_RGMII_RD1__RGMII_RD1         0x1b0b0
 253                                 MX6QDL_PAD_RGMII_RD2__RGMII_RD2         0x1b0b0
 254                                 MX6QDL_PAD_RGMII_RD3__RGMII_RD3         0x1b0b0
 255                                 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL   0x1b0b0
 256                                 MX6QDL_PAD_GPIO_6__ENET_IRQ             0x000b1
 257                         >;
 258                 };
 259
 260                 pinctrl_gpio_leds: gpioledsgrp {
 261                         fsl,pins = <
 262                                 MX6QDL_PAD_DISP0_DAT21__GPIO5_IO15      0x80000000
 263                         >;
 264                 };
 265
 266                 pinctrl_gpmi_nand: gpminandgrp {
 267                         fsl,pins = <
 268                                 MX6QDL_PAD_NANDF_CLE__NAND_CLE          0xb0b1
 269                                 MX6QDL_PAD_NANDF_ALE__NAND_ALE          0xb0b1
 270                                 MX6QDL_PAD_NANDF_WP_B__NAND_WP_B        0xb0b1
 271                                 MX6QDL_PAD_NANDF_RB0__NAND_READY_B      0xb000
 272                                 MX6QDL_PAD_NANDF_CS0__NAND_CE0_B        0xb0b1
 273                                 MX6QDL_PAD_NANDF_CS1__NAND_CE1_B        0xb0b1
 274                                 MX6QDL_PAD_SD4_CMD__NAND_RE_B           0xb0b1
 275                                 MX6QDL_PAD_SD4_CLK__NAND_WE_B           0xb0b1
 276                                 MX6QDL_PAD_NANDF_D0__NAND_DATA00        0xb0b1
 277                                 MX6QDL_PAD_NANDF_D1__NAND_DATA01        0xb0b1
 278                                 MX6QDL_PAD_NANDF_D2__NAND_DATA02        0xb0b1
 279                                 MX6QDL_PAD_NANDF_D3__NAND_DATA03        0xb0b1
 280                                 MX6QDL_PAD_NANDF_D4__NAND_DATA04        0xb0b1
 281                                 MX6QDL_PAD_NANDF_D5__NAND_DATA05        0xb0b1
 282                                 MX6QDL_PAD_NANDF_D6__NAND_DATA06        0xb0b1
 283                                 MX6QDL_PAD_NANDF_D7__NAND_DATA07        0xb0b1
 284                                 MX6QDL_PAD_SD4_DAT0__NAND_DQS           0x00b1
 285                         >;
 286                 };
 287
 288                 pinctrl_i2c2: i2c2grp {
 289                         fsl,pins = <
 290                                 MX6QDL_PAD_EIM_EB2__I2C2_SCL    0x4001b8b1
 291                                 MX6QDL_PAD_KEY_ROW3__I2C2_SDA   0x4001b8b1
 292                         >;
 293                 };
 294
 295                 pinctrl_i2c3: i2c3grp {
 296                         fsl,pins = <
 297                                 MX6QDL_PAD_GPIO_3__I2C3_SCL  0x4001b8b1
 298                                 MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1
 299                         >;
 300                 };
 301
 302                 pinctrl_pwm3: pwm1grp {
 303                         fsl,pins = <
 304                                 MX6QDL_PAD_SD4_DAT1__PWM3_OUT           0x1b0b1
 305                         >;
 306                 };
 307
 308                 pinctrl_spdif: spdifgrp {
 309                         fsl,pins = <
 310                                 MX6QDL_PAD_KEY_COL3__SPDIF_IN 0x1b0b0
 311                         >;
 312                 };
 313
 314                 pinctrl_uart4: uart4grp {
 315                         fsl,pins = <
 316                                 MX6QDL_PAD_KEY_COL0__UART4_TX_DATA      0x1b0b1
 317                                 MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA      0x1b0b1
 318                         >;
 319                 };
 320
 321                 pinctrl_usdhc3: usdhc3grp {
 322                         fsl,pins = <
 323                                 MX6QDL_PAD_SD3_CMD__SD3_CMD             0x17059
 324                                 MX6QDL_PAD_SD3_CLK__SD3_CLK             0x10059
 325                                 MX6QDL_PAD_SD3_DAT0__SD3_DATA0          0x17059
 326                                 MX6QDL_PAD_SD3_DAT1__SD3_DATA1          0x17059
 327                                 MX6QDL_PAD_SD3_DAT2__SD3_DATA2          0x17059
 328                                 MX6QDL_PAD_SD3_DAT3__SD3_DATA3          0x17059
 329                                 MX6QDL_PAD_SD3_DAT4__SD3_DATA4          0x17059
 330                                 MX6QDL_PAD_SD3_DAT5__SD3_DATA5          0x17059
 331                                 MX6QDL_PAD_SD3_DAT6__SD3_DATA6          0x17059
 332                                 MX6QDL_PAD_SD3_DAT7__SD3_DATA7          0x17059
 333                         >;
 334                 };
 335
 336                 pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
 337                         fsl,pins = <
 338                                 MX6QDL_PAD_SD3_CMD__SD3_CMD             0x170b9
 339                                 MX6QDL_PAD_SD3_CLK__SD3_CLK             0x100b9
 340                                 MX6QDL_PAD_SD3_DAT0__SD3_DATA0          0x170b9
 341                                 MX6QDL_PAD_SD3_DAT1__SD3_DATA1          0x170b9
 342                                 MX6QDL_PAD_SD3_DAT2__SD3_DATA2          0x170b9
 343                                 MX6QDL_PAD_SD3_DAT3__SD3_DATA3          0x170b9
 344                                 MX6QDL_PAD_SD3_DAT4__SD3_DATA4          0x170b9
 345                                 MX6QDL_PAD_SD3_DAT5__SD3_DATA5          0x170b9
 346                                 MX6QDL_PAD_SD3_DAT6__SD3_DATA6          0x170b9
 347                                 MX6QDL_PAD_SD3_DAT7__SD3_DATA7          0x170b9
 348                         >;
 349                 };
 350
 351                 pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
 352                         fsl,pins = <
 353                                 MX6QDL_PAD_SD3_CMD__SD3_CMD             0x170f9
 354                                 MX6QDL_PAD_SD3_CLK__SD3_CLK             0x100f9
 355                                 MX6QDL_PAD_SD3_DAT0__SD3_DATA0          0x170f9
 356                                 MX6QDL_PAD_SD3_DAT1__SD3_DATA1          0x170f9
 357                                 MX6QDL_PAD_SD3_DAT2__SD3_DATA2          0x170f9
 358                                 MX6QDL_PAD_SD3_DAT3__SD3_DATA3          0x170f9
 359                                 MX6QDL_PAD_SD3_DAT4__SD3_DATA4          0x170f9
 360                                 MX6QDL_PAD_SD3_DAT5__SD3_DATA5          0x170f9
 361                                 MX6QDL_PAD_SD3_DAT6__SD3_DATA6          0x170f9
 362                                 MX6QDL_PAD_SD3_DAT7__SD3_DATA7          0x170f9
 363                         >;
 364                 };
 365
 366                 pinctrl_weim_cs0: weimcs0grp {
 367                         fsl,pins = <
 368                                 MX6QDL_PAD_EIM_CS0__EIM_CS0_B           0xb0b1
 369                         >;
 370                 };
 371
 372                 pinctrl_weim_nor: weimnorgrp {
 373                         fsl,pins = <
 374                                 MX6QDL_PAD_EIM_OE__EIM_OE_B             0xb0b1
 375                                 MX6QDL_PAD_EIM_RW__EIM_RW               0xb0b1
 376                                 MX6QDL_PAD_EIM_WAIT__EIM_WAIT_B         0xb060
 377                                 MX6QDL_PAD_EIM_D16__EIM_DATA16          0x1b0b0
 378                                 MX6QDL_PAD_EIM_D17__EIM_DATA17          0x1b0b0
 379                                 MX6QDL_PAD_EIM_D18__EIM_DATA18          0x1b0b0
 380                                 MX6QDL_PAD_EIM_D19__EIM_DATA19          0x1b0b0
 381                                 MX6QDL_PAD_EIM_D20__EIM_DATA20          0x1b0b0
 382                                 MX6QDL_PAD_EIM_D21__EIM_DATA21          0x1b0b0
 383                                 MX6QDL_PAD_EIM_D22__EIM_DATA22          0x1b0b0
 384                                 MX6QDL_PAD_EIM_D23__EIM_DATA23          0x1b0b0
 385                                 MX6QDL_PAD_EIM_D24__EIM_DATA24          0x1b0b0
 386                                 MX6QDL_PAD_EIM_D25__EIM_DATA25          0x1b0b0
 387                                 MX6QDL_PAD_EIM_D26__EIM_DATA26          0x1b0b0
 388                                 MX6QDL_PAD_EIM_D27__EIM_DATA27          0x1b0b0
 389                                 MX6QDL_PAD_EIM_D28__EIM_DATA28          0x1b0b0
 390                                 MX6QDL_PAD_EIM_D29__EIM_DATA29          0x1b0b0
 391                                 MX6QDL_PAD_EIM_D30__EIM_DATA30          0x1b0b0
 392                                 MX6QDL_PAD_EIM_D31__EIM_DATA31          0x1b0b0
 393                                 MX6QDL_PAD_EIM_A23__EIM_ADDR23          0xb0b1
 394                                 MX6QDL_PAD_EIM_A22__EIM_ADDR22          0xb0b1
 395                                 MX6QDL_PAD_EIM_A21__EIM_ADDR21          0xb0b1
 396                                 MX6QDL_PAD_EIM_A20__EIM_ADDR20          0xb0b1
 397                                 MX6QDL_PAD_EIM_A19__EIM_ADDR19          0xb0b1
 398                                 MX6QDL_PAD_EIM_A18__EIM_ADDR18          0xb0b1
 399                                 MX6QDL_PAD_EIM_A17__EIM_ADDR17          0xb0b1
 400                                 MX6QDL_PAD_EIM_A16__EIM_ADDR16          0xb0b1
 401                                 MX6QDL_PAD_EIM_DA15__EIM_AD15           0xb0b1
 402                                 MX6QDL_PAD_EIM_DA14__EIM_AD14           0xb0b1
 403                                 MX6QDL_PAD_EIM_DA13__EIM_AD13           0xb0b1
 404                                 MX6QDL_PAD_EIM_DA12__EIM_AD12           0xb0b1
 405                                 MX6QDL_PAD_EIM_DA11__EIM_AD11           0xb0b1
 406                                 MX6QDL_PAD_EIM_DA10__EIM_AD10           0xb0b1
 407                                 MX6QDL_PAD_EIM_DA9__EIM_AD09            0xb0b1
 408                                 MX6QDL_PAD_EIM_DA8__EIM_AD08            0xb0b1
 409                                 MX6QDL_PAD_EIM_DA7__EIM_AD07            0xb0b1
 410                                 MX6QDL_PAD_EIM_DA6__EIM_AD06            0xb0b1
 411                                 MX6QDL_PAD_EIM_DA5__EIM_AD05            0xb0b1
 412                                 MX6QDL_PAD_EIM_DA4__EIM_AD04            0xb0b1
 413                                 MX6QDL_PAD_EIM_DA3__EIM_AD03            0xb0b1
 414                                 MX6QDL_PAD_EIM_DA2__EIM_AD02            0xb0b1
 415                                 MX6QDL_PAD_EIM_DA1__EIM_AD01            0xb0b1
 416                                 MX6QDL_PAD_EIM_DA0__EIM_AD00            0xb0b1
 417                         >;
 418                 };
 419         };
 420 };
 421
 422 &ldb {
 423         status = "okay";
 424
 425         lvds-channel@0 {
 426                 fsl,data-mapping = "spwg";
 427                 fsl,data-width = <18>;
 428                 status = "okay";
 429
 430                 display-timings {
 431                         native-mode = <&timing0>;
 432                         timing0: hsd100pxn1 {
 433                                 clock-frequency = <65000000>;
 434                                 hactive = <1024>;
 435                                 vactive = <768>;
 436                                 hback-porch = <220>;
 437                                 hfront-porch = <40>;
 438                                 vback-porch = <21>;
 439                                 vfront-porch = <7>;
 440                                 hsync-len = <60>;
 441                                 vsync-len = <10>;
 442                         };
 443                 };
 444         };
 445 };
 446
 447 &pwm3 {
 448         pinctrl-names = "default";
 449         pinctrl-0 = <&pinctrl_pwm3>;
 450         status = "okay";
 451 };
 452
 453 &spdif {
 454         pinctrl-names = "default";
 455         pinctrl-0 = <&pinctrl_spdif>;
 456         status = "okay";
 457 };
 458
 459 &uart4 {
 460         pinctrl-names = "default";
 461         pinctrl-0 = <&pinctrl_uart4>;
 462         status = "okay";
 463 };
 464
 465 &usdhc3 {
 466         pinctrl-names = "default", "state_100mhz", "state_200mhz";
 467         pinctrl-0 = <&pinctrl_usdhc3>;
 468         pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
 469         pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
 470         cd-gpios = <&gpio6 15 0>;
 471         wp-gpios = <&gpio1 13 0>;
 472         status = "okay";
 473 };
 474
 475 &weim {
 476         pinctrl-names = "default";
 477         pinctrl-0 = <&pinctrl_weim_nor &pinctrl_weim_cs0>;
 478         #address-cells = <2>;
 479         #size-cells = <1>;
 480         ranges = <0 0 0x08000000 0x08000000>;
 481         status = "disabled"; /* pin conflict with SPI NOR */
 482
 483         nor@0,0 {
 484                 compatible = "cfi-flash";
 485                 reg = <0 0 0x02000000>;
 486                 #address-cells = <1>;
 487                 #size-cells = <1>;
 488                 bank-width = <2>;
 489                 fsl,weim-cs-timing = <0x00620081 0x00000001 0x1c022000
 490                                 0x0000c000 0x1404a38e 0x00000000>;
 491         };
 492 };