kernel/arch/arm/boot/dts/dra72-evm.dts

   1 /*
   2  * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  */
   8 /dts-v1/;
   9
  10 #include "dra72x.dtsi"
  11 #include <dt-bindings/gpio/gpio.h>
  12
  13 / {
  14         model = "TI DRA722";
  15         compatible = "ti,dra72-evm", "ti,dra722", "ti,dra72", "ti,dra7";
  16
  17         memory {
  18                 device_type = "memory";
  19                 reg = <0x80000000 0x40000000>; /* 1024 MB */
  20         };
  21
  22         evm_3v3: fixedregulator-evm_3v3 {
  23                 compatible = "regulator-fixed";
  24                 regulator-name = "evm_3v3";
  25                 regulator-min-microvolt = <3300000>;
  26                 regulator-max-microvolt = <3300000>;
  27         };
  28
  29         extcon_usb1: extcon_usb1 {
  30                 compatible = "linux,extcon-usb-gpio";
  31                 id-gpio = <&pcf_gpio_21 1 GPIO_ACTIVE_HIGH>;
  32         };
  33
  34         extcon_usb2: extcon_usb2 {
  35                 compatible = "linux,extcon-usb-gpio";
  36                 id-gpio = <&pcf_gpio_21 2 GPIO_ACTIVE_HIGH>;
  37         };
  38 };
  39
  40 &dra7_pmx_core {
  41         i2c1_pins: pinmux_i2c1_pins {
  42                 pinctrl-single,pins = <
  43                         0x400 (PIN_INPUT | MUX_MODE0) /* i2c1_sda.i2c1_sda */
  44                         0x404 (PIN_INPUT | MUX_MODE0) /* i2c1_scl.i2c1_scl */
  45                 >;
  46         };
  47
  48         nand_default: nand_default {
  49                 pinctrl-single,pins = <
  50                         0x0     (PIN_INPUT  | MUX_MODE0) /* gpmc_ad0 */
  51                         0x4     (PIN_INPUT  | MUX_MODE0) /* gpmc_ad1 */
  52                         0x8     (PIN_INPUT  | MUX_MODE0) /* gpmc_ad2 */
  53                         0xc     (PIN_INPUT  | MUX_MODE0) /* gpmc_ad3 */
  54                         0x10    (PIN_INPUT  | MUX_MODE0) /* gpmc_ad4 */
  55                         0x14    (PIN_INPUT  | MUX_MODE0) /* gpmc_ad5 */
  56                         0x18    (PIN_INPUT  | MUX_MODE0) /* gpmc_ad6 */
  57                         0x1c    (PIN_INPUT  | MUX_MODE0) /* gpmc_ad7 */
  58                         0x20    (PIN_INPUT  | MUX_MODE0) /* gpmc_ad8 */
  59                         0x24    (PIN_INPUT  | MUX_MODE0) /* gpmc_ad9 */
  60                         0x28    (PIN_INPUT  | MUX_MODE0) /* gpmc_ad10 */
  61                         0x2c    (PIN_INPUT  | MUX_MODE0) /* gpmc_ad11 */
  62                         0x30    (PIN_INPUT  | MUX_MODE0) /* gpmc_ad12 */
  63                         0x34    (PIN_INPUT  | MUX_MODE0) /* gpmc_ad13 */
  64                         0x38    (PIN_INPUT  | MUX_MODE0) /* gpmc_ad14 */
  65                         0x3c    (PIN_INPUT  | MUX_MODE0) /* gpmc_ad15 */
  66                         0xb4    (PIN_OUTPUT | MUX_MODE0) /* gpmc_cs0 */
  67                         0xc4    (PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale */
  68                         0xcc    (PIN_OUTPUT | MUX_MODE0) /* gpmc_wen */
  69                         0xc8    (PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren */
  70                         0xd0    (PIN_OUTPUT | MUX_MODE0) /* gpmc_ben0 */
  71                         0xd8    (PIN_INPUT  | MUX_MODE0) /* gpmc_wait0 */
  72                 >;
  73         };
  74
  75         usb1_pins: pinmux_usb1_pins {
  76                 pinctrl-single,pins = <
  77                         0x280 (PIN_INPUT_SLEW | MUX_MODE0) /* usb1_drvvbus */
  78                 >;
  79         };
  80
  81         usb2_pins: pinmux_usb2_pins {
  82                 pinctrl-single,pins = <
  83                         0x284 (PIN_INPUT_SLEW | MUX_MODE0) /* usb2_drvvbus */
  84                 >;
  85         };
  86
  87         tps65917_pins_default: tps65917_pins_default {
  88                 pinctrl-single,pins = <
  89                         0x424 (PIN_INPUT_PULLUP | MUX_MODE1) /* wakeup3.sys_nirq1 */
  90                 >;
  91         };
  92
  93         mmc1_pins_default: mmc1_pins_default {
  94                 pinctrl-single,pins = <
  95                         0x36c (PIN_INPUT | MUX_MODE14)  /* mmc1sdcd.gpio219 */
  96                         0x354 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */
  97                         0x358 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */
  98                         0x35c (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */
  99                         0x360 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */
 100                         0x364 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */
 101                         0x368 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */
 102                 >;
 103         };
 104
 105         mmc2_pins_default: mmc2_pins_default {
 106                 pinctrl-single,pins = <
 107                         0x9c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */
 108                         0xb0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
 109                         0xa0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
 110                         0xa4 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
 111                         0xa8 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
 112                         0xac (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
 113                         0x8c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
 114                         0x90 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
 115                         0x94 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
 116                         0x98 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
 117                 >;
 118         };
 119
 120         dcan1_pins_default: dcan1_pins_default {
 121                 pinctrl-single,pins = <
 122                         0x3d0   (PIN_OUTPUT_PULLUP | MUX_MODE0) /* dcan1_tx */
 123                         0x418   (PULL_UP | MUX_MODE1)   /* wakeup0.dcan1_rx */
 124                 >;
 125         };
 126
 127         dcan1_pins_sleep: dcan1_pins_sleep {
 128                 pinctrl-single,pins = <
 129                         0x3d0   (MUX_MODE15 | PULL_UP)  /* dcan1_tx.off */
 130                         0x418   (MUX_MODE15 | PULL_UP)  /* wakeup0.off */
 131                 >;
 132         };
 133
 134         qspi1_pins: pinmux_qspi1_pins {
 135                 pinctrl-single,pins = <
 136                         0x74 (PIN_OUTPUT | MUX_MODE1)   /* gpmc_a13.qspi1_rtclk */
 137                         0x78 (PIN_INPUT | MUX_MODE1)    /* gpmc_a14.qspi1_d3 */
 138                         0x7c (PIN_INPUT | MUX_MODE1)    /* gpmc_a15.qspi1_d2 */
 139                         0x80 (PIN_INPUT | MUX_MODE1)    /* gpmc_a16.qspi1_d1 */
 140                         0x84 (PIN_INPUT | MUX_MODE1)    /* gpmc_a17.qspi1_d0 */
 141                         0x88 (PIN_OUTPUT | MUX_MODE1)   /* qpmc_a18.qspi1_sclk */
 142                         0xb8 (PIN_OUTPUT | MUX_MODE1)   /* gpmc_cs2.qspi1_cs0 */
 143                 >;
 144         };
 145 };
 146
 147 &i2c1 {
 148         status = "okay";
 149         pinctrl-names = "default";
 150         pinctrl-0 = <&i2c1_pins>;
 151         clock-frequency = <400000>;
 152
 153         tps65917: tps65917@58 {
 154                 compatible = "ti,tps65917";
 155                 reg = <0x58>;
 156
 157                 pinctrl-names = "default";
 158                 pinctrl-0 = <&tps65917_pins_default>;
 159
 160                 interrupts = <GIC_SPI 2 IRQ_TYPE_NONE>;  /* IRQ_SYS_1N */
 161                 interrupt-controller;
 162                 #interrupt-cells = <2>;
 163
 164                 ti,system-power-controller;
 165
 166                 tps65917_pmic {
 167                         compatible = "ti,tps65917-pmic";
 168
 169                         regulators {
 170                                 smps1_reg: smps1 {
 171                                         /* VDD_MPU */
 172                                         regulator-name = "smps1";
 173                                         regulator-min-microvolt = <850000>;
 174                                         regulator-max-microvolt = <1250000>;
 175                                         regulator-always-on;
 176                                         regulator-boot-on;
 177                                 };
 178
 179                                 smps2_reg: smps2 {
 180                                         /* VDD_CORE */
 181                                         regulator-name = "smps2";
 182                                         regulator-min-microvolt = <850000>;
 183                                         regulator-max-microvolt = <1060000>;
 184                                         regulator-boot-on;
 185                                         regulator-always-on;
 186                                 };
 187
 188                                 smps3_reg: smps3 {
 189                                         /* VDD_GPU IVA DSPEVE */
 190                                         regulator-name = "smps3";
 191                                         regulator-min-microvolt = <850000>;
 192                                         regulator-max-microvolt = <1250000>;
 193                                         regulator-boot-on;
 194                                         regulator-always-on;
 195                                 };
 196
 197                                 smps4_reg: smps4 {
 198                                         /* VDDS1V8 */
 199                                         regulator-name = "smps4";
 200                                         regulator-min-microvolt = <1800000>;
 201                                         regulator-max-microvolt = <1800000>;
 202                                         regulator-always-on;
 203                                         regulator-boot-on;
 204                                 };
 205
 206                                 smps5_reg: smps5 {
 207                                         /* VDD_DDR */
 208                                         regulator-name = "smps5";
 209                                         regulator-min-microvolt = <1350000>;
 210                                         regulator-max-microvolt = <1350000>;
 211                                         regulator-boot-on;
 212                                         regulator-always-on;
 213                                 };
 214
 215                                 ldo1_reg: ldo1 {
 216                                         /* LDO1_OUT --> SDIO  */
 217                                         regulator-name = "ldo1";
 218                                         regulator-min-microvolt = <1800000>;
 219                                         regulator-max-microvolt = <3300000>;
 220                                         regulator-boot-on;
 221                                 };
 222
 223                                 ldo2_reg: ldo2 {
 224                                         /* LDO2_OUT --> TP1017 (UNUSED)  */
 225                                         regulator-name = "ldo2";
 226                                         regulator-min-microvolt = <1800000>;
 227                                         regulator-max-microvolt = <3300000>;
 228                                 };
 229
 230                                 ldo3_reg: ldo3 {
 231                                         /* VDDA_1V8_PHY */
 232                                         regulator-name = "ldo3";
 233                                         regulator-min-microvolt = <1800000>;
 234                                         regulator-max-microvolt = <1800000>;
 235                                         regulator-boot-on;
 236                                         regulator-always-on;
 237                                 };
 238
 239                                 ldo5_reg: ldo5 {
 240                                         /* VDDA_1V8_PLL */
 241                                         regulator-name = "ldo5";
 242                                         regulator-min-microvolt = <1800000>;
 243                                         regulator-max-microvolt = <1800000>;
 244                                         regulator-always-on;
 245                                         regulator-boot-on;
 246                                 };
 247
 248                                 ldo4_reg: ldo4 {
 249                                         /* VDDA_3V_USB: VDDA_USBHS33 */
 250                                         regulator-name = "ldo4";
 251                                         regulator-min-microvolt = <3300000>;
 252                                         regulator-max-microvolt = <3300000>;
 253                                         regulator-boot-on;
 254                                 };
 255                         };
 256                 };
 257
 258                 tps65917_power_button {
 259                         compatible = "ti,palmas-pwrbutton";
 260                         interrupt-parent = <&tps65917>;
 261                         interrupts = <1 IRQ_TYPE_NONE>;
 262                         wakeup-source;
 263                         ti,palmas-long-press-seconds = <6>;
 264                 };
 265         };
 266
 267         pcf_gpio_21: gpio@21 {
 268                 compatible = "ti,pcf8575";
 269                 reg = <0x21>;
 270                 lines-initial-states = <0x1408>;
 271                 gpio-controller;
 272                 #gpio-cells = <2>;
 273                 interrupt-parent = <&gpio6>;
 274                 interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
 275                 interrupt-controller;
 276                 #interrupt-cells = <2>;
 277         };
 278 };
 279
 280 &uart1 {
 281         status = "okay";
 282 };
 283
 284 &elm {
 285         status = "okay";
 286 };
 287
 288 &gpmc {
 289         status = "okay";
 290         pinctrl-names = "default";
 291         pinctrl-0 = <&nand_default>;
 292         ranges = <0 0 0 0x01000000>;    /* minimum GPMC partition = 16MB */
 293         nand@0,0 {
 294                 /* To use NAND, DIP switch SW5 must be set like so:
 295                  * SW5.1 (NAND_SELn) = ON (LOW)
 296                  * SW5.9 (GPMC_WPN) = OFF (HIGH)
 297                  */
 298                 reg = <0 0 4>;          /* device IO registers */
 299                 ti,nand-ecc-opt = "bch8";
 300                 ti,elm-id = <&elm>;
 301                 nand-bus-width = <16>;
 302                 gpmc,device-width = <2>;
 303                 gpmc,sync-clk-ps = <0>;
 304                 gpmc,cs-on-ns = <0>;
 305                 gpmc,cs-rd-off-ns = <80>;
 306                 gpmc,cs-wr-off-ns = <80>;
 307                 gpmc,adv-on-ns = <0>;
 308                 gpmc,adv-rd-off-ns = <60>;
 309                 gpmc,adv-wr-off-ns = <60>;
 310                 gpmc,we-on-ns = <10>;
 311                 gpmc,we-off-ns = <50>;
 312                 gpmc,oe-on-ns = <4>;
 313                 gpmc,oe-off-ns = <40>;
 314                 gpmc,access-ns = <40>;
 315                 gpmc,wr-access-ns = <80>;
 316                 gpmc,rd-cycle-ns = <80>;
 317                 gpmc,wr-cycle-ns = <80>;
 318                 gpmc,bus-turnaround-ns = <0>;
 319                 gpmc,cycle2cycle-delay-ns = <0>;
 320                 gpmc,clk-activation-ns = <0>;
 321                 gpmc,wait-monitoring-ns = <0>;
 322                 gpmc,wr-data-mux-bus-ns = <0>;
 323                 /* MTD partition table */
 324                 /* All SPL-* partitions are sized to minimal length
 325                  * which can be independently programmable. For
 326                  * NAND flash this is equal to size of erase-block */
 327                 #address-cells = <1>;
 328                 #size-cells = <1>;
 329                 partition@0 {
 330                         label = "NAND.SPL";
 331                         reg = <0x00000000 0x000020000>;
 332                 };
 333                 partition@1 {
 334                         label = "NAND.SPL.backup1";
 335                         reg = <0x00020000 0x00020000>;
 336                 };
 337                 partition@2 {
 338                         label = "NAND.SPL.backup2";
 339                         reg = <0x00040000 0x00020000>;
 340                 };
 341                 partition@3 {
 342                         label = "NAND.SPL.backup3";
 343                         reg = <0x00060000 0x00020000>;
 344                 };
 345                 partition@4 {
 346                         label = "NAND.u-boot-spl-os";
 347                         reg = <0x00080000 0x00040000>;
 348                 };
 349                 partition@5 {
 350                         label = "NAND.u-boot";
 351                         reg = <0x000c0000 0x00100000>;
 352                 };
 353                 partition@6 {
 354                         label = "NAND.u-boot-env";
 355                         reg = <0x001c0000 0x00020000>;
 356                 };
 357                 partition@7 {
 358                         label = "NAND.u-boot-env.backup1";
 359                         reg = <0x001e0000 0x00020000>;
 360                 };
 361                 partition@8 {
 362                         label = "NAND.kernel";
 363                         reg = <0x00200000 0x00800000>;
 364                 };
 365                 partition@9 {
 366                         label = "NAND.file-system";
 367                         reg = <0x00a00000 0x0f600000>;
 368                 };
 369         };
 370 };
 371
 372 &usb2_phy1 {
 373         phy-supply = <&ldo4_reg>;
 374 };
 375
 376 &usb2_phy2 {
 377         phy-supply = <&ldo4_reg>;
 378 };
 379
 380 &omap_dwc3_1 {
 381         extcon = <&extcon_usb1>;
 382 };
 383
 384 &omap_dwc3_2 {
 385         extcon = <&extcon_usb2>;
 386 };
 387
 388 &usb1 {
 389         dr_mode = "peripheral";
 390         pinctrl-names = "default";
 391         pinctrl-0 = <&usb1_pins>;
 392 };
 393
 394 &usb2 {
 395         dr_mode = "host";
 396         pinctrl-names = "default";
 397         pinctrl-0 = <&usb2_pins>;
 398 };
 399
 400 &mmc1 {
 401         status = "okay";
 402         pinctrl-names = "default";
 403         pinctrl-0 = <&mmc1_pins_default>;
 404
 405         vmmc-supply = <&ldo1_reg>;
 406         bus-width = <4>;
 407         /*
 408          * SDCD signal is not being used here - using the fact that GPIO mode
 409          * is a viable alternative
 410          */
 411         cd-gpios = <&gpio6 27 0>;
 412 };
 413
 414 &mmc2 {
 415         /* SW5-3 in ON position */
 416         status = "okay";
 417         pinctrl-names = "default";
 418         pinctrl-0 = <&mmc2_pins_default>;
 419
 420         vmmc-supply = <&evm_3v3>;
 421         bus-width = <8>;
 422         ti,non-removable;
 423 };
 424
 425 &dra7_pmx_core {
 426         cpsw_default: cpsw_default {
 427                 pinctrl-single,pins = <
 428                         /* Slave 2 */
 429                         0x198 (PIN_OUTPUT | MUX_MODE3)  /* vin2a_d12.rgmii1_txc */
 430                         0x19c (PIN_OUTPUT | MUX_MODE3)  /* vin2a_d13.rgmii1_tctl */
 431                         0x1a0 (PIN_OUTPUT | MUX_MODE3)  /* vin2a_d14.rgmii1_td3 */
 432                         0x1a4 (PIN_OUTPUT | MUX_MODE3)  /* vin2a_d15.rgmii1_td2 */
 433                         0x1a8 (PIN_OUTPUT | MUX_MODE3)  /* vin2a_d16.rgmii1_td1 */
 434                         0x1ac (PIN_OUTPUT | MUX_MODE3)  /* vin2a_d17.rgmii1_td0 */
 435                         0x1b0 (PIN_INPUT | MUX_MODE3)   /* vin2a_d18.rgmii1_rclk */
 436                         0x1b4 (PIN_INPUT | MUX_MODE3)   /* vin2a_d19.rgmii1_rctl */
 437                         0x1b8 (PIN_INPUT | MUX_MODE3)   /* vin2a_d20.rgmii1_rd3 */
 438                         0x1bc (PIN_INPUT | MUX_MODE3)   /* vin2a_d21.rgmii1_rd2 */
 439                         0x1c0 (PIN_INPUT | MUX_MODE3)   /* vin2a_d22.rgmii1_rd1 */
 440                         0x1c4 (PIN_INPUT | MUX_MODE3)   /* vin2a_d23.rgmii1_rd0 */
 441                 >;
 442
 443         };
 444
 445         cpsw_sleep: cpsw_sleep {
 446                 pinctrl-single,pins = <
 447                         /* Slave 2 */
 448                         0x198 (MUX_MODE15)
 449                         0x19c (MUX_MODE15)
 450                         0x1a0 (MUX_MODE15)
 451                         0x1a4 (MUX_MODE15)
 452                         0x1a8 (MUX_MODE15)
 453                         0x1ac (MUX_MODE15)
 454                         0x1b0 (MUX_MODE15)
 455                         0x1b4 (MUX_MODE15)
 456                         0x1b8 (MUX_MODE15)
 457                         0x1bc (MUX_MODE15)
 458                         0x1c0 (MUX_MODE15)
 459                         0x1c4 (MUX_MODE15)
 460                 >;
 461         };
 462
 463         davinci_mdio_default: davinci_mdio_default {
 464                 pinctrl-single,pins = <
 465                         /* MDIO */
 466                         0x23c (PIN_OUTPUT_PULLUP | MUX_MODE0)   /* mdio_d.mdio_d */
 467                         0x240 (PIN_INPUT_PULLUP | MUX_MODE0)    /* mdio_clk.mdio_clk */
 468                 >;
 469         };
 470
 471         davinci_mdio_sleep: davinci_mdio_sleep {
 472                 pinctrl-single,pins = <
 473                         0x23c (MUX_MODE15)
 474                         0x240 (MUX_MODE15)
 475                 >;
 476         };
 477 };
 478
 479 &mac {
 480         status = "okay";
 481         pinctrl-names = "default", "sleep";
 482         pinctrl-0 = <&cpsw_default>;
 483         pinctrl-1 = <&cpsw_sleep>;
 484 };
 485
 486 &cpsw_emac1 {
 487         phy_id = <&davinci_mdio>, <3>;
 488         phy-mode = "rgmii";
 489 };
 490
 491 &davinci_mdio {
 492         pinctrl-names = "default", "sleep";
 493         pinctrl-0 = <&davinci_mdio_default>;
 494         pinctrl-1 = <&davinci_mdio_sleep>;
 495         active_slave = <1>;
 496 };
 497
 498 &dcan1 {
 499         status = "ok";
 500         pinctrl-names = "default", "sleep";
 501         pinctrl-0 = <&dcan1_pins_default>;
 502         pinctrl-1 = <&dcan1_pins_sleep>;
 503 };
 504
 505 &qspi {
 506         status = "okay";
 507         pinctrl-names = "default";
 508         pinctrl-0 = <&qspi1_pins>;
 509
 510         spi-max-frequency = <48000000>;
 511         m25p80@0 {
 512                 compatible = "s25fl256s1";
 513                 spi-max-frequency = <48000000>;
 514                 reg = <0>;
 515                 spi-tx-bus-width = <1>;
 516                 spi-rx-bus-width = <4>;
 517                 spi-cpol;
 518                 spi-cpha;
 519                 #address-cells = <1>;
 520                 #size-cells = <1>;
 521
 522                 /* MTD partition table.
 523                  * The ROM checks the first four physical blocks
 524                  * for a valid file to boot and the flash here is
 525                  * 64KiB block size.
 526                  */
 527                 partition@0 {
 528                         label = "QSPI.SPL";
 529                         reg = <0x00000000 0x000010000>;
 530                 };
 531                 partition@1 {
 532                         label = "QSPI.SPL.backup1";
 533                         reg = <0x00010000 0x00010000>;
 534                 };
 535                 partition@2 {
 536                         label = "QSPI.SPL.backup2";
 537                         reg = <0x00020000 0x00010000>;
 538                 };
 539                 partition@3 {
 540                         label = "QSPI.SPL.backup3";
 541                         reg = <0x00030000 0x00010000>;
 542                 };
 543                 partition@4 {
 544                         label = "QSPI.u-boot";
 545                         reg = <0x00040000 0x00100000>;
 546                 };
 547                 partition@5 {
 548                         label = "QSPI.u-boot-spl-os";
 549                         reg = <0x00140000 0x00080000>;
 550                 };
 551                 partition@6 {
 552                         label = "QSPI.u-boot-env";
 553                         reg = <0x001c0000 0x00010000>;
 554                 };
 555                 partition@7 {
 556                         label = "QSPI.u-boot-env.backup1";
 557                         reg = <0x001d0000 0x0010000>;
 558                 };
 559                 partition@8 {
 560                         label = "QSPI.kernel";
 561                         reg = <0x001e0000 0x0800000>;
 562                 };
 563                 partition@9 {
 564                         label = "QSPI.file-system";
 565                         reg = <0x009e0000 0x01620000>;
 566                 };
 567         };
 568 };