kernel/arch/arm/boot/dts/berlin2.dtsi

   1 /*
   2  * Device Tree Include file for Marvell Armada 1500 (Berlin BG2) SoC
   3  *
   4  * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
   5  *
   6  * based on GPL'ed 2.6 kernel sources
   7  *  (c) Marvell International Ltd.
   8  *
   9  * This file is licensed under the terms of the GNU General Public
  10  * License version 2.  This program is licensed "as is" without any
  11  * warranty of any kind, whether express or implied.
  12  */
  13
  14 #include "skeleton.dtsi"
  15 #include <dt-bindings/clock/berlin2.h>
  16 #include <dt-bindings/interrupt-controller/arm-gic.h>
  17
  18 / {
  19         model = "Marvell Armada 1500 (BG2) SoC";
  20         compatible = "marvell,berlin2", "marvell,berlin";
  21
  22         cpus {
  23                 #address-cells = <1>;
  24                 #size-cells = <0>;
  25                 enable-method = "marvell,berlin-smp";
  26
  27                 cpu@0 {
  28                         compatible = "marvell,pj4b";
  29                         device_type = "cpu";
  30                         next-level-cache = <&l2>;
  31                         reg = <0>;
  32                 };
  33
  34                 cpu@1 {
  35                         compatible = "marvell,pj4b";
  36                         device_type = "cpu";
  37                         next-level-cache = <&l2>;
  38                         reg = <1>;
  39                 };
  40         };
  41
  42         refclk: oscillator {
  43                 compatible = "fixed-clock";
  44                 #clock-cells = <0>;
  45                 clock-frequency = <25000000>;
  46         };
  47
  48         soc {
  49                 compatible = "simple-bus";
  50                 #address-cells = <1>;
  51                 #size-cells = <1>;
  52                 interrupt-parent = <&gic>;
  53
  54                 ranges = <0 0xf7000000 0x1000000>;
  55
  56                 sdhci0: sdhci@ab0000 {
  57                         compatible = "mrvl,pxav3-mmc";
  58                         reg = <0xab0000 0x200>;
  59                         clocks = <&chip CLKID_SDIO0XIN>, <&chip CLKID_SDIO0>;
  60                         clock-names = "io", "core";
  61                         interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
  62                         status = "disabled";
  63                 };
  64
  65                 sdhci1: sdhci@ab0800 {
  66                         compatible = "mrvl,pxav3-mmc";
  67                         reg = <0xab0800 0x200>;
  68                         clocks = <&chip CLKID_SDIO1XIN>, <&chip CLKID_SDIO1>;
  69                         clock-names = "io", "core";
  70                         interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
  71                         status = "disabled";
  72                 };
  73
  74                 sdhci2: sdhci@ab1000 {
  75                         compatible = "mrvl,pxav3-mmc";
  76                         reg = <0xab1000 0x200>;
  77                         interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
  78                         clocks = <&chip CLKID_NFC_ECC>, <&chip CLKID_NFC>;
  79                         clock-names = "io", "core";
  80                         pinctrl-0 = <&emmc_pmux>;
  81                         pinctrl-names = "default";
  82                         status = "disabled";
  83                 };
  84
  85                 l2: l2-cache-controller@ac0000 {
  86                         compatible = "marvell,tauros3-cache", "arm,pl310-cache";
  87                         reg = <0xac0000 0x1000>;
  88                         cache-unified;
  89                         cache-level = <2>;
  90                 };
  91
  92                 scu: snoop-control-unit@ad0000 {
  93                         compatible = "arm,cortex-a9-scu";
  94                         reg = <0xad0000 0x58>;
  95                 };
  96
  97                 gic: interrupt-controller@ad1000 {
  98                         compatible = "arm,cortex-a9-gic";
  99                         reg = <0xad1000 0x1000>, <0xad0100 0x0100>;
 100                         interrupt-controller;
 101                         #interrupt-cells = <3>;
 102                 };
 103
 104                 local-timer@ad0600 {
 105                         compatible = "arm,cortex-a9-twd-timer";
 106                         reg = <0xad0600 0x20>;
 107                         interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
 108                         clocks = <&chip CLKID_TWD>;
 109                 };
 110
 111                 eth1: ethernet@b90000 {
 112                         compatible = "marvell,pxa168-eth";
 113                         reg = <0xb90000 0x10000>;
 114                         clocks = <&chip CLKID_GETH1>;
 115                         interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 116                         /* set by bootloader */
 117                         local-mac-address = [00 00 00 00 00 00];
 118                         #address-cells = <1>;
 119                         #size-cells = <0>;
 120                         phy-connection-type = "mii";
 121                         phy-handle = <&ethphy1>;
 122                         status = "disabled";
 123
 124                         ethphy1: ethernet-phy@0 {
 125                                 reg = <0>;
 126                         };
 127                 };
 128
 129                 cpu-ctrl@dd0000 {
 130                         compatible = "marvell,berlin-cpu-ctrl";
 131                         reg = <0xdd0000 0x10000>;
 132                 };
 133
 134                 eth0: ethernet@e50000 {
 135                         compatible = "marvell,pxa168-eth";
 136                         reg = <0xe50000 0x10000>;
 137                         clocks = <&chip CLKID_GETH0>;
 138                         interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
 139                         /* set by bootloader */
 140                         local-mac-address = [00 00 00 00 00 00];
 141                         #address-cells = <1>;
 142                         #size-cells = <0>;
 143                         phy-connection-type = "mii";
 144                         phy-handle = <&ethphy0>;
 145                         status = "disabled";
 146
 147                         ethphy0: ethernet-phy@0 {
 148                                 reg = <0>;
 149                         };
 150                 };
 151
 152                 apb@e80000 {
 153                         compatible = "simple-bus";
 154                         #address-cells = <1>;
 155                         #size-cells = <1>;
 156
 157                         ranges = <0 0xe80000 0x10000>;
 158                         interrupt-parent = <&aic>;
 159
 160                         gpio0: gpio@0400 {
 161                                 compatible = "snps,dw-apb-gpio";
 162                                 reg = <0x0400 0x400>;
 163                                 #address-cells = <1>;
 164                                 #size-cells = <0>;
 165
 166                                 porta: gpio-port@0 {
 167                                         compatible = "snps,dw-apb-gpio-port";
 168                                         gpio-controller;
 169                                         #gpio-cells = <2>;
 170                                         snps,nr-gpios = <8>;
 171                                         reg = <0>;
 172                                         interrupt-controller;
 173                                         #interrupt-cells = <2>;
 174                                         interrupts = <0>;
 175                                 };
 176                         };
 177
 178                         gpio1: gpio@0800 {
 179                                 compatible = "snps,dw-apb-gpio";
 180                                 reg = <0x0800 0x400>;
 181                                 #address-cells = <1>;
 182                                 #size-cells = <0>;
 183
 184                                 portb: gpio-port@1 {
 185                                         compatible = "snps,dw-apb-gpio-port";
 186                                         gpio-controller;
 187                                         #gpio-cells = <2>;
 188                                         snps,nr-gpios = <8>;
 189                                         reg = <0>;
 190                                         interrupt-controller;
 191                                         #interrupt-cells = <2>;
 192                                         interrupts = <1>;
 193                                 };
 194                         };
 195
 196                         gpio2: gpio@0c00 {
 197                                 compatible = "snps,dw-apb-gpio";
 198                                 reg = <0x0c00 0x400>;
 199                                 #address-cells = <1>;
 200                                 #size-cells = <0>;
 201
 202                                 portc: gpio-port@2 {
 203                                         compatible = "snps,dw-apb-gpio-port";
 204                                         gpio-controller;
 205                                         #gpio-cells = <2>;
 206                                         snps,nr-gpios = <8>;
 207                                         reg = <0>;
 208                                         interrupt-controller;
 209                                         #interrupt-cells = <2>;
 210                                         interrupts = <2>;
 211                                 };
 212                         };
 213
 214                         gpio3: gpio@1000 {
 215                                 compatible = "snps,dw-apb-gpio";
 216                                 reg = <0x1000 0x400>;
 217                                 #address-cells = <1>;
 218                                 #size-cells = <0>;
 219
 220                                 portd: gpio-port@3 {
 221                                         compatible = "snps,dw-apb-gpio-port";
 222                                         gpio-controller;
 223                                         #gpio-cells = <2>;
 224                                         snps,nr-gpios = <8>;
 225                                         reg = <0>;
 226                                         interrupt-controller;
 227                                         #interrupt-cells = <2>;
 228                                         interrupts = <3>;
 229                                 };
 230                         };
 231
 232                         timer0: timer@2c00 {
 233                                 compatible = "snps,dw-apb-timer";
 234                                 reg = <0x2c00 0x14>;
 235                                 interrupts = <8>;
 236                                 clocks = <&chip CLKID_CFG>;
 237                                 clock-names = "timer";
 238                                 status = "okay";
 239                         };
 240
 241                         timer1: timer@2c14 {
 242                                 compatible = "snps,dw-apb-timer";
 243                                 reg = <0x2c14 0x14>;
 244                                 interrupts = <9>;
 245                                 clocks = <&chip CLKID_CFG>;
 246                                 clock-names = "timer";
 247                                 status = "okay";
 248                         };
 249
 250                         timer2: timer@2c28 {
 251                                 compatible = "snps,dw-apb-timer";
 252                                 reg = <0x2c28 0x14>;
 253                                 interrupts = <10>;
 254                                 clocks = <&chip CLKID_CFG>;
 255                                 clock-names = "timer";
 256                                 status = "disabled";
 257                         };
 258
 259                         timer3: timer@2c3c {
 260                                 compatible = "snps,dw-apb-timer";
 261                                 reg = <0x2c3c 0x14>;
 262                                 interrupts = <11>;
 263                                 clocks = <&chip CLKID_CFG>;
 264                                 clock-names = "timer";
 265                                 status = "disabled";
 266                         };
 267
 268                         timer4: timer@2c50 {
 269                                 compatible = "snps,dw-apb-timer";
 270                                 reg = <0x2c50 0x14>;
 271                                 interrupts = <12>;
 272                                 clocks = <&chip CLKID_CFG>;
 273                                 clock-names = "timer";
 274                                 status = "disabled";
 275                         };
 276
 277                         timer5: timer@2c64 {
 278                                 compatible = "snps,dw-apb-timer";
 279                                 reg = <0x2c64 0x14>;
 280                                 interrupts = <13>;
 281                                 clocks = <&chip CLKID_CFG>;
 282                                 clock-names = "timer";
 283                                 status = "disabled";
 284                         };
 285
 286                         timer6: timer@2c78 {
 287                                 compatible = "snps,dw-apb-timer";
 288                                 reg = <0x2c78 0x14>;
 289                                 interrupts = <14>;
 290                                 clocks = <&chip CLKID_CFG>;
 291                                 clock-names = "timer";
 292                                 status = "disabled";
 293                         };
 294
 295                         timer7: timer@2c8c {
 296                                 compatible = "snps,dw-apb-timer";
 297                                 reg = <0x2c8c 0x14>;
 298                                 interrupts = <15>;
 299                                 clocks = <&chip CLKID_CFG>;
 300                                 clock-names = "timer";
 301                                 status = "disabled";
 302                         };
 303
 304                         aic: interrupt-controller@3000 {
 305                                 compatible = "snps,dw-apb-ictl";
 306                                 reg = <0x3000 0xc00>;
 307                                 interrupt-controller;
 308                                 #interrupt-cells = <1>;
 309                                 interrupt-parent = <&gic>;
 310                                 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 311                         };
 312                 };
 313
 314                 ahci: sata@e90000 {
 315                         compatible = "marvell,berlin2-ahci", "generic-ahci";
 316                         reg = <0xe90000 0x1000>;
 317                         interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
 318                         clocks = <&chip CLKID_SATA>;
 319                         #address-cells = <1>;
 320                         #size-cells = <0>;
 321
 322                         sata0: sata-port@0 {
 323                                 reg = <0>;
 324                                 phys = <&sata_phy 0>;
 325                                 status = "disabled";
 326                         };
 327
 328                         sata1: sata-port@1 {
 329                                 reg = <1>;
 330                                 phys = <&sata_phy 1>;
 331                                 status = "disabled";
 332                         };
 333                 };
 334
 335                 sata_phy: phy@e900a0 {
 336                         compatible = "marvell,berlin2-sata-phy";
 337                         reg = <0xe900a0 0x200>;
 338                         clocks = <&chip CLKID_SATA>;
 339                         #address-cells = <1>;
 340                         #size-cells = <0>;
 341                         #phy-cells = <1>;
 342                         status = "disabled";
 343
 344                         sata-phy@0 {
 345                                 reg = <0>;
 346                         };
 347
 348                         sata-phy@1 {
 349                                 reg = <1>;
 350                         };
 351                 };
 352
 353                 chip: chip-control@ea0000 {
 354                         compatible = "marvell,berlin2-chip-ctrl";
 355                         #clock-cells = <1>;
 356                         #reset-cells = <2>;
 357                         reg = <0xea0000 0x400>;
 358                         clocks = <&refclk>;
 359                         clock-names = "refclk";
 360
 361                         emmc_pmux: emmc-pmux {
 362                                 groups = "G26";
 363                                 function = "emmc";
 364                         };
 365                 };
 366
 367                 apb@fc0000 {
 368                         compatible = "simple-bus";
 369                         #address-cells = <1>;
 370                         #size-cells = <1>;
 371
 372                         ranges = <0 0xfc0000 0x10000>;
 373                         interrupt-parent = <&sic>;
 374
 375                         sm_gpio1: gpio@5000 {
 376                                 compatible = "snps,dw-apb-gpio";
 377                                 reg = <0x5000 0x400>;
 378                                 #address-cells = <1>;
 379                                 #size-cells = <0>;
 380
 381                                 portf: gpio-port@5 {
 382                                         compatible = "snps,dw-apb-gpio-port";
 383                                         gpio-controller;
 384                                         #gpio-cells = <2>;
 385                                         snps,nr-gpios = <8>;
 386                                         reg = <0>;
 387                                 };
 388                         };
 389
 390                         sm_gpio0: gpio@c000 {
 391                                 compatible = "snps,dw-apb-gpio";
 392                                 reg = <0xc000 0x400>;
 393                                 #address-cells = <1>;
 394                                 #size-cells = <0>;
 395
 396                                 porte: gpio-port@4 {
 397                                         compatible = "snps,dw-apb-gpio-port";
 398                                         gpio-controller;
 399                                         #gpio-cells = <2>;
 400                                         snps,nr-gpios = <8>;
 401                                         reg = <0>;
 402                                         interrupt-controller;
 403                                         #interrupt-cells = <2>;
 404                                         interrupts = <11>;
 405                                 };
 406                         };
 407
 408                         uart0: serial@9000 {
 409                                 compatible = "snps,dw-apb-uart";
 410                                 reg = <0x9000 0x100>;
 411                                 reg-shift = <2>;
 412                                 reg-io-width = <1>;
 413                                 interrupts = <8>;
 414                                 clocks = <&refclk>;
 415                                 pinctrl-0 = <&uart0_pmux>;
 416                                 pinctrl-names = "default";
 417                                 status = "disabled";
 418                         };
 419
 420                         uart1: serial@a000 {
 421                                 compatible = "snps,dw-apb-uart";
 422                                 reg = <0xa000 0x100>;
 423                                 reg-shift = <2>;
 424                                 reg-io-width = <1>;
 425                                 interrupts = <9>;
 426                                 clocks = <&refclk>;
 427                                 pinctrl-0 = <&uart1_pmux>;
 428                                 pinctrl-names = "default";
 429                                 status = "disabled";
 430                         };
 431
 432                         uart2: serial@b000 {
 433                                 compatible = "snps,dw-apb-uart";
 434                                 reg = <0xb000 0x100>;
 435                                 reg-shift = <2>;
 436                                 reg-io-width = <1>;
 437                                 interrupts = <10>;
 438                                 clocks = <&refclk>;
 439                                 pinctrl-0 = <&uart2_pmux>;
 440                                 pinctrl-names = "default";
 441                                 status = "disabled";
 442                         };
 443
 444                         sysctrl: system-controller@d000 {
 445                                 compatible = "marvell,berlin2-system-ctrl";
 446                                 reg = <0xd000 0x100>;
 447
 448                                 uart0_pmux: uart0-pmux {
 449                                         groups = "GSM4";
 450                                         function = "uart0";
 451                                 };
 452
 453                                 uart1_pmux: uart1-pmux {
 454                                         groups = "GSM5";
 455                                         function = "uart1";
 456                                 };
 457
 458                                 uart2_pmux: uart2-pmux {
 459                                         groups = "GSM3";
 460                                         function = "uart2";
 461                                 };
 462                         };
 463
 464                         sic: interrupt-controller@e000 {
 465                                 compatible = "snps,dw-apb-ictl";
 466                                 reg = <0xe000 0x400>;
 467                                 interrupt-controller;
 468                                 #interrupt-cells = <1>;
 469                                 interrupt-parent = <&gic>;
 470                                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 471                         };
 472                 };
 473         };
 474 };