2 * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
12 #ifndef _LINUX_BITOPS_H
13 #error only <linux/bitops.h> can be included directly
18 #include <linux/types.h>
19 #include <linux/compiler.h>
20 #include <asm/barrier.h>
23 * Hardware assisted read-modify-write using ARC700 LLOCK/SCOND insns.
24 * The Kconfig glue ensures that in SMP, this is only set if the container
25 * SoC/platform has cross-core coherent LLOCK/SCOND
27 #if defined(CONFIG_ARC_HAS_LLSC)
29 static inline void set_bit(unsigned long nr, volatile unsigned long *m)
36 * ARC ISA micro-optimization:
38 * Instructions dealing with bitpos only consider lower 5 bits (0-31)
39 * e.g (x << 33) is handled like (x << 1) by ASL instruction
40 * (mem pointer still needs adjustment to point to next word)
42 * Hence the masking to clamp @nr arg can be elided in general.
44 * However if @nr is a constant (above assumed it in a register),
45 * and greater than 31, gcc can optimize away (x << 33) to 0,
46 * as overflow, given the 32-bit ISA. Thus masking needs to be done
47 * for constant @nr, but no code is generated due to const prop.
49 if (__builtin_constant_p(nr))
53 "1: llock %0, [%1] \n"
62 static inline void clear_bit(unsigned long nr, volatile unsigned long *m)
68 if (__builtin_constant_p(nr))
72 "1: llock %0, [%1] \n"
81 static inline void change_bit(unsigned long nr, volatile unsigned long *m)
87 if (__builtin_constant_p(nr))
91 "1: llock %0, [%1] \n"
104 * set it and return 0 (old value)
106 * return 1 (old value).
108 * Since ARC lacks a equivalent h/w primitive, the bit is set unconditionally
109 * and the old value of bit is returned
111 static inline int test_and_set_bit(unsigned long nr, volatile unsigned long *m)
113 unsigned long old, temp;
117 if (__builtin_constant_p(nr))
121 * Explicit full memory barrier needed before/after as
122 * LLOCK/SCOND themselves don't provide any such semantics
126 __asm__ __volatile__(
127 "1: llock %0, [%2] \n"
128 " bset %1, %0, %3 \n"
131 : "=&r"(old), "=&r"(temp)
137 return (old & (1 << nr)) != 0;
141 test_and_clear_bit(unsigned long nr, volatile unsigned long *m)
143 unsigned int old, temp;
147 if (__builtin_constant_p(nr))
152 __asm__ __volatile__(
153 "1: llock %0, [%2] \n"
154 " bclr %1, %0, %3 \n"
157 : "=&r"(old), "=&r"(temp)
163 return (old & (1 << nr)) != 0;
167 test_and_change_bit(unsigned long nr, volatile unsigned long *m)
169 unsigned int old, temp;
173 if (__builtin_constant_p(nr))
178 __asm__ __volatile__(
179 "1: llock %0, [%2] \n"
180 " bxor %1, %0, %3 \n"
183 : "=&r"(old), "=&r"(temp)
189 return (old & (1 << nr)) != 0;
192 #else /* !CONFIG_ARC_HAS_LLSC */
197 * Non hardware assisted Atomic-R-M-W
198 * Locking would change to irq-disabling only (UP) and spinlocks (SMP)
200 * There's "significant" micro-optimization in writing our own variants of
201 * bitops (over generic variants)
203 * (1) The generic APIs have "signed" @nr while we have it "unsigned"
204 * This avoids extra code to be generated for pointer arithmatic, since
205 * is "not sure" that index is NOT -ve
206 * (2) Utilize the fact that ARCompact bit fidding insn (BSET/BCLR/ASL) etc
207 * only consider bottom 5 bits of @nr, so NO need to mask them off.
208 * (GCC Quirk: however for constant @nr we still need to do the masking
212 static inline void set_bit(unsigned long nr, volatile unsigned long *m)
214 unsigned long temp, flags;
217 if (__builtin_constant_p(nr))
223 *m = temp | (1UL << nr);
225 bitops_unlock(flags);
228 static inline void clear_bit(unsigned long nr, volatile unsigned long *m)
230 unsigned long temp, flags;
233 if (__builtin_constant_p(nr))
239 *m = temp & ~(1UL << nr);
241 bitops_unlock(flags);
244 static inline void change_bit(unsigned long nr, volatile unsigned long *m)
246 unsigned long temp, flags;
249 if (__builtin_constant_p(nr))
255 *m = temp ^ (1UL << nr);
257 bitops_unlock(flags);
260 static inline int test_and_set_bit(unsigned long nr, volatile unsigned long *m)
262 unsigned long old, flags;
265 if (__builtin_constant_p(nr))
269 * spin lock/unlock provide the needed smp_mb() before/after
274 *m = old | (1 << nr);
276 bitops_unlock(flags);
278 return (old & (1 << nr)) != 0;
282 test_and_clear_bit(unsigned long nr, volatile unsigned long *m)
284 unsigned long old, flags;
287 if (__builtin_constant_p(nr))
293 *m = old & ~(1 << nr);
295 bitops_unlock(flags);
297 return (old & (1 << nr)) != 0;
301 test_and_change_bit(unsigned long nr, volatile unsigned long *m)
303 unsigned long old, flags;
306 if (__builtin_constant_p(nr))
312 *m = old ^ (1 << nr);
314 bitops_unlock(flags);
316 return (old & (1 << nr)) != 0;
319 #endif /* CONFIG_ARC_HAS_LLSC */
321 /***************************************
322 * Non atomic variants
323 **************************************/
325 static inline void __set_bit(unsigned long nr, volatile unsigned long *m)
330 if (__builtin_constant_p(nr))
334 *m = temp | (1UL << nr);
337 static inline void __clear_bit(unsigned long nr, volatile unsigned long *m)
342 if (__builtin_constant_p(nr))
346 *m = temp & ~(1UL << nr);
349 static inline void __change_bit(unsigned long nr, volatile unsigned long *m)
354 if (__builtin_constant_p(nr))
358 *m = temp ^ (1UL << nr);
362 __test_and_set_bit(unsigned long nr, volatile unsigned long *m)
367 if (__builtin_constant_p(nr))
371 *m = old | (1 << nr);
373 return (old & (1 << nr)) != 0;
377 __test_and_clear_bit(unsigned long nr, volatile unsigned long *m)
382 if (__builtin_constant_p(nr))
386 *m = old & ~(1 << nr);
388 return (old & (1 << nr)) != 0;
392 __test_and_change_bit(unsigned long nr, volatile unsigned long *m)
397 if (__builtin_constant_p(nr))
401 *m = old ^ (1 << nr);
403 return (old & (1 << nr)) != 0;
407 * This routine doesn't need to be atomic.
410 test_bit(unsigned int nr, const volatile unsigned long *addr)
416 if (__builtin_constant_p(nr))
421 return ((mask & *addr) != 0);
425 * Count the number of zeros, starting from MSB
426 * Helper for fls( ) friends
427 * This is a pure count, so (1-32) or (0-31) doesn't apply
428 * It could be 0 to 32, based on num of 0's in there
429 * clz(0x8000_0000) = 0, clz(0xFFFF_FFFF)=0, clz(0) = 32, clz(1) = 31
431 static inline __attribute__ ((const)) int clz(unsigned int x)
435 __asm__ __volatile__(
438 " add.p %0, %0, 1 \n"
446 static inline int constant_fls(int x)
452 if (!(x & 0xffff0000u)) {
456 if (!(x & 0xff000000u)) {
460 if (!(x & 0xf0000000u)) {
464 if (!(x & 0xc0000000u)) {
468 if (!(x & 0x80000000u)) {
476 * fls = Find Last Set in word
478 * fls(1) = 1, fls(0x80000000) = 32, fls(0) = 0
480 static inline __attribute__ ((const)) int fls(unsigned long x)
482 if (__builtin_constant_p(x))
483 return constant_fls(x);
489 * __fls: Similar to fls, but zero based (0-31)
491 static inline __attribute__ ((const)) int __fls(unsigned long x)
500 * ffs = Find First Set in word (LSB to MSB)
501 * @result: [1-32], 0 if all 0's
503 #define ffs(x) ({ unsigned long __t = (x); fls(__t & -__t); })
506 * __ffs: Similar to ffs, but zero based (0-31)
508 static inline __attribute__ ((const)) int __ffs(unsigned long word)
513 return ffs(word) - 1;
517 * ffz = Find First Zero in word.
518 * @return:[0-31], 32 if all 1's
520 #define ffz(x) __ffs(~(x))
522 #include <asm-generic/bitops/hweight.h>
523 #include <asm-generic/bitops/fls64.h>
524 #include <asm-generic/bitops/sched.h>
525 #include <asm-generic/bitops/lock.h>
527 #include <asm-generic/bitops/find.h>
528 #include <asm-generic/bitops/le.h>
529 #include <asm-generic/bitops/ext2-atomic-setbit.h>
531 #endif /* !__ASSEMBLY__ */