kernel/Documentation/devicetree/bindings/drm/msm/hdmi.txt

   1 Qualcomm adreno/snapdragon hdmi output
   2
   3 Required properties:
   4 - compatible: one of the following
   5    * "qcom,hdmi-tx-8084"
   6    * "qcom,hdmi-tx-8074"
   7    * "qcom,hdmi-tx-8660"
   8    * "qcom,hdmi-tx-8960"
   9 - reg: Physical base address and length of the controller's registers
  10 - reg-names: "core_physical"
  11 - interrupts: The interrupt signal from the hdmi block.
  12 - clocks: device clocks
  13   See ../clocks/clock-bindings.txt for details.
  14 - qcom,hdmi-tx-ddc-clk-gpio: ddc clk pin
  15 - qcom,hdmi-tx-ddc-data-gpio: ddc data pin
  16 - qcom,hdmi-tx-hpd-gpio: hpd pin
  17 - core-vdda-supply: phandle to supply regulator
  18 - hdmi-mux-supply: phandle to mux regulator
  19
  20 Optional properties:
  21 - qcom,hdmi-tx-mux-en-gpio: hdmi mux enable pin
  22 - qcom,hdmi-tx-mux-sel-gpio: hdmi mux select pin
  23
  24 Example:
  25
  26 / {
  27         ...
  28
  29         hdmi: qcom,hdmi-tx-8960@4a00000 {
  30                 compatible = "qcom,hdmi-tx-8960";
  31                 reg-names = "core_physical";
  32                 reg = <0x04a00000 0x1000>;
  33                 interrupts = <GIC_SPI 79 0>;
  34                 clock-names =
  35                     "core_clk",
  36                     "master_iface_clk",
  37                     "slave_iface_clk";
  38                 clocks =
  39                     <&mmcc HDMI_APP_CLK>,
  40                     <&mmcc HDMI_M_AHB_CLK>,
  41                     <&mmcc HDMI_S_AHB_CLK>;
  42                 qcom,hdmi-tx-ddc-clk = <&msmgpio 70 GPIO_ACTIVE_HIGH>;
  43                 qcom,hdmi-tx-ddc-data = <&msmgpio 71 GPIO_ACTIVE_HIGH>;
  44                 qcom,hdmi-tx-hpd = <&msmgpio 72 GPIO_ACTIVE_HIGH>;
  45                 core-vdda-supply = <&pm8921_hdmi_mvs>;
  46                 hdmi-mux-supply = <&ext_3p3v>;
  47         };
  48 };