2 * Exynos4210 UART Emulation
4 * Copyright (C) 2011 Samsung Electronics Co Ltd.
5 * Maksim Kozlov, <m.kozlov@samsung.com>
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 * You should have received a copy of the GNU General Public License along
18 * with this program; if not, see <http://www.gnu.org/licenses/>.
22 #include "qemu/osdep.h"
23 #include "hw/sysbus.h"
24 #include "qemu/error-report.h"
25 #include "sysemu/sysemu.h"
26 #include "sysemu/char.h"
28 #include "hw/arm/exynos4210.h"
31 #undef DEBUG_UART_EXTEND
37 #define DEBUG_UART_EXTEND 0
39 #define DEBUG_Rx_DATA 0
40 #define DEBUG_Tx_DATA 0
43 #define PRINT_DEBUG(fmt, args...) \
45 fprintf(stderr, " [%s:%d] "fmt, __func__, __LINE__, ##args); \
49 #define PRINT_DEBUG_EXTEND(fmt, args...) \
51 fprintf(stderr, " [%s:%d] "fmt, __func__, __LINE__, ##args); \
54 #define PRINT_DEBUG_EXTEND(fmt, args...) \
59 #define PRINT_DEBUG(fmt, args...) \
61 #define PRINT_DEBUG_EXTEND(fmt, args...) \
65 #define PRINT_ERROR(fmt, args...) \
67 fprintf(stderr, " [%s:%d] "fmt, __func__, __LINE__, ##args); \
71 * Offsets for UART registers relative to SFR base address
75 #define ULCON 0x0000 /* Line Control */
76 #define UCON 0x0004 /* Control */
77 #define UFCON 0x0008 /* FIFO Control */
78 #define UMCON 0x000C /* Modem Control */
79 #define UTRSTAT 0x0010 /* Tx/Rx Status */
80 #define UERSTAT 0x0014 /* UART Error Status */
81 #define UFSTAT 0x0018 /* FIFO Status */
82 #define UMSTAT 0x001C /* Modem Status */
83 #define UTXH 0x0020 /* Transmit Buffer */
84 #define URXH 0x0024 /* Receive Buffer */
85 #define UBRDIV 0x0028 /* Baud Rate Divisor */
86 #define UFRACVAL 0x002C /* Divisor Fractional Value */
87 #define UINTP 0x0030 /* Interrupt Pending */
88 #define UINTSP 0x0034 /* Interrupt Source Pending */
89 #define UINTM 0x0038 /* Interrupt Mask */
92 * for indexing register in the uint32_t array
94 * 'reg' - register offset (see offsets definitions above)
97 #define I_(reg) (reg / sizeof(uint32_t))
99 typedef struct Exynos4210UartReg {
100 const char *name; /* the only reason is the debug output */
102 uint32_t reset_value;
105 static Exynos4210UartReg exynos4210_uart_regs[] = {
106 {"ULCON", ULCON, 0x00000000},
107 {"UCON", UCON, 0x00003000},
108 {"UFCON", UFCON, 0x00000000},
109 {"UMCON", UMCON, 0x00000000},
110 {"UTRSTAT", UTRSTAT, 0x00000006}, /* RO */
111 {"UERSTAT", UERSTAT, 0x00000000}, /* RO */
112 {"UFSTAT", UFSTAT, 0x00000000}, /* RO */
113 {"UMSTAT", UMSTAT, 0x00000000}, /* RO */
114 {"UTXH", UTXH, 0x5c5c5c5c}, /* WO, undefined reset value*/
115 {"URXH", URXH, 0x00000000}, /* RO */
116 {"UBRDIV", UBRDIV, 0x00000000},
117 {"UFRACVAL", UFRACVAL, 0x00000000},
118 {"UINTP", UINTP, 0x00000000},
119 {"UINTSP", UINTSP, 0x00000000},
120 {"UINTM", UINTM, 0x00000000},
123 #define EXYNOS4210_UART_REGS_MEM_SIZE 0x3C
125 /* UART FIFO Control */
126 #define UFCON_FIFO_ENABLE 0x1
127 #define UFCON_Rx_FIFO_RESET 0x2
128 #define UFCON_Tx_FIFO_RESET 0x4
129 #define UFCON_Tx_FIFO_TRIGGER_LEVEL_SHIFT 8
130 #define UFCON_Tx_FIFO_TRIGGER_LEVEL (7 << UFCON_Tx_FIFO_TRIGGER_LEVEL_SHIFT)
131 #define UFCON_Rx_FIFO_TRIGGER_LEVEL_SHIFT 4
132 #define UFCON_Rx_FIFO_TRIGGER_LEVEL (7 << UFCON_Rx_FIFO_TRIGGER_LEVEL_SHIFT)
134 /* Uart FIFO Status */
135 #define UFSTAT_Rx_FIFO_COUNT 0xff
136 #define UFSTAT_Rx_FIFO_FULL 0x100
137 #define UFSTAT_Rx_FIFO_ERROR 0x200
138 #define UFSTAT_Tx_FIFO_COUNT_SHIFT 16
139 #define UFSTAT_Tx_FIFO_COUNT (0xff << UFSTAT_Tx_FIFO_COUNT_SHIFT)
140 #define UFSTAT_Tx_FIFO_FULL_SHIFT 24
141 #define UFSTAT_Tx_FIFO_FULL (1 << UFSTAT_Tx_FIFO_FULL_SHIFT)
143 /* UART Interrupt Source Pending */
144 #define UINTSP_RXD 0x1 /* Receive interrupt */
145 #define UINTSP_ERROR 0x2 /* Error interrupt */
146 #define UINTSP_TXD 0x4 /* Transmit interrupt */
147 #define UINTSP_MODEM 0x8 /* Modem interrupt */
149 /* UART Line Control */
150 #define ULCON_IR_MODE_SHIFT 6
151 #define ULCON_PARITY_SHIFT 3
152 #define ULCON_STOP_BIT_SHIFT 1
154 /* UART Tx/Rx Status */
155 #define UTRSTAT_TRANSMITTER_EMPTY 0x4
156 #define UTRSTAT_Tx_BUFFER_EMPTY 0x2
157 #define UTRSTAT_Rx_BUFFER_DATA_READY 0x1
159 /* UART Error Status */
160 #define UERSTAT_OVERRUN 0x1
161 #define UERSTAT_PARITY 0x2
162 #define UERSTAT_FRAME 0x4
163 #define UERSTAT_BREAK 0x8
167 uint32_t sp, rp; /* store and retrieve pointers */
169 } Exynos4210UartFIFO;
171 #define TYPE_EXYNOS4210_UART "exynos4210.uart"
172 #define EXYNOS4210_UART(obj) \
173 OBJECT_CHECK(Exynos4210UartState, (obj), TYPE_EXYNOS4210_UART)
175 typedef struct Exynos4210UartState {
176 SysBusDevice parent_obj;
180 uint32_t reg[EXYNOS4210_UART_REGS_MEM_SIZE / sizeof(uint32_t)];
181 Exynos4210UartFIFO rx;
182 Exynos4210UartFIFO tx;
184 CharDriverState *chr;
189 } Exynos4210UartState;
193 /* Used only for debugging inside PRINT_DEBUG_... macros */
194 static const char *exynos4210_uart_regname(hwaddr offset)
199 for (i = 0; i < ARRAY_SIZE(exynos4210_uart_regs); i++) {
200 if (offset == exynos4210_uart_regs[i].offset) {
201 return exynos4210_uart_regs[i].name;
210 static void fifo_store(Exynos4210UartFIFO *q, uint8_t ch)
213 q->sp = (q->sp + 1) % q->size;
216 static uint8_t fifo_retrieve(Exynos4210UartFIFO *q)
218 uint8_t ret = q->data[q->rp];
219 q->rp = (q->rp + 1) % q->size;
223 static int fifo_elements_number(Exynos4210UartFIFO *q)
226 return q->size - q->rp + q->sp;
229 return q->sp - q->rp;
232 static int fifo_empty_elements_number(Exynos4210UartFIFO *q)
234 return q->size - fifo_elements_number(q);
237 static void fifo_reset(Exynos4210UartFIFO *q)
242 q->data = (uint8_t *)g_malloc0(q->size);
248 static uint32_t exynos4210_uart_Tx_FIFO_trigger_level(Exynos4210UartState *s)
253 reg = (s->reg[I_(UFCON)] & UFCON_Tx_FIFO_TRIGGER_LEVEL) >>
254 UFCON_Tx_FIFO_TRIGGER_LEVEL_SHIFT;
256 switch (s->channel) {
270 PRINT_ERROR("Wrong UART channel number: %d\n", s->channel);
276 static void exynos4210_uart_update_irq(Exynos4210UartState *s)
279 * The Tx interrupt is always requested if the number of data in the
280 * transmit FIFO is smaller than the trigger level.
282 if (s->reg[I_(UFCON)] & UFCON_FIFO_ENABLE) {
284 uint32_t count = (s->reg[I_(UFSTAT)] & UFSTAT_Tx_FIFO_COUNT) >>
285 UFSTAT_Tx_FIFO_COUNT_SHIFT;
287 if (count <= exynos4210_uart_Tx_FIFO_trigger_level(s)) {
288 s->reg[I_(UINTSP)] |= UINTSP_TXD;
292 s->reg[I_(UINTP)] = s->reg[I_(UINTSP)] & ~s->reg[I_(UINTM)];
294 if (s->reg[I_(UINTP)]) {
295 qemu_irq_raise(s->irq);
298 fprintf(stderr, "UART%d: IRQ has been raised: %08x\n",
299 s->channel, s->reg[I_(UINTP)]);
303 qemu_irq_lower(s->irq);
307 static void exynos4210_uart_update_parameters(Exynos4210UartState *s)
309 int speed, parity, data_bits, stop_bits, frame_size;
310 QEMUSerialSetParams ssp;
313 if (s->reg[I_(UBRDIV)] == 0) {
317 frame_size = 1; /* start bit */
318 if (s->reg[I_(ULCON)] & 0x20) {
319 frame_size++; /* parity bit */
320 if (s->reg[I_(ULCON)] & 0x28) {
329 if (s->reg[I_(ULCON)] & 0x4) {
335 data_bits = (s->reg[I_(ULCON)] & 0x3) + 5;
337 frame_size += data_bits + stop_bits;
339 uclk_rate = 24000000;
341 speed = uclk_rate / ((16 * (s->reg[I_(UBRDIV)]) & 0xffff) +
342 (s->reg[I_(UFRACVAL)] & 0x7) + 16);
346 ssp.data_bits = data_bits;
347 ssp.stop_bits = stop_bits;
349 qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_SERIAL_SET_PARAMS, &ssp);
351 PRINT_DEBUG("UART%d: speed: %d, parity: %c, data: %d, stop: %d\n",
352 s->channel, speed, parity, data_bits, stop_bits);
355 static void exynos4210_uart_write(void *opaque, hwaddr offset,
356 uint64_t val, unsigned size)
358 Exynos4210UartState *s = (Exynos4210UartState *)opaque;
361 PRINT_DEBUG_EXTEND("UART%d: <0x%04x> %s <- 0x%08llx\n", s->channel,
362 offset, exynos4210_uart_regname(offset), (long long unsigned int)val);
368 s->reg[I_(offset)] = val;
369 exynos4210_uart_update_parameters(s);
372 s->reg[I_(UFCON)] = val;
373 if (val & UFCON_Rx_FIFO_RESET) {
375 s->reg[I_(UFCON)] &= ~UFCON_Rx_FIFO_RESET;
376 PRINT_DEBUG("UART%d: Rx FIFO Reset\n", s->channel);
378 if (val & UFCON_Tx_FIFO_RESET) {
380 s->reg[I_(UFCON)] &= ~UFCON_Tx_FIFO_RESET;
381 PRINT_DEBUG("UART%d: Tx FIFO Reset\n", s->channel);
387 s->reg[I_(UTRSTAT)] &= ~(UTRSTAT_TRANSMITTER_EMPTY |
388 UTRSTAT_Tx_BUFFER_EMPTY);
390 qemu_chr_fe_write(s->chr, &ch, 1);
392 fprintf(stderr, "%c", ch);
394 s->reg[I_(UTRSTAT)] |= UTRSTAT_TRANSMITTER_EMPTY |
395 UTRSTAT_Tx_BUFFER_EMPTY;
396 s->reg[I_(UINTSP)] |= UINTSP_TXD;
397 exynos4210_uart_update_irq(s);
402 s->reg[I_(UINTP)] &= ~val;
403 s->reg[I_(UINTSP)] &= ~val;
404 PRINT_DEBUG("UART%d: UINTP [%04x] have been cleared: %08x\n",
405 s->channel, offset, s->reg[I_(UINTP)]);
406 exynos4210_uart_update_irq(s);
413 PRINT_DEBUG("UART%d: Trying to write into RO register: %s [%04x]\n",
414 s->channel, exynos4210_uart_regname(offset), offset);
417 s->reg[I_(UINTSP)] &= ~val;
420 s->reg[I_(UINTM)] = val;
421 exynos4210_uart_update_irq(s);
426 s->reg[I_(offset)] = val;
430 static uint64_t exynos4210_uart_read(void *opaque, hwaddr offset,
433 Exynos4210UartState *s = (Exynos4210UartState *)opaque;
437 case UERSTAT: /* Read Only */
438 res = s->reg[I_(UERSTAT)];
439 s->reg[I_(UERSTAT)] = 0;
441 case UFSTAT: /* Read Only */
442 s->reg[I_(UFSTAT)] = fifo_elements_number(&s->rx) & 0xff;
443 if (fifo_empty_elements_number(&s->rx) == 0) {
444 s->reg[I_(UFSTAT)] |= UFSTAT_Rx_FIFO_FULL;
445 s->reg[I_(UFSTAT)] &= ~0xff;
447 return s->reg[I_(UFSTAT)];
449 if (s->reg[I_(UFCON)] & UFCON_FIFO_ENABLE) {
450 if (fifo_elements_number(&s->rx)) {
451 res = fifo_retrieve(&s->rx);
453 fprintf(stderr, "%c", res);
455 if (!fifo_elements_number(&s->rx)) {
456 s->reg[I_(UTRSTAT)] &= ~UTRSTAT_Rx_BUFFER_DATA_READY;
458 s->reg[I_(UTRSTAT)] |= UTRSTAT_Rx_BUFFER_DATA_READY;
461 s->reg[I_(UINTSP)] |= UINTSP_ERROR;
462 exynos4210_uart_update_irq(s);
466 s->reg[I_(UTRSTAT)] &= ~UTRSTAT_Rx_BUFFER_DATA_READY;
467 res = s->reg[I_(URXH)];
471 PRINT_DEBUG("UART%d: Trying to read from WO register: %s [%04x]\n",
472 s->channel, exynos4210_uart_regname(offset), offset);
475 return s->reg[I_(offset)];
481 static const MemoryRegionOps exynos4210_uart_ops = {
482 .read = exynos4210_uart_read,
483 .write = exynos4210_uart_write,
484 .endianness = DEVICE_NATIVE_ENDIAN,
486 .max_access_size = 4,
491 static int exynos4210_uart_can_receive(void *opaque)
493 Exynos4210UartState *s = (Exynos4210UartState *)opaque;
495 return fifo_empty_elements_number(&s->rx);
499 static void exynos4210_uart_receive(void *opaque, const uint8_t *buf, int size)
501 Exynos4210UartState *s = (Exynos4210UartState *)opaque;
504 if (s->reg[I_(UFCON)] & UFCON_FIFO_ENABLE) {
505 if (fifo_empty_elements_number(&s->rx) < size) {
506 for (i = 0; i < fifo_empty_elements_number(&s->rx); i++) {
507 fifo_store(&s->rx, buf[i]);
509 s->reg[I_(UINTSP)] |= UINTSP_ERROR;
510 s->reg[I_(UTRSTAT)] |= UTRSTAT_Rx_BUFFER_DATA_READY;
512 for (i = 0; i < size; i++) {
513 fifo_store(&s->rx, buf[i]);
515 s->reg[I_(UTRSTAT)] |= UTRSTAT_Rx_BUFFER_DATA_READY;
517 /* XXX: Around here we maybe should check Rx trigger level */
518 s->reg[I_(UINTSP)] |= UINTSP_RXD;
520 s->reg[I_(URXH)] = buf[0];
521 s->reg[I_(UINTSP)] |= UINTSP_RXD;
522 s->reg[I_(UTRSTAT)] |= UTRSTAT_Rx_BUFFER_DATA_READY;
525 exynos4210_uart_update_irq(s);
529 static void exynos4210_uart_event(void *opaque, int event)
531 Exynos4210UartState *s = (Exynos4210UartState *)opaque;
533 if (event == CHR_EVENT_BREAK) {
534 /* When the RxDn is held in logic 0, then a null byte is pushed into the
536 fifo_store(&s->rx, '\0');
537 s->reg[I_(UERSTAT)] |= UERSTAT_BREAK;
538 exynos4210_uart_update_irq(s);
543 static void exynos4210_uart_reset(DeviceState *dev)
545 Exynos4210UartState *s = EXYNOS4210_UART(dev);
548 for (i = 0; i < ARRAY_SIZE(exynos4210_uart_regs); i++) {
549 s->reg[I_(exynos4210_uart_regs[i].offset)] =
550 exynos4210_uart_regs[i].reset_value;
556 PRINT_DEBUG("UART%d: Rx FIFO size: %d\n", s->channel, s->rx.size);
559 static const VMStateDescription vmstate_exynos4210_uart_fifo = {
560 .name = "exynos4210.uart.fifo",
562 .minimum_version_id = 1,
563 .fields = (VMStateField[]) {
564 VMSTATE_UINT32(sp, Exynos4210UartFIFO),
565 VMSTATE_UINT32(rp, Exynos4210UartFIFO),
566 VMSTATE_VBUFFER_UINT32(data, Exynos4210UartFIFO, 1, NULL, 0, size),
567 VMSTATE_END_OF_LIST()
571 static const VMStateDescription vmstate_exynos4210_uart = {
572 .name = "exynos4210.uart",
574 .minimum_version_id = 1,
575 .fields = (VMStateField[]) {
576 VMSTATE_STRUCT(rx, Exynos4210UartState, 1,
577 vmstate_exynos4210_uart_fifo, Exynos4210UartFIFO),
578 VMSTATE_UINT32_ARRAY(reg, Exynos4210UartState,
579 EXYNOS4210_UART_REGS_MEM_SIZE / sizeof(uint32_t)),
580 VMSTATE_END_OF_LIST()
584 DeviceState *exynos4210_uart_create(hwaddr addr,
587 CharDriverState *chr,
593 const char chr_name[] = "serial";
594 char label[ARRAY_SIZE(chr_name) + 1];
596 dev = qdev_create(NULL, TYPE_EXYNOS4210_UART);
599 if (channel >= MAX_SERIAL_PORTS) {
600 error_report("Only %d serial ports are supported by QEMU",
604 chr = serial_hds[channel];
606 snprintf(label, ARRAY_SIZE(label), "%s%d", chr_name, channel);
607 chr = qemu_chr_new(label, "null", NULL);
609 error_report("Can't assign serial port to UART%d", channel);
615 qdev_prop_set_chr(dev, "chardev", chr);
616 qdev_prop_set_uint32(dev, "channel", channel);
617 qdev_prop_set_uint32(dev, "rx-size", fifo_size);
618 qdev_prop_set_uint32(dev, "tx-size", fifo_size);
620 bus = SYS_BUS_DEVICE(dev);
621 qdev_init_nofail(dev);
622 if (addr != (hwaddr)-1) {
623 sysbus_mmio_map(bus, 0, addr);
625 sysbus_connect_irq(bus, 0, irq);
630 static int exynos4210_uart_init(SysBusDevice *dev)
632 Exynos4210UartState *s = EXYNOS4210_UART(dev);
635 memory_region_init_io(&s->iomem, OBJECT(s), &exynos4210_uart_ops, s,
636 "exynos4210.uart", EXYNOS4210_UART_REGS_MEM_SIZE);
637 sysbus_init_mmio(dev, &s->iomem);
639 sysbus_init_irq(dev, &s->irq);
641 qemu_chr_add_handlers(s->chr, exynos4210_uart_can_receive,
642 exynos4210_uart_receive, exynos4210_uart_event, s);
647 static Property exynos4210_uart_properties[] = {
648 DEFINE_PROP_CHR("chardev", Exynos4210UartState, chr),
649 DEFINE_PROP_UINT32("channel", Exynos4210UartState, channel, 0),
650 DEFINE_PROP_UINT32("rx-size", Exynos4210UartState, rx.size, 16),
651 DEFINE_PROP_UINT32("tx-size", Exynos4210UartState, tx.size, 16),
652 DEFINE_PROP_END_OF_LIST(),
655 static void exynos4210_uart_class_init(ObjectClass *klass, void *data)
657 DeviceClass *dc = DEVICE_CLASS(klass);
658 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
660 k->init = exynos4210_uart_init;
661 dc->reset = exynos4210_uart_reset;
662 dc->props = exynos4210_uart_properties;
663 dc->vmsd = &vmstate_exynos4210_uart;
666 static const TypeInfo exynos4210_uart_info = {
667 .name = TYPE_EXYNOS4210_UART,
668 .parent = TYPE_SYS_BUS_DEVICE,
669 .instance_size = sizeof(Exynos4210UartState),
670 .class_init = exynos4210_uart_class_init,
673 static void exynos4210_uart_register(void)
675 type_register_static(&exynos4210_uart_info);
678 type_init(exynos4210_uart_register)