X-Git-Url: https://gerrit.opnfv.org/gerrit/gitweb?p=kvmfornfv.git;a=blobdiff_plain;f=kernel%2Farch%2Farm%2Fmach-omap1%2Firq.c;h=b11edc8a46f0ec0c549969987ebfaec803ae11ac;hp=a8a533df24e102a12a01f6b0897209b014a0bc60;hb=e09b41010ba33a20a87472ee821fa407a5b8da36;hpb=f93b97fd65072de626c074dbe099a1fff05ce060 diff --git a/kernel/arch/arm/mach-omap1/irq.c b/kernel/arch/arm/mach-omap1/irq.c index a8a533df2..b11edc8a4 100644 --- a/kernel/arch/arm/mach-omap1/irq.c +++ b/kernel/arch/arm/mach-omap1/irq.c @@ -43,6 +43,7 @@ #include #include +#include #include #include "soc.h" @@ -56,66 +57,41 @@ struct omap_irq_bank { unsigned long base_reg; + void __iomem *va; unsigned long trigger_map; unsigned long wake_enable; }; -u32 omap_irq_flags; +static u32 omap_l2_irq; static unsigned int irq_bank_count; static struct omap_irq_bank *irq_banks; +static struct irq_domain *domain; -static inline void irq_bank_writel(unsigned long value, int bank, int offset) -{ - omap_writel(value, irq_banks[bank].base_reg + offset); -} - -static void omap_ack_irq(struct irq_data *d) +static inline unsigned int irq_bank_readl(int bank, int offset) { - if (d->irq > 31) - omap_writel(0x1, OMAP_IH2_BASE + IRQ_CONTROL_REG_OFFSET); - - omap_writel(0x1, OMAP_IH1_BASE + IRQ_CONTROL_REG_OFFSET); + return readl_relaxed(irq_banks[bank].va + offset); } - -static void omap_mask_irq(struct irq_data *d) +static inline void irq_bank_writel(unsigned long value, int bank, int offset) { - int bank = IRQ_BANK(d->irq); - u32 l; - - l = omap_readl(irq_banks[bank].base_reg + IRQ_MIR_REG_OFFSET); - l |= 1 << IRQ_BIT(d->irq); - omap_writel(l, irq_banks[bank].base_reg + IRQ_MIR_REG_OFFSET); + writel_relaxed(value, irq_banks[bank].va + offset); } -static void omap_unmask_irq(struct irq_data *d) +static void omap_ack_irq(int irq) { - int bank = IRQ_BANK(d->irq); - u32 l; + if (irq > 31) + writel_relaxed(0x1, irq_banks[1].va + IRQ_CONTROL_REG_OFFSET); - l = omap_readl(irq_banks[bank].base_reg + IRQ_MIR_REG_OFFSET); - l &= ~(1 << IRQ_BIT(d->irq)); - omap_writel(l, irq_banks[bank].base_reg + IRQ_MIR_REG_OFFSET); + writel_relaxed(0x1, irq_banks[0].va + IRQ_CONTROL_REG_OFFSET); } static void omap_mask_ack_irq(struct irq_data *d) { - omap_mask_irq(d); - omap_ack_irq(d); -} - -static int omap_wake_irq(struct irq_data *d, unsigned int enable) -{ - int bank = IRQ_BANK(d->irq); - - if (enable) - irq_banks[bank].wake_enable |= IRQ_BIT(d->irq); - else - irq_banks[bank].wake_enable &= ~IRQ_BIT(d->irq); + struct irq_chip_type *ct = irq_data_get_chip_type(d); - return 0; + ct->chip.irq_mask(d); + omap_ack_irq(d->irq); } - /* * Allows tuning the IRQ type and priority * @@ -165,46 +141,105 @@ static struct omap_irq_bank omap1610_irq_banks[] = { }; #endif -static struct irq_chip omap_irq_chip = { - .name = "MPU", - .irq_ack = omap_mask_ack_irq, - .irq_mask = omap_mask_irq, - .irq_unmask = omap_unmask_irq, - .irq_set_wake = omap_wake_irq, -}; +asmlinkage void __exception_irq_entry omap1_handle_irq(struct pt_regs *regs) +{ + void __iomem *l1 = irq_banks[0].va; + void __iomem *l2 = irq_banks[1].va; + u32 irqnr; + + do { + irqnr = readl_relaxed(l1 + IRQ_ITR_REG_OFFSET); + irqnr &= ~(readl_relaxed(l1 + IRQ_MIR_REG_OFFSET) & 0xffffffff); + if (!irqnr) + break; + + irqnr = readl_relaxed(l1 + IRQ_SIR_FIQ_REG_OFFSET); + if (irqnr) + goto irq; + + irqnr = readl_relaxed(l1 + IRQ_SIR_IRQ_REG_OFFSET); + if (irqnr == omap_l2_irq) { + irqnr = readl_relaxed(l2 + IRQ_SIR_IRQ_REG_OFFSET); + if (irqnr) + irqnr += 32; + } +irq: + if (irqnr) + handle_domain_irq(domain, irqnr, regs); + else + break; + } while (irqnr); +} + +static __init void +omap_alloc_gc(void __iomem *base, unsigned int irq_start, unsigned int num) +{ + struct irq_chip_generic *gc; + struct irq_chip_type *ct; + + gc = irq_alloc_generic_chip("MPU", 1, irq_start, base, + handle_level_irq); + ct = gc->chip_types; + ct->chip.irq_ack = omap_mask_ack_irq; + ct->chip.irq_mask = irq_gc_mask_set_bit; + ct->chip.irq_unmask = irq_gc_mask_clr_bit; + ct->chip.irq_set_wake = irq_gc_set_wake; + ct->regs.mask = IRQ_MIR_REG_OFFSET; + irq_setup_generic_chip(gc, IRQ_MSK(num), IRQ_GC_INIT_MASK_CACHE, + IRQ_NOREQUEST | IRQ_NOPROBE, 0); +} void __init omap1_init_irq(void) { - int i, j; + struct irq_chip_type *ct; + struct irq_data *d = NULL; + int i, j, irq_base; + unsigned long nr_irqs; #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850) if (cpu_is_omap7xx()) { - omap_irq_flags = INT_7XX_IH2_IRQ; irq_banks = omap7xx_irq_banks; irq_bank_count = ARRAY_SIZE(omap7xx_irq_banks); } #endif #ifdef CONFIG_ARCH_OMAP15XX if (cpu_is_omap1510()) { - omap_irq_flags = INT_1510_IH2_IRQ; irq_banks = omap1510_irq_banks; irq_bank_count = ARRAY_SIZE(omap1510_irq_banks); } if (cpu_is_omap310()) { - omap_irq_flags = INT_1510_IH2_IRQ; irq_banks = omap310_irq_banks; irq_bank_count = ARRAY_SIZE(omap310_irq_banks); } #endif #if defined(CONFIG_ARCH_OMAP16XX) if (cpu_is_omap16xx()) { - omap_irq_flags = INT_1510_IH2_IRQ; irq_banks = omap1610_irq_banks; irq_bank_count = ARRAY_SIZE(omap1610_irq_banks); } #endif - printk("Total of %i interrupts in %i interrupt banks\n", - irq_bank_count * 32, irq_bank_count); + + for (i = 0; i < irq_bank_count; i++) { + irq_banks[i].va = ioremap(irq_banks[i].base_reg, 0xff); + if (WARN_ON(!irq_banks[i].va)) + return; + } + + nr_irqs = irq_bank_count * 32; + + irq_base = irq_alloc_descs(-1, 0, nr_irqs, 0); + if (irq_base < 0) { + pr_warn("Couldn't allocate IRQ numbers\n"); + irq_base = 0; + } + omap_l2_irq = cpu_is_omap7xx() ? irq_base + 1 : irq_base; + omap_l2_irq -= NR_IRQS_LEGACY; + + domain = irq_domain_add_legacy(NULL, nr_irqs, irq_base, 0, + &irq_domain_simple_ops, NULL); + + pr_info("Total of %lu interrupts in %i interrupt banks\n", + nr_irqs, irq_bank_count); /* Mask and clear all interrupts */ for (i = 0; i < irq_bank_count; i++) { @@ -227,19 +262,15 @@ void __init omap1_init_irq(void) irq_trigger = irq_banks[i].trigger_map >> IRQ_BIT(j); omap_irq_set_cfg(j, 0, 0, irq_trigger); - - irq_set_chip_and_handler(j, &omap_irq_chip, - handle_level_irq); - set_irq_flags(j, IRQF_VALID); + irq_clear_status_flags(j, IRQ_NOREQUEST); } + omap_alloc_gc(irq_banks[i].va, irq_base + i * 32, 32); } /* Unmask level 2 handler */ - - if (cpu_is_omap7xx()) - omap_unmask_irq(irq_get_irq_data(INT_7XX_IH2_IRQ)); - else if (cpu_is_omap15xx()) - omap_unmask_irq(irq_get_irq_data(INT_1510_IH2_IRQ)); - else if (cpu_is_omap16xx()) - omap_unmask_irq(irq_get_irq_data(INT_1610_IH2_IRQ)); + d = irq_get_irq_data(irq_find_mapping(domain, omap_l2_irq)); + if (d) { + ct = irq_data_get_chip_type(d); + ct->chip.irq_unmask(d); + } }