*/
+#include "qemu/osdep.h"
#include "cpu.h"
#include "disas/disas.h"
#include "tcg-op.h"
#include "exec/helper-gen.h"
#include "tricore-opcodes.h"
+#include "exec/log.h"
/*
* TCG registers
static TCGv cpu_PSW_AV;
static TCGv cpu_PSW_SAV;
/* CPU env */
-static TCGv_ptr cpu_env;
+static TCGv_env cpu_env;
#include "exec/gen-icount.h"
#define EA_B_ABSOLUT(con) (((offset & 0xf00000) << 8) | \
((offset & 0x0fffff) << 1))
+/* For two 32-bit registers used a 64-bit register, the first
+ registernumber needs to be even. Otherwise we trap. */
+static inline void generate_trap(DisasContext *ctx, int class, int tin);
+#define CHECK_REG_PAIR(reg) do { \
+ if (reg & 0x1) { \
+ generate_trap(ctx, TRAPC_INSN_ERR, TIN2_OPD); \
+ } \
+} while (0)
+
/* Functions for load/save to/from memory */
static inline void gen_offset_ld(DisasContext *ctx, TCGv r1, TCGv r2,
TCGv temp = tcg_temp_new();
TCGv temp2 = tcg_temp_new();
+ CHECK_REG_PAIR(ereg);
/* temp = (M(EA, word) */
tcg_gen_qemu_ld_tl(temp, ea, ctx->mem_idx, MO_LEUL);
/* temp = temp & ~E[a][63:32]) */
tcg_gen_xor_i64(t1, result, r1);
tcg_gen_xor_i64(t0, r1, r2);
tcg_gen_andc_i64(t1, t1, t0);
- tcg_gen_trunc_shr_i64_i32(cpu_PSW_V, t1, 32);
+ tcg_gen_extrh_i64_i32(cpu_PSW_V, t1);
/* calc SV bit */
tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
/* calc AV/SAV bits */
- tcg_gen_trunc_shr_i64_i32(temp, result, 32);
+ tcg_gen_extrh_i64_i32(temp, result);
tcg_gen_add_tl(cpu_PSW_AV, temp, temp);
tcg_gen_xor_tl(cpu_PSW_AV, temp, cpu_PSW_AV);
/* calc SAV */
tcg_gen_mul_i64(t1, t1, t3);
tcg_gen_add_i64(t1, t2, t1);
- tcg_gen_trunc_i64_i32(ret, t1);
+ tcg_gen_extrl_i64_i32(ret, t1);
/* calc V
t1 > 0x7fffffff */
tcg_gen_setcondi_i64(TCG_COND_GT, t3, t1, 0x7fffffffLL);
/* t1 < -0x80000000 */
tcg_gen_setcondi_i64(TCG_COND_LT, t2, t1, -0x80000000LL);
tcg_gen_or_i64(t2, t2, t3);
- tcg_gen_trunc_i64_i32(cpu_PSW_V, t2);
+ tcg_gen_extrl_i64_i32(cpu_PSW_V, t2);
tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31);
/* Calc SV bit */
tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
/* only the add overflows, if t2 < t1
calc V bit */
tcg_gen_setcond_i64(TCG_COND_LTU, t2, t2, t1);
- tcg_gen_trunc_i64_i32(cpu_PSW_V, t2);
+ tcg_gen_extrl_i64_i32(cpu_PSW_V, t2);
tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31);
/* Calc SV bit */
tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
tcg_gen_sari_i64(t2, t2, up_shift);
tcg_gen_add_i64(t3, t1, t2);
- tcg_gen_trunc_i64_i32(temp3, t3);
+ tcg_gen_extrl_i64_i32(temp3, t3);
/* calc v bit */
tcg_gen_setcondi_i64(TCG_COND_GT, t1, t3, 0x7fffffffLL);
tcg_gen_setcondi_i64(TCG_COND_LT, t2, t3, -0x80000000LL);
tcg_gen_or_i64(t1, t1, t2);
- tcg_gen_trunc_i64_i32(cpu_PSW_V, t1);
+ tcg_gen_extrl_i64_i32(cpu_PSW_V, t1);
tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31);
/* We produce an overflow on the host if the mul before was
(0x80000000 * 0x80000000) << 1). If this is the
tcg_gen_xor_i64(t3, t4, t1);
tcg_gen_xor_i64(t2, t1, t2);
tcg_gen_andc_i64(t3, t3, t2);
- tcg_gen_trunc_shr_i64_i32(cpu_PSW_V, t3, 32);
+ tcg_gen_extrh_i64_i32(cpu_PSW_V, t3);
/* We produce an overflow on the host if the mul before was
(0x80000000 * 0x80000000) << 1). If this is the
case, we negate the ovf. */
tcg_gen_mul_i64(t1, t1, t3);
tcg_gen_sub_i64(t1, t2, t1);
- tcg_gen_trunc_i64_i32(ret, t1);
+ tcg_gen_extrl_i64_i32(ret, t1);
/* calc V
t2 > 0x7fffffff */
tcg_gen_setcondi_i64(TCG_COND_GT, t3, t1, 0x7fffffffLL);
/* result < -0x80000000 */
tcg_gen_setcondi_i64(TCG_COND_LT, t2, t1, -0x80000000LL);
tcg_gen_or_i64(t2, t2, t3);
- tcg_gen_trunc_i64_i32(cpu_PSW_V, t2);
+ tcg_gen_extrl_i64_i32(cpu_PSW_V, t2);
tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31);
/* Calc SV bit */
tcg_gen_extr_i64_i32(ret_low, ret_high, t3);
/* calc V bit, only the sub can overflow, if t1 > t2 */
tcg_gen_setcond_i64(TCG_COND_GTU, t1, t1, t2);
- tcg_gen_trunc_i64_i32(cpu_PSW_V, t1);
+ tcg_gen_extrl_i64_i32(cpu_PSW_V, t1);
tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31);
/* Calc SV bit */
tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
tcg_gen_xor_i64(t1, result, r1);
tcg_gen_xor_i64(t0, r1, r2);
tcg_gen_and_i64(t1, t1, t0);
- tcg_gen_trunc_shr_i64_i32(cpu_PSW_V, t1, 32);
+ tcg_gen_extrh_i64_i32(cpu_PSW_V, t1);
/* calc SV bit */
tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
/* calc AV/SAV bits */
- tcg_gen_trunc_shr_i64_i32(temp, result, 32);
+ tcg_gen_extrh_i64_i32(temp, result);
tcg_gen_add_tl(cpu_PSW_AV, temp, temp);
tcg_gen_xor_tl(cpu_PSW_AV, temp, cpu_PSW_AV);
/* calc SAV */
tcg_gen_add_i64(t2, t2, t4);
tcg_gen_sub_i64(t3, t1, t2);
- tcg_gen_trunc_i64_i32(temp3, t3);
+ tcg_gen_extrl_i64_i32(temp3, t3);
/* calc v bit */
tcg_gen_setcondi_i64(TCG_COND_GT, t1, t3, 0x7fffffffLL);
tcg_gen_setcondi_i64(TCG_COND_LT, t2, t3, -0x80000000LL);
tcg_gen_or_i64(t1, t1, t2);
- tcg_gen_trunc_i64_i32(cpu_PSW_V, t1);
+ tcg_gen_extrl_i64_i32(cpu_PSW_V, t1);
tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31);
/* Calc SV bit */
tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
tcg_gen_xor_i64(t3, t4, t1);
tcg_gen_xor_i64(t2, t1, t2);
tcg_gen_and_i64(t3, t3, t2);
- tcg_gen_trunc_shr_i64_i32(cpu_PSW_V, t3, 32);
+ tcg_gen_extrh_i64_i32(cpu_PSW_V, t3);
/* We produce an overflow on the host if the mul before was
(0x80000000 * 0x80000000) << 1). If this is the
case, we negate the ovf. */
}
}
+static void generate_trap(DisasContext *ctx, int class, int tin)
+{
+ TCGv_i32 classtemp = tcg_const_i32(class);
+ TCGv_i32 tintemp = tcg_const_i32(tin);
+
+ gen_save_pc(ctx->pc);
+ gen_helper_raise_exception_sync(cpu_env, classtemp, tintemp);
+ ctx->bstate = BS_EXCP;
+
+ tcg_temp_free(classtemp);
+ tcg_temp_free(tintemp);
+}
+
static inline void gen_branch_cond(DisasContext *ctx, TCGCond cond, TCGv r1,
TCGv r2, int16_t address)
{
}
break;
default:
- printf("Branch Error at %x\n", ctx->pc);
+ generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
ctx->bstate = BS_BRANCH;
}
if (tricore_feature(env, TRICORE_FEATURE_16)) {
tcg_gen_movi_tl(cpu_gpr_d[r1], const4);
tcg_gen_sari_tl(cpu_gpr_d[r1+1], cpu_gpr_d[r1], 31);
- } /* TODO: else raise illegal opcode trap */
+ } else {
+ generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
+ }
break;
case OPC1_16_SRC_SH:
gen_shi(cpu_gpr_d[r1], cpu_gpr_d[r1], const4);
case OPC1_16_SRC_SHA:
gen_shaci(cpu_gpr_d[r1], cpu_gpr_d[r1], const4);
break;
+ default:
+ generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
}
case OPC1_16_SRR_XOR:
tcg_gen_xor_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]);
break;
+ default:
+ generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
}
tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LEUL);
tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 4);
break;
+ default:
+ generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
}
case OPC1_16_SC_SUB_A:
tcg_gen_subi_tl(cpu_gpr_a[10], cpu_gpr_a[10], const16);
break;
+ default:
+ generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
}
tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LESL);
tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 4);
break;
+ default:
+ generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
}
case OPC1_16_SRO_ST_W:
gen_offset_st(ctx, cpu_gpr_d[15], cpu_gpr_a[r2], address * 4, MO_LESL);
break;
+ default:
+ generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
}
break;
case OPC2_16_SR_FRET:
gen_fret(ctx);
+ break;
+ default:
+ generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
}
case OPC2_16_SR_SAT_HU:
gen_saturate_u(cpu_gpr_d[r1], cpu_gpr_d[r1], 0xffff);
break;
+ default:
+ generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
}
r1 = MASK_OP_SR_S1D(ctx->opcode);
tcg_gen_not_tl(cpu_gpr_d[r1], cpu_gpr_d[r1]);
break;
+ default:
+ generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
}
tcg_gen_qemu_ld_tl(cpu_gpr_a[r1], temp, ctx->mem_idx, MO_LESL);
break;
case OPC2_32_ABS_LD_D:
+ CHECK_REG_PAIR(r1);
gen_ld_2regs_64(cpu_gpr_d[r1+1], cpu_gpr_d[r1], temp, ctx);
break;
case OPC2_32_ABS_LD_DA:
+ CHECK_REG_PAIR(r1);
gen_ld_2regs_64(cpu_gpr_a[r1+1], cpu_gpr_a[r1], temp, ctx);
break;
case OPC2_32_ABS_LD_W:
tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_LESL);
break;
+ default:
+ generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
tcg_temp_free(temp);
case OPC2_32_ABS_LD_HU:
tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_LEUW);
break;
+ default:
+ generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
tcg_temp_free(temp);
case OPC2_32_ABS_SWAP_W:
gen_swap(ctx, r1, temp);
break;
+ default:
+ generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
tcg_temp_free(temp);
case OPC2_32_ABS_STUCX:
gen_helper_1arg(stucx, EA_ABS_FORMAT(off18));
break;
+ default:
+ generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
}
tcg_gen_qemu_st_tl(cpu_gpr_a[r1], temp, ctx->mem_idx, MO_LESL);
break;
case OPC2_32_ABS_ST_D:
+ CHECK_REG_PAIR(r1);
gen_st_2regs_64(cpu_gpr_d[r1+1], cpu_gpr_d[r1], temp, ctx);
break;
case OPC2_32_ABS_ST_DA:
+ CHECK_REG_PAIR(r1);
gen_st_2regs_64(cpu_gpr_a[r1+1], cpu_gpr_a[r1], temp, ctx);
break;
case OPC2_32_ABS_ST_W:
tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_LESL);
break;
-
+ default:
+ generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
tcg_temp_free(temp);
}
case OPC2_32_ABS_ST_H:
tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_LEUW);
break;
+ default:
+ generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
tcg_temp_free(temp);
}
gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
pos1, pos2, &tcg_gen_or_tl, &tcg_gen_and_tl);
break;
+ default:
+ generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
}
gen_bit_1op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
pos1, pos2, &tcg_gen_or_tl);
break;
+ default:
+ generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
}
gen_bit_1op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
pos1, pos2, &tcg_gen_xor_tl);
break;
+ default:
+ generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
}
gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
pos1, pos2, &tcg_gen_or_tl, &tcg_gen_or_tl);
break;
+ default:
+ generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
}
gen_bit_1op(temp, cpu_gpr_d[r1], cpu_gpr_d[r2],
pos1, pos2, &tcg_gen_or_tl);
break;
+ default:
+ generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
tcg_gen_shli_tl(cpu_gpr_d[r3], cpu_gpr_d[r3], 1);
tcg_gen_add_tl(cpu_gpr_d[r3], cpu_gpr_d[r3], temp);
gen_bit_1op(temp, cpu_gpr_d[r1], cpu_gpr_d[r2],
pos1, pos2, &tcg_gen_xor_tl);
break;
+ default:
+ generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
tcg_gen_shli_tl(cpu_gpr_d[r3], cpu_gpr_d[r3], 1);
tcg_gen_add_tl(cpu_gpr_d[r3], cpu_gpr_d[r3], temp);
break;
case OPC2_32_BO_CACHEI_WI_SHORTOFF:
case OPC2_32_BO_CACHEI_W_SHORTOFF:
- /* TODO: Raise illegal opcode trap,
- if !tricore_feature(TRICORE_FEATURE_131) */
+ if (!tricore_feature(env, TRICORE_FEATURE_131)) {
+ generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
+ }
break;
case OPC2_32_BO_CACHEI_W_POSTINC:
case OPC2_32_BO_CACHEI_WI_POSTINC:
if (tricore_feature(env, TRICORE_FEATURE_131)) {
tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
- } /* TODO: else raise illegal opcode trap */
+ } else {
+ generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
+ }
break;
case OPC2_32_BO_CACHEI_W_PREINC:
case OPC2_32_BO_CACHEI_WI_PREINC:
if (tricore_feature(env, TRICORE_FEATURE_131)) {
tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
- } /* TODO: else raise illegal opcode trap */
+ } else {
+ generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
+ }
break;
case OPC2_32_BO_ST_A_SHORTOFF:
gen_offset_st(ctx, cpu_gpr_a[r1], cpu_gpr_a[r2], off10, MO_LESL);
gen_st_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_UB);
break;
case OPC2_32_BO_ST_D_SHORTOFF:
+ CHECK_REG_PAIR(r1);
gen_offset_st_2regs(cpu_gpr_d[r1+1], cpu_gpr_d[r1], cpu_gpr_a[r2],
off10, ctx);
break;
case OPC2_32_BO_ST_D_POSTINC:
+ CHECK_REG_PAIR(r1);
gen_st_2regs_64(cpu_gpr_d[r1+1], cpu_gpr_d[r1], cpu_gpr_a[r2], ctx);
tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
break;
case OPC2_32_BO_ST_D_PREINC:
+ CHECK_REG_PAIR(r1);
temp = tcg_temp_new();
tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10);
gen_st_2regs_64(cpu_gpr_d[r1+1], cpu_gpr_d[r1], temp, ctx);
tcg_temp_free(temp);
break;
case OPC2_32_BO_ST_DA_SHORTOFF:
+ CHECK_REG_PAIR(r1);
gen_offset_st_2regs(cpu_gpr_a[r1+1], cpu_gpr_a[r1], cpu_gpr_a[r2],
off10, ctx);
break;
case OPC2_32_BO_ST_DA_POSTINC:
+ CHECK_REG_PAIR(r1);
gen_st_2regs_64(cpu_gpr_a[r1+1], cpu_gpr_a[r1], cpu_gpr_a[r2], ctx);
tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
break;
case OPC2_32_BO_ST_DA_PREINC:
+ CHECK_REG_PAIR(r1);
temp = tcg_temp_new();
tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10);
gen_st_2regs_64(cpu_gpr_a[r1+1], cpu_gpr_a[r1], temp, ctx);
case OPC2_32_BO_ST_W_PREINC:
gen_st_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUL);
break;
+ default:
+ generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
}
temp = tcg_temp_new();
temp2 = tcg_temp_new();
temp3 = tcg_const_i32(off10);
-
+ CHECK_REG_PAIR(r2);
tcg_gen_ext16u_tl(temp, cpu_gpr_a[r2+1]);
tcg_gen_add_tl(temp2, cpu_gpr_a[r2], temp);
gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
break;
case OPC2_32_BO_ST_D_BR:
+ CHECK_REG_PAIR(r1);
gen_st_2regs_64(cpu_gpr_d[r1+1], cpu_gpr_d[r1], temp2, ctx);
gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
break;
case OPC2_32_BO_ST_D_CIRC:
+ CHECK_REG_PAIR(r1);
tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUL);
tcg_gen_shri_tl(temp2, cpu_gpr_a[r2+1], 16);
tcg_gen_addi_tl(temp, temp, 4);
gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
break;
case OPC2_32_BO_ST_DA_BR:
+ CHECK_REG_PAIR(r1);
gen_st_2regs_64(cpu_gpr_a[r1+1], cpu_gpr_a[r1], temp2, ctx);
gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
break;
case OPC2_32_BO_ST_DA_CIRC:
+ CHECK_REG_PAIR(r1);
tcg_gen_qemu_st_tl(cpu_gpr_a[r1], temp2, ctx->mem_idx, MO_LEUL);
tcg_gen_shri_tl(temp2, cpu_gpr_a[r2+1], 16);
tcg_gen_addi_tl(temp, temp, 4);
tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUL);
gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
break;
+ default:
+ generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
tcg_temp_free(temp);
tcg_temp_free(temp2);
gen_ld_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_SB);
break;
case OPC2_32_BO_LD_D_SHORTOFF:
+ CHECK_REG_PAIR(r1);
gen_offset_ld_2regs(cpu_gpr_d[r1+1], cpu_gpr_d[r1], cpu_gpr_a[r2],
off10, ctx);
break;
case OPC2_32_BO_LD_D_POSTINC:
+ CHECK_REG_PAIR(r1);
gen_ld_2regs_64(cpu_gpr_d[r1+1], cpu_gpr_d[r1], cpu_gpr_a[r2], ctx);
tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
break;
case OPC2_32_BO_LD_D_PREINC:
+ CHECK_REG_PAIR(r1);
temp = tcg_temp_new();
tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10);
gen_ld_2regs_64(cpu_gpr_d[r1+1], cpu_gpr_d[r1], temp, ctx);
tcg_temp_free(temp);
break;
case OPC2_32_BO_LD_DA_SHORTOFF:
+ CHECK_REG_PAIR(r1);
gen_offset_ld_2regs(cpu_gpr_a[r1+1], cpu_gpr_a[r1], cpu_gpr_a[r2],
off10, ctx);
break;
case OPC2_32_BO_LD_DA_POSTINC:
+ CHECK_REG_PAIR(r1);
gen_ld_2regs_64(cpu_gpr_a[r1+1], cpu_gpr_a[r1], cpu_gpr_a[r2], ctx);
tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
break;
case OPC2_32_BO_LD_DA_PREINC:
+ CHECK_REG_PAIR(r1);
temp = tcg_temp_new();
tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10);
gen_ld_2regs_64(cpu_gpr_a[r1+1], cpu_gpr_a[r1], temp, ctx);
case OPC2_32_BO_LD_W_PREINC:
gen_ld_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUL);
break;
+ default:
+ generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
}
temp = tcg_temp_new();
temp2 = tcg_temp_new();
temp3 = tcg_const_i32(off10);
-
+ CHECK_REG_PAIR(r2);
tcg_gen_ext16u_tl(temp, cpu_gpr_a[r2+1]);
tcg_gen_add_tl(temp2, cpu_gpr_a[r2], temp);
gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
break;
case OPC2_32_BO_LD_D_BR:
+ CHECK_REG_PAIR(r1);
gen_ld_2regs_64(cpu_gpr_d[r1+1], cpu_gpr_d[r1], temp2, ctx);
gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
break;
case OPC2_32_BO_LD_D_CIRC:
+ CHECK_REG_PAIR(r1);
tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUL);
tcg_gen_shri_tl(temp2, cpu_gpr_a[r2+1], 16);
tcg_gen_addi_tl(temp, temp, 4);
gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
break;
case OPC2_32_BO_LD_DA_BR:
+ CHECK_REG_PAIR(r1);
gen_ld_2regs_64(cpu_gpr_a[r1+1], cpu_gpr_a[r1], temp2, ctx);
gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
break;
case OPC2_32_BO_LD_DA_CIRC:
+ CHECK_REG_PAIR(r1);
tcg_gen_qemu_ld_tl(cpu_gpr_a[r1], temp2, ctx->mem_idx, MO_LEUL);
tcg_gen_shri_tl(temp2, cpu_gpr_a[r2+1], 16);
tcg_gen_addi_tl(temp, temp, 4);
tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUL);
gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
break;
+ default:
+ generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
tcg_temp_free(temp);
tcg_temp_free(temp2);
tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
gen_swapmsk(ctx, r1, cpu_gpr_a[r2]);
break;
+ default:
+ generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
tcg_temp_free(temp);
tcg_temp_free(temp2);
temp = tcg_temp_new();
temp2 = tcg_temp_new();
temp3 = tcg_const_i32(off10);
-
+ CHECK_REG_PAIR(r2);
tcg_gen_ext16u_tl(temp, cpu_gpr_a[r2+1]);
tcg_gen_add_tl(temp2, cpu_gpr_a[r2], temp);
gen_swapmsk(ctx, r1, temp2);
gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
break;
+ default:
+ generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
tcg_temp_free(temp);
if (tricore_feature(env, TRICORE_FEATURE_16)) {
gen_offset_st(ctx, cpu_gpr_a[r1], cpu_gpr_a[r2], address, MO_LEUL);
} else {
- /* raise illegal opcode trap */
+ generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
break;
case OPC1_32_BOL_ST_W_LONGOFF:
if (tricore_feature(env, TRICORE_FEATURE_16)) {
gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], address, MO_SB);
} else {
- /* raise illegal opcode trap */
+ generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
break;
case OPC1_32_BOL_LD_BU_LONGOFF:
if (tricore_feature(env, TRICORE_FEATURE_16)) {
gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], address, MO_UB);
} else {
- /* raise illegal opcode trap */
+ generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
break;
case OPC1_32_BOL_LD_H_LONGOFF:
if (tricore_feature(env, TRICORE_FEATURE_16)) {
gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], address, MO_LESW);
} else {
- /* raise illegal opcode trap */
+ generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
break;
case OPC1_32_BOL_LD_HU_LONGOFF:
if (tricore_feature(env, TRICORE_FEATURE_16)) {
gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], address, MO_LEUW);
} else {
- /* raise illegal opcode trap */
+ generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
break;
case OPC1_32_BOL_ST_B_LONGOFF:
if (tricore_feature(env, TRICORE_FEATURE_16)) {
gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], address, MO_SB);
} else {
- /* raise illegal opcode trap */
+ generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
break;
case OPC1_32_BOL_ST_H_LONGOFF:
if (tricore_feature(env, TRICORE_FEATURE_16)) {
gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], address, MO_LESW);
} else {
- /* raise illegal opcode trap */
+ generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
break;
+ default:
+ generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
}
case OPC2_32_RC_XOR:
tcg_gen_xori_tl(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
break;
+ default:
+ generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
tcg_temp_free(temp);
}
gen_accumulating_condi(TCG_COND_NE, cpu_gpr_d[r2], cpu_gpr_d[r1],
const9, &tcg_gen_xor_tl);
break;
+ default:
+ generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
tcg_temp_free(temp);
}
case OPC2_32_RC_SYSCALL:
/* TODO: Add exception generation */
break;
+ default:
+ generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
}
gen_muli_i32s(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
break;
case OPC2_32_RC_MUL_64:
+ CHECK_REG_PAIR(r2);
gen_muli_i64s(cpu_gpr_d[r2], cpu_gpr_d[r2+1], cpu_gpr_d[r1], const9);
break;
case OPC2_32_RC_MULS_32:
break;
case OPC2_32_RC_MUL_U_64:
const9 = MASK_OP_RC_CONST9(ctx->opcode);
+ CHECK_REG_PAIR(r2);
gen_muli_i64u(cpu_gpr_d[r2], cpu_gpr_d[r2+1], cpu_gpr_d[r1], const9);
break;
case OPC2_32_RC_MULS_U_32:
const9 = MASK_OP_RC_CONST9(ctx->opcode);
gen_mulsui_i32(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
break;
+ default:
+ generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
}
switch (op2) {
case OPC2_32_RCPW_IMASK:
+ CHECK_REG_PAIR(r2);
/* if pos + width > 31 undefined result */
if (pos + width <= 31) {
tcg_gen_movi_tl(cpu_gpr_d[r2+1], ((1u << width) - 1) << pos);
tcg_temp_free(temp);
}
break;
+ default:
+ generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
}
tcg_temp_free(temp3);
break;
+ default:
+ generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
tcg_temp_free(temp);
tcg_temp_free(temp2);
tcg_temp_free(temp);
tcg_temp_free(temp2);
break;
+ default:
+ generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
}
gen_maddi32_d(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r3], const9);
break;
case OPC2_32_RCR_MADD_64:
+ CHECK_REG_PAIR(r4);
+ CHECK_REG_PAIR(r3);
gen_maddi64_d(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1],
cpu_gpr_d[r3], cpu_gpr_d[r3+1], const9);
break;
gen_maddsi_32(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r3], const9);
break;
case OPC2_32_RCR_MADDS_64:
+ CHECK_REG_PAIR(r4);
+ CHECK_REG_PAIR(r3);
gen_maddsi_64(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1],
cpu_gpr_d[r3], cpu_gpr_d[r3+1], const9);
break;
case OPC2_32_RCR_MADD_U_64:
+ CHECK_REG_PAIR(r4);
+ CHECK_REG_PAIR(r3);
const9 = MASK_OP_RCR_CONST9(ctx->opcode);
gen_maddui64_d(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1],
cpu_gpr_d[r3], cpu_gpr_d[r3+1], const9);
gen_maddsui_32(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r3], const9);
break;
case OPC2_32_RCR_MADDS_U_64:
+ CHECK_REG_PAIR(r4);
+ CHECK_REG_PAIR(r3);
const9 = MASK_OP_RCR_CONST9(ctx->opcode);
gen_maddsui_64(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1],
cpu_gpr_d[r3], cpu_gpr_d[r3+1], const9);
break;
+ default:
+ generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
}
gen_msubi32_d(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r3], const9);
break;
case OPC2_32_RCR_MSUB_64:
+ CHECK_REG_PAIR(r4);
+ CHECK_REG_PAIR(r3);
gen_msubi64_d(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1],
cpu_gpr_d[r3], cpu_gpr_d[r3+1], const9);
break;
gen_msubsi_32(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r3], const9);
break;
case OPC2_32_RCR_MSUBS_64:
+ CHECK_REG_PAIR(r4);
+ CHECK_REG_PAIR(r3);
gen_msubsi_64(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1],
cpu_gpr_d[r3], cpu_gpr_d[r3+1], const9);
break;
case OPC2_32_RCR_MSUB_U_64:
+ CHECK_REG_PAIR(r4);
+ CHECK_REG_PAIR(r3);
const9 = MASK_OP_RCR_CONST9(ctx->opcode);
gen_msubui64_d(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1],
cpu_gpr_d[r3], cpu_gpr_d[r3+1], const9);
gen_msubsui_32(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r3], const9);
break;
case OPC2_32_RCR_MSUBS_U_64:
+ CHECK_REG_PAIR(r4);
+ CHECK_REG_PAIR(r3);
const9 = MASK_OP_RCR_CONST9(ctx->opcode);
gen_msubsui_64(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1],
cpu_gpr_d[r3], cpu_gpr_d[r3+1], const9);
break;
+ default:
+ generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
}
break;
case OPC1_32_RLC_MOV_64:
if (tricore_feature(env, TRICORE_FEATURE_16)) {
- if ((r2 & 0x1) != 0) {
- /* TODO: raise OPD trap */
- }
+ CHECK_REG_PAIR(r2);
tcg_gen_movi_tl(cpu_gpr_d[r2], const16);
tcg_gen_movi_tl(cpu_gpr_d[r2+1], const16 >> 15);
} else {
- /* TODO: raise illegal opcode trap */
+ generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
break;
case OPC1_32_RLC_MOV_U:
const16 = MASK_OP_RLC_CONST16(ctx->opcode);
gen_mtcr(env, ctx, cpu_gpr_d[r1], const16);
break;
+ default:
+ generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
}
gen_accumulating_cond(TCG_COND_NE, cpu_gpr_d[r3], cpu_gpr_d[r1],
cpu_gpr_d[r2], &tcg_gen_xor_tl);
break;
+ default:
+ generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
}
case OPC2_32_RR_XOR:
tcg_gen_xor_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
break;
+ default:
+ generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
tcg_temp_free(temp);
}
case OPC2_32_RR_SUB_A:
tcg_gen_sub_tl(cpu_gpr_a[r3], cpu_gpr_a[r1], cpu_gpr_a[r2]);
break;
+ default:
+ generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
}
gen_fcall_save_ctx(ctx);
tcg_gen_andi_tl(cpu_PC, cpu_gpr_a[r1], ~0x1);
break;
+ default:
+ generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
tcg_gen_exit_tb(0);
ctx->bstate = BS_BRANCH;
gen_helper_bmerge(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
break;
case OPC2_32_RR_BSPLIT:
+ CHECK_REG_PAIR(r3);
gen_bsplit(cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1]);
break;
case OPC2_32_RR_DVINIT_B:
+ CHECK_REG_PAIR(r3);
gen_dvinit_b(env, cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1],
cpu_gpr_d[r2]);
break;
temp = tcg_temp_new();
temp2 = tcg_temp_new();
temp3 = tcg_temp_new();
-
+ CHECK_REG_PAIR(r3);
tcg_gen_shri_tl(temp3, cpu_gpr_d[r1], 8);
/* reset av */
tcg_gen_movi_tl(cpu_PSW_AV, 0);
tcg_temp_free(temp3);
break;
case OPC2_32_RR_DVINIT_H:
+ CHECK_REG_PAIR(r3);
gen_dvinit_h(env, cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1],
cpu_gpr_d[r2]);
break;
temp = tcg_temp_new();
temp2 = tcg_temp_new();
temp3 = tcg_temp_new();
-
+ CHECK_REG_PAIR(r3);
tcg_gen_shri_tl(temp3, cpu_gpr_d[r1], 16);
/* reset av */
tcg_gen_movi_tl(cpu_PSW_AV, 0);
case OPC2_32_RR_DVINIT:
temp = tcg_temp_new();
temp2 = tcg_temp_new();
+ CHECK_REG_PAIR(r3);
/* overflow = ((D[b] == 0) ||
((D[b] == 0xFFFFFFFF) && (D[a] == 0x80000000))) */
tcg_gen_setcondi_tl(TCG_COND_EQ, temp, cpu_gpr_d[r2], 0xffffffff);
gen_helper_parity(cpu_gpr_d[r3], cpu_gpr_d[r1]);
break;
case OPC2_32_RR_UNPACK:
+ CHECK_REG_PAIR(r3);
gen_unpack(cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1]);
break;
case OPC2_32_RR_CRC32:
if (tricore_feature(env, TRICORE_FEATURE_161)) {
gen_helper_crc32(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
- } /* TODO: else raise illegal opcode trap */
+ } else {
+ generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
+ }
break;
case OPC2_32_RR_DIV:
if (tricore_feature(env, TRICORE_FEATURE_16)) {
GEN_HELPER_RR(divide, cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1],
cpu_gpr_d[r2]);
- } /* TODO: else raise illegal opcode trap */
+ } else {
+ generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
+ }
break;
case OPC2_32_RR_DIV_U:
if (tricore_feature(env, TRICORE_FEATURE_16)) {
GEN_HELPER_RR(divide_u, cpu_gpr_d[r3], cpu_gpr_d[r3+1],
cpu_gpr_d[r1], cpu_gpr_d[r2]);
- } /* TODO: else raise illegal opcode trap */
+ } else {
+ generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
+ }
+ break;
+ case OPC2_32_RR_MUL_F:
+ gen_helper_fmul(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], cpu_gpr_d[r2]);
break;
+ case OPC2_32_RR_DIV_F:
+ gen_helper_fdiv(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], cpu_gpr_d[r2]);
+ break;
+ case OPC2_32_RR_CMP_F:
+ gen_helper_fcmp(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], cpu_gpr_d[r2]);
+ break;
+ case OPC2_32_RR_FTOI:
+ gen_helper_ftoi(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1]);
+ break;
+ case OPC2_32_RR_ITOF:
+ gen_helper_itof(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1]);
+ break;
+ default:
+ generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
}
switch (op2) {
case OPC2_32_RR1_MUL_H_32_LL:
temp64 = tcg_temp_new_i64();
+ CHECK_REG_PAIR(r3);
GEN_HELPER_LL(mul_h, temp64, cpu_gpr_d[r1], cpu_gpr_d[r2], n);
tcg_gen_extr_i64_i32(cpu_gpr_d[r3], cpu_gpr_d[r3+1], temp64);
gen_calc_usb_mul_h(cpu_gpr_d[r3], cpu_gpr_d[r3+1]);
break;
case OPC2_32_RR1_MUL_H_32_LU:
temp64 = tcg_temp_new_i64();
+ CHECK_REG_PAIR(r3);
GEN_HELPER_LU(mul_h, temp64, cpu_gpr_d[r1], cpu_gpr_d[r2], n);
tcg_gen_extr_i64_i32(cpu_gpr_d[r3], cpu_gpr_d[r3+1], temp64);
gen_calc_usb_mul_h(cpu_gpr_d[r3], cpu_gpr_d[r3+1]);
break;
case OPC2_32_RR1_MUL_H_32_UL:
temp64 = tcg_temp_new_i64();
+ CHECK_REG_PAIR(r3);
GEN_HELPER_UL(mul_h, temp64, cpu_gpr_d[r1], cpu_gpr_d[r2], n);
tcg_gen_extr_i64_i32(cpu_gpr_d[r3], cpu_gpr_d[r3+1], temp64);
gen_calc_usb_mul_h(cpu_gpr_d[r3], cpu_gpr_d[r3+1]);
break;
case OPC2_32_RR1_MUL_H_32_UU:
temp64 = tcg_temp_new_i64();
+ CHECK_REG_PAIR(r3);
GEN_HELPER_UU(mul_h, temp64, cpu_gpr_d[r1], cpu_gpr_d[r2], n);
tcg_gen_extr_i64_i32(cpu_gpr_d[r3], cpu_gpr_d[r3+1], temp64);
gen_calc_usb_mul_h(cpu_gpr_d[r3], cpu_gpr_d[r3+1]);
break;
case OPC2_32_RR1_MULM_H_64_LL:
temp64 = tcg_temp_new_i64();
+ CHECK_REG_PAIR(r3);
GEN_HELPER_LL(mulm_h, temp64, cpu_gpr_d[r1], cpu_gpr_d[r2], n);
tcg_gen_extr_i64_i32(cpu_gpr_d[r3], cpu_gpr_d[r3+1], temp64);
/* reset V bit */
break;
case OPC2_32_RR1_MULM_H_64_LU:
temp64 = tcg_temp_new_i64();
+ CHECK_REG_PAIR(r3);
GEN_HELPER_LU(mulm_h, temp64, cpu_gpr_d[r1], cpu_gpr_d[r2], n);
tcg_gen_extr_i64_i32(cpu_gpr_d[r3], cpu_gpr_d[r3+1], temp64);
/* reset V bit */
break;
case OPC2_32_RR1_MULM_H_64_UL:
temp64 = tcg_temp_new_i64();
+ CHECK_REG_PAIR(r3);
GEN_HELPER_UL(mulm_h, temp64, cpu_gpr_d[r1], cpu_gpr_d[r2], n);
tcg_gen_extr_i64_i32(cpu_gpr_d[r3], cpu_gpr_d[r3+1], temp64);
/* reset V bit */
break;
case OPC2_32_RR1_MULM_H_64_UU:
temp64 = tcg_temp_new_i64();
+ CHECK_REG_PAIR(r3);
GEN_HELPER_UU(mulm_h, temp64, cpu_gpr_d[r1], cpu_gpr_d[r2], n);
tcg_gen_extr_i64_i32(cpu_gpr_d[r3], cpu_gpr_d[r3+1], temp64);
/* reset V bit */
GEN_HELPER_UU(mulr_h, cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], n);
gen_calc_usb_mulr_h(cpu_gpr_d[r3]);
break;
+ default:
+ generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
tcg_temp_free(n);
}
gen_mul_q(cpu_gpr_d[r3], temp, cpu_gpr_d[r1], cpu_gpr_d[r2], n, 32);
break;
case OPC2_32_RR1_MUL_Q_64:
+ CHECK_REG_PAIR(r3);
gen_mul_q(cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
n, 0);
break;
gen_mul_q(cpu_gpr_d[r3], temp, cpu_gpr_d[r1], temp, n, 16);
break;
case OPC2_32_RR1_MUL_Q_64_L:
+ CHECK_REG_PAIR(r3);
tcg_gen_ext16s_tl(temp, cpu_gpr_d[r2]);
gen_mul_q(cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1], temp, n, 0);
break;
gen_mul_q(cpu_gpr_d[r3], temp, cpu_gpr_d[r1], temp, n, 16);
break;
case OPC2_32_RR1_MUL_Q_64_U:
+ CHECK_REG_PAIR(r3);
tcg_gen_sari_tl(temp, cpu_gpr_d[r2], 16);
gen_mul_q(cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1], temp, n, 0);
break;
tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16);
gen_mulr_q(cpu_gpr_d[r3], temp, temp2, n);
break;
+ default:
+ generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
tcg_temp_free(temp);
tcg_temp_free(temp2);
gen_mul_i32s(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
break;
case OPC2_32_RR2_MUL_64:
+ CHECK_REG_PAIR(r3);
gen_mul_i64s(cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1],
cpu_gpr_d[r2]);
break;
cpu_gpr_d[r2]);
break;
case OPC2_32_RR2_MUL_U_64:
+ CHECK_REG_PAIR(r3);
gen_mul_i64u(cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1],
cpu_gpr_d[r2]);
break;
gen_helper_mul_suov(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1],
cpu_gpr_d[r2]);
break;
+ default:
+ generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
}
}
break;
case OPC2_32_RRPW_IMASK:
+ CHECK_REG_PAIR(r3);
if (pos + width <= 31) {
tcg_gen_movi_tl(cpu_gpr_d[r3+1], ((1u << width) - 1) << pos);
tcg_gen_shli_tl(cpu_gpr_d[r3], cpu_gpr_d[r2], pos);
width, pos);
}
break;
+ default:
+ generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
}
cpu_gpr_d[r1], cpu_gpr_d[r2]);
tcg_temp_free(temp);
break;
+ default:
+ generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
}
switch (op2) {
case OPC2_32_RRR_DVADJ:
+ CHECK_REG_PAIR(r3);
+ CHECK_REG_PAIR(r4);
GEN_HELPER_RRR(dvadj, cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
cpu_gpr_d[r3+1], cpu_gpr_d[r2]);
break;
case OPC2_32_RRR_DVSTEP:
+ CHECK_REG_PAIR(r3);
+ CHECK_REG_PAIR(r4);
GEN_HELPER_RRR(dvstep, cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
cpu_gpr_d[r3+1], cpu_gpr_d[r2]);
break;
case OPC2_32_RRR_DVSTEP_U:
+ CHECK_REG_PAIR(r3);
+ CHECK_REG_PAIR(r4);
GEN_HELPER_RRR(dvstep_u, cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
cpu_gpr_d[r3+1], cpu_gpr_d[r2]);
break;
case OPC2_32_RRR_IXMAX:
+ CHECK_REG_PAIR(r3);
+ CHECK_REG_PAIR(r4);
GEN_HELPER_RRR(ixmax, cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
cpu_gpr_d[r3+1], cpu_gpr_d[r2]);
break;
case OPC2_32_RRR_IXMAX_U:
+ CHECK_REG_PAIR(r3);
+ CHECK_REG_PAIR(r4);
GEN_HELPER_RRR(ixmax_u, cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
cpu_gpr_d[r3+1], cpu_gpr_d[r2]);
break;
case OPC2_32_RRR_IXMIN:
+ CHECK_REG_PAIR(r3);
+ CHECK_REG_PAIR(r4);
GEN_HELPER_RRR(ixmin, cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
cpu_gpr_d[r3+1], cpu_gpr_d[r2]);
break;
case OPC2_32_RRR_IXMIN_U:
+ CHECK_REG_PAIR(r3);
+ CHECK_REG_PAIR(r4);
GEN_HELPER_RRR(ixmin_u, cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
cpu_gpr_d[r3+1], cpu_gpr_d[r2]);
break;
case OPC2_32_RRR_PACK:
+ CHECK_REG_PAIR(r3);
gen_helper_pack(cpu_gpr_d[r4], cpu_PSW_C, cpu_gpr_d[r3],
cpu_gpr_d[r3+1], cpu_gpr_d[r1]);
break;
+ case OPC2_32_RRR_ADD_F:
+ gen_helper_fadd(cpu_gpr_d[r4], cpu_env, cpu_gpr_d[r1], cpu_gpr_d[r3]);
+ break;
+ case OPC2_32_RRR_SUB_F:
+ gen_helper_fsub(cpu_gpr_d[r4], cpu_env, cpu_gpr_d[r1], cpu_gpr_d[r3]);
+ break;
+ default:
+ generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
}
cpu_gpr_d[r2]);
break;
case OPC2_32_RRR2_MADD_64:
+ CHECK_REG_PAIR(r4);
+ CHECK_REG_PAIR(r3);
gen_madd64_d(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1],
cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r2]);
break;
cpu_gpr_d[r3], cpu_gpr_d[r2]);
break;
case OPC2_32_RRR2_MADDS_64:
+ CHECK_REG_PAIR(r4);
+ CHECK_REG_PAIR(r3);
gen_madds_64(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1],
cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r2]);
break;
case OPC2_32_RRR2_MADD_U_64:
+ CHECK_REG_PAIR(r4);
+ CHECK_REG_PAIR(r3);
gen_maddu64_d(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1],
cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r2]);
break;
cpu_gpr_d[r3], cpu_gpr_d[r2]);
break;
case OPC2_32_RRR2_MADDS_U_64:
+ CHECK_REG_PAIR(r4);
+ CHECK_REG_PAIR(r3);
gen_maddsu_64(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1],
cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r2]);
break;
+ default:
+ generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
}
cpu_gpr_d[r2]);
break;
case OPC2_32_RRR2_MSUB_64:
+ CHECK_REG_PAIR(r4);
+ CHECK_REG_PAIR(r3);
gen_msub64_d(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1],
cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r2]);
break;
cpu_gpr_d[r3], cpu_gpr_d[r2]);
break;
case OPC2_32_RRR2_MSUBS_64:
+ CHECK_REG_PAIR(r4);
+ CHECK_REG_PAIR(r3);
gen_msubs_64(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1],
cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r2]);
break;
cpu_gpr_d[r3], cpu_gpr_d[r2]);
break;
case OPC2_32_RRR2_MSUBS_U_64:
+ CHECK_REG_PAIR(r4);
+ CHECK_REG_PAIR(r3);
gen_msubsu_64(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1],
cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r2]);
break;
+ default:
+ generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
}
switch (op2) {
case OPC2_32_RRR1_MADD_H_LL:
+ CHECK_REG_PAIR(r4);
+ CHECK_REG_PAIR(r3);
gen_madd_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LL);
break;
case OPC2_32_RRR1_MADD_H_LU:
+ CHECK_REG_PAIR(r4);
+ CHECK_REG_PAIR(r3);
gen_madd_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LU);
break;
case OPC2_32_RRR1_MADD_H_UL:
+ CHECK_REG_PAIR(r4);
+ CHECK_REG_PAIR(r3);
gen_madd_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UL);
break;
case OPC2_32_RRR1_MADD_H_UU:
+ CHECK_REG_PAIR(r4);
+ CHECK_REG_PAIR(r3);
gen_madd_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UU);
break;
case OPC2_32_RRR1_MADDS_H_LL:
+ CHECK_REG_PAIR(r4);
+ CHECK_REG_PAIR(r3);
gen_madds_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LL);
break;
case OPC2_32_RRR1_MADDS_H_LU:
+ CHECK_REG_PAIR(r4);
+ CHECK_REG_PAIR(r3);
gen_madds_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LU);
break;
case OPC2_32_RRR1_MADDS_H_UL:
+ CHECK_REG_PAIR(r4);
+ CHECK_REG_PAIR(r3);
gen_madds_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UL);
break;
case OPC2_32_RRR1_MADDS_H_UU:
+ CHECK_REG_PAIR(r4);
+ CHECK_REG_PAIR(r3);
gen_madds_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UU);
break;
case OPC2_32_RRR1_MADDM_H_LL:
+ CHECK_REG_PAIR(r4);
+ CHECK_REG_PAIR(r3);
gen_maddm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LL);
break;
case OPC2_32_RRR1_MADDM_H_LU:
+ CHECK_REG_PAIR(r4);
+ CHECK_REG_PAIR(r3);
gen_maddm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LU);
break;
case OPC2_32_RRR1_MADDM_H_UL:
+ CHECK_REG_PAIR(r4);
+ CHECK_REG_PAIR(r3);
gen_maddm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UL);
break;
case OPC2_32_RRR1_MADDM_H_UU:
+ CHECK_REG_PAIR(r4);
+ CHECK_REG_PAIR(r3);
gen_maddm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UU);
break;
case OPC2_32_RRR1_MADDMS_H_LL:
+ CHECK_REG_PAIR(r4);
+ CHECK_REG_PAIR(r3);
gen_maddms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LL);
break;
case OPC2_32_RRR1_MADDMS_H_LU:
+ CHECK_REG_PAIR(r4);
+ CHECK_REG_PAIR(r3);
gen_maddms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LU);
break;
case OPC2_32_RRR1_MADDMS_H_UL:
+ CHECK_REG_PAIR(r4);
+ CHECK_REG_PAIR(r3);
gen_maddms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UL);
break;
case OPC2_32_RRR1_MADDMS_H_UU:
+ CHECK_REG_PAIR(r4);
+ CHECK_REG_PAIR(r3);
gen_maddms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UU);
break;
gen_maddr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
cpu_gpr_d[r2], n, MODE_UU);
break;
+ default:
+ generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
}
cpu_gpr_d[r2], n, 32, env);
break;
case OPC2_32_RRR1_MADD_Q_64:
+ CHECK_REG_PAIR(r4);
+ CHECK_REG_PAIR(r3);
gen_madd64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
n, env);
temp, n, 16, env);
break;
case OPC2_32_RRR1_MADD_Q_64_L:
+ CHECK_REG_PAIR(r4);
+ CHECK_REG_PAIR(r3);
tcg_gen_ext16s_tl(temp, cpu_gpr_d[r2]);
gen_madd64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
cpu_gpr_d[r3+1], cpu_gpr_d[r1], temp,
temp, n, 16, env);
break;
case OPC2_32_RRR1_MADD_Q_64_U:
+ CHECK_REG_PAIR(r4);
+ CHECK_REG_PAIR(r3);
tcg_gen_sari_tl(temp, cpu_gpr_d[r2], 16);
gen_madd64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
cpu_gpr_d[r3+1], cpu_gpr_d[r1], temp,
gen_m16add32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n);
break;
case OPC2_32_RRR1_MADD_Q_64_LL:
+ CHECK_REG_PAIR(r4);
+ CHECK_REG_PAIR(r3);
tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]);
tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]);
gen_m16add64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
gen_m16add32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n);
break;
case OPC2_32_RRR1_MADD_Q_64_UU:
+ CHECK_REG_PAIR(r4);
+ CHECK_REG_PAIR(r3);
tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16);
tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16);
gen_m16add64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
cpu_gpr_d[r2], n, 32);
break;
case OPC2_32_RRR1_MADDS_Q_64:
+ CHECK_REG_PAIR(r4);
+ CHECK_REG_PAIR(r3);
gen_madds64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
n);
temp, n, 16);
break;
case OPC2_32_RRR1_MADDS_Q_64_L:
+ CHECK_REG_PAIR(r4);
+ CHECK_REG_PAIR(r3);
tcg_gen_ext16s_tl(temp, cpu_gpr_d[r2]);
gen_madds64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
cpu_gpr_d[r3+1], cpu_gpr_d[r1], temp,
temp, n, 16);
break;
case OPC2_32_RRR1_MADDS_Q_64_U:
+ CHECK_REG_PAIR(r4);
+ CHECK_REG_PAIR(r3);
tcg_gen_sari_tl(temp, cpu_gpr_d[r2], 16);
gen_madds64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
cpu_gpr_d[r3+1], cpu_gpr_d[r1], temp,
gen_m16adds32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n);
break;
case OPC2_32_RRR1_MADDS_Q_64_LL:
+ CHECK_REG_PAIR(r4);
+ CHECK_REG_PAIR(r3);
tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]);
tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]);
gen_m16adds64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
gen_m16adds32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n);
break;
case OPC2_32_RRR1_MADDS_Q_64_UU:
+ CHECK_REG_PAIR(r4);
+ CHECK_REG_PAIR(r3);
tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16);
tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16);
gen_m16adds64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
cpu_gpr_d[r3+1], temp, temp2, n);
break;
case OPC2_32_RRR1_MADDR_H_64_UL:
+ CHECK_REG_PAIR(r3);
gen_maddr64_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r3+1],
cpu_gpr_d[r1], cpu_gpr_d[r2], n, 2);
break;
case OPC2_32_RRR1_MADDRS_H_64_UL:
+ CHECK_REG_PAIR(r3);
gen_maddr64s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r3+1],
cpu_gpr_d[r1], cpu_gpr_d[r2], n, 2);
break;
tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16);
gen_maddrs_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n);
break;
+ default:
+ generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
tcg_temp_free(temp);
tcg_temp_free(temp2);
switch (op2) {
case OPC2_32_RRR1_MADDSU_H_32_LL:
+ CHECK_REG_PAIR(r4);
+ CHECK_REG_PAIR(r3);
gen_maddsu_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LL);
break;
case OPC2_32_RRR1_MADDSU_H_32_LU:
+ CHECK_REG_PAIR(r4);
+ CHECK_REG_PAIR(r3);
gen_maddsu_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LU);
break;
case OPC2_32_RRR1_MADDSU_H_32_UL:
+ CHECK_REG_PAIR(r4);
+ CHECK_REG_PAIR(r3);
gen_maddsu_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UL);
break;
case OPC2_32_RRR1_MADDSU_H_32_UU:
+ CHECK_REG_PAIR(r4);
+ CHECK_REG_PAIR(r3);
gen_maddsu_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UU);
break;
case OPC2_32_RRR1_MADDSUS_H_32_LL:
+ CHECK_REG_PAIR(r4);
+ CHECK_REG_PAIR(r3);
gen_maddsus_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
n, MODE_LL);
break;
case OPC2_32_RRR1_MADDSUS_H_32_LU:
+ CHECK_REG_PAIR(r4);
+ CHECK_REG_PAIR(r3);
gen_maddsus_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
n, MODE_LU);
break;
case OPC2_32_RRR1_MADDSUS_H_32_UL:
+ CHECK_REG_PAIR(r4);
+ CHECK_REG_PAIR(r3);
gen_maddsus_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
n, MODE_UL);
break;
case OPC2_32_RRR1_MADDSUS_H_32_UU:
+ CHECK_REG_PAIR(r4);
+ CHECK_REG_PAIR(r3);
gen_maddsus_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
n, MODE_UU);
break;
case OPC2_32_RRR1_MADDSUM_H_64_LL:
+ CHECK_REG_PAIR(r4);
+ CHECK_REG_PAIR(r3);
gen_maddsum_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
n, MODE_LL);
break;
case OPC2_32_RRR1_MADDSUM_H_64_LU:
+ CHECK_REG_PAIR(r4);
+ CHECK_REG_PAIR(r3);
gen_maddsum_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
n, MODE_LU);
break;
case OPC2_32_RRR1_MADDSUM_H_64_UL:
+ CHECK_REG_PAIR(r4);
+ CHECK_REG_PAIR(r3);
gen_maddsum_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
n, MODE_UL);
break;
case OPC2_32_RRR1_MADDSUM_H_64_UU:
+ CHECK_REG_PAIR(r4);
+ CHECK_REG_PAIR(r3);
gen_maddsum_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
n, MODE_UU);
break;
case OPC2_32_RRR1_MADDSUMS_H_64_LL:
+ CHECK_REG_PAIR(r4);
+ CHECK_REG_PAIR(r3);
gen_maddsums_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
n, MODE_LL);
break;
case OPC2_32_RRR1_MADDSUMS_H_64_LU:
+ CHECK_REG_PAIR(r4);
+ CHECK_REG_PAIR(r3);
gen_maddsums_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
n, MODE_LU);
break;
case OPC2_32_RRR1_MADDSUMS_H_64_UL:
+ CHECK_REG_PAIR(r4);
+ CHECK_REG_PAIR(r3);
gen_maddsums_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
n, MODE_UL);
break;
case OPC2_32_RRR1_MADDSUMS_H_64_UU:
+ CHECK_REG_PAIR(r4);
+ CHECK_REG_PAIR(r3);
gen_maddsums_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
n, MODE_UU);
gen_maddsur32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
cpu_gpr_d[r2], n, MODE_UU);
break;
+ default:
+ generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
}
switch (op2) {
case OPC2_32_RRR1_MSUB_H_LL:
+ CHECK_REG_PAIR(r4);
+ CHECK_REG_PAIR(r3);
gen_msub_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LL);
break;
case OPC2_32_RRR1_MSUB_H_LU:
+ CHECK_REG_PAIR(r4);
+ CHECK_REG_PAIR(r3);
gen_msub_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LU);
break;
case OPC2_32_RRR1_MSUB_H_UL:
+ CHECK_REG_PAIR(r4);
+ CHECK_REG_PAIR(r3);
gen_msub_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UL);
break;
case OPC2_32_RRR1_MSUB_H_UU:
+ CHECK_REG_PAIR(r4);
+ CHECK_REG_PAIR(r3);
gen_msub_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UU);
break;
case OPC2_32_RRR1_MSUBS_H_LL:
+ CHECK_REG_PAIR(r4);
+ CHECK_REG_PAIR(r3);
gen_msubs_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LL);
break;
case OPC2_32_RRR1_MSUBS_H_LU:
+ CHECK_REG_PAIR(r4);
+ CHECK_REG_PAIR(r3);
gen_msubs_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LU);
break;
case OPC2_32_RRR1_MSUBS_H_UL:
+ CHECK_REG_PAIR(r4);
+ CHECK_REG_PAIR(r3);
gen_msubs_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UL);
break;
case OPC2_32_RRR1_MSUBS_H_UU:
+ CHECK_REG_PAIR(r4);
+ CHECK_REG_PAIR(r3);
gen_msubs_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UU);
break;
case OPC2_32_RRR1_MSUBM_H_LL:
+ CHECK_REG_PAIR(r4);
+ CHECK_REG_PAIR(r3);
gen_msubm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LL);
break;
case OPC2_32_RRR1_MSUBM_H_LU:
+ CHECK_REG_PAIR(r4);
+ CHECK_REG_PAIR(r3);
gen_msubm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LU);
break;
case OPC2_32_RRR1_MSUBM_H_UL:
+ CHECK_REG_PAIR(r4);
+ CHECK_REG_PAIR(r3);
gen_msubm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UL);
break;
case OPC2_32_RRR1_MSUBM_H_UU:
+ CHECK_REG_PAIR(r4);
+ CHECK_REG_PAIR(r3);
gen_msubm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UU);
break;
case OPC2_32_RRR1_MSUBMS_H_LL:
+ CHECK_REG_PAIR(r4);
+ CHECK_REG_PAIR(r3);
gen_msubms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LL);
break;
case OPC2_32_RRR1_MSUBMS_H_LU:
+ CHECK_REG_PAIR(r4);
+ CHECK_REG_PAIR(r3);
gen_msubms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LU);
break;
case OPC2_32_RRR1_MSUBMS_H_UL:
+ CHECK_REG_PAIR(r4);
+ CHECK_REG_PAIR(r3);
gen_msubms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UL);
break;
case OPC2_32_RRR1_MSUBMS_H_UU:
+ CHECK_REG_PAIR(r4);
+ CHECK_REG_PAIR(r3);
gen_msubms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UU);
break;
gen_msubr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
cpu_gpr_d[r2], n, MODE_UU);
break;
+ default:
+ generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
}
cpu_gpr_d[r2], n, 32, env);
break;
case OPC2_32_RRR1_MSUB_Q_64:
+ CHECK_REG_PAIR(r4);
+ CHECK_REG_PAIR(r3);
gen_msub64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
n, env);
temp, n, 16, env);
break;
case OPC2_32_RRR1_MSUB_Q_64_L:
+ CHECK_REG_PAIR(r4);
+ CHECK_REG_PAIR(r3);
tcg_gen_ext16s_tl(temp, cpu_gpr_d[r2]);
gen_msub64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
cpu_gpr_d[r3+1], cpu_gpr_d[r1], temp,
temp, n, 16, env);
break;
case OPC2_32_RRR1_MSUB_Q_64_U:
+ CHECK_REG_PAIR(r4);
+ CHECK_REG_PAIR(r3);
tcg_gen_sari_tl(temp, cpu_gpr_d[r2], 16);
gen_msub64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
cpu_gpr_d[r3+1], cpu_gpr_d[r1], temp,
gen_m16sub32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n);
break;
case OPC2_32_RRR1_MSUB_Q_64_LL:
+ CHECK_REG_PAIR(r4);
+ CHECK_REG_PAIR(r3);
tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]);
tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]);
gen_m16sub64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
gen_m16sub32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n);
break;
case OPC2_32_RRR1_MSUB_Q_64_UU:
+ CHECK_REG_PAIR(r4);
+ CHECK_REG_PAIR(r3);
tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16);
tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16);
gen_m16sub64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
cpu_gpr_d[r2], n, 32);
break;
case OPC2_32_RRR1_MSUBS_Q_64:
+ CHECK_REG_PAIR(r4);
+ CHECK_REG_PAIR(r3);
gen_msubs64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
n);
temp, n, 16);
break;
case OPC2_32_RRR1_MSUBS_Q_64_L:
+ CHECK_REG_PAIR(r4);
+ CHECK_REG_PAIR(r3);
tcg_gen_ext16s_tl(temp, cpu_gpr_d[r2]);
gen_msubs64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
cpu_gpr_d[r3+1], cpu_gpr_d[r1], temp,
temp, n, 16);
break;
case OPC2_32_RRR1_MSUBS_Q_64_U:
+ CHECK_REG_PAIR(r4);
+ CHECK_REG_PAIR(r3);
tcg_gen_sari_tl(temp, cpu_gpr_d[r2], 16);
gen_msubs64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
cpu_gpr_d[r3+1], cpu_gpr_d[r1], temp,
gen_m16subs32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n);
break;
case OPC2_32_RRR1_MSUBS_Q_64_LL:
+ CHECK_REG_PAIR(r4);
+ CHECK_REG_PAIR(r3);
tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]);
tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]);
gen_m16subs64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
gen_m16subs32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n);
break;
case OPC2_32_RRR1_MSUBS_Q_64_UU:
+ CHECK_REG_PAIR(r4);
+ CHECK_REG_PAIR(r3);
tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16);
tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16);
gen_m16subs64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
cpu_gpr_d[r3+1], temp, temp2, n);
break;
case OPC2_32_RRR1_MSUBR_H_64_UL:
+ CHECK_REG_PAIR(r3);
gen_msubr64_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r3+1],
cpu_gpr_d[r1], cpu_gpr_d[r2], n, 2);
break;
case OPC2_32_RRR1_MSUBRS_H_64_UL:
+ CHECK_REG_PAIR(r3);
gen_msubr64s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r3+1],
cpu_gpr_d[r1], cpu_gpr_d[r2], n, 2);
break;
tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16);
gen_msubrs_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n);
break;
+ default:
+ generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
tcg_temp_free(temp);
tcg_temp_free(temp2);
switch (op2) {
case OPC2_32_RRR1_MSUBAD_H_32_LL:
+ CHECK_REG_PAIR(r4);
+ CHECK_REG_PAIR(r3);
gen_msubad_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LL);
break;
case OPC2_32_RRR1_MSUBAD_H_32_LU:
+ CHECK_REG_PAIR(r4);
+ CHECK_REG_PAIR(r3);
gen_msubad_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LU);
break;
case OPC2_32_RRR1_MSUBAD_H_32_UL:
+ CHECK_REG_PAIR(r4);
+ CHECK_REG_PAIR(r3);
gen_msubad_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UL);
break;
case OPC2_32_RRR1_MSUBAD_H_32_UU:
+ CHECK_REG_PAIR(r4);
+ CHECK_REG_PAIR(r3);
gen_msubad_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UU);
break;
case OPC2_32_RRR1_MSUBADS_H_32_LL:
+ CHECK_REG_PAIR(r4);
+ CHECK_REG_PAIR(r3);
gen_msubads_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
n, MODE_LL);
break;
case OPC2_32_RRR1_MSUBADS_H_32_LU:
+ CHECK_REG_PAIR(r4);
+ CHECK_REG_PAIR(r3);
gen_msubads_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
n, MODE_LU);
break;
case OPC2_32_RRR1_MSUBADS_H_32_UL:
+ CHECK_REG_PAIR(r4);
+ CHECK_REG_PAIR(r3);
gen_msubads_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
n, MODE_UL);
break;
case OPC2_32_RRR1_MSUBADS_H_32_UU:
+ CHECK_REG_PAIR(r4);
+ CHECK_REG_PAIR(r3);
gen_msubads_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
n, MODE_UU);
break;
case OPC2_32_RRR1_MSUBADM_H_64_LL:
+ CHECK_REG_PAIR(r4);
+ CHECK_REG_PAIR(r3);
gen_msubadm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
n, MODE_LL);
break;
case OPC2_32_RRR1_MSUBADM_H_64_LU:
+ CHECK_REG_PAIR(r4);
+ CHECK_REG_PAIR(r3);
gen_msubadm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
n, MODE_LU);
break;
case OPC2_32_RRR1_MSUBADM_H_64_UL:
+ CHECK_REG_PAIR(r4);
+ CHECK_REG_PAIR(r3);
gen_msubadm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
n, MODE_UL);
break;
case OPC2_32_RRR1_MSUBADM_H_64_UU:
+ CHECK_REG_PAIR(r4);
+ CHECK_REG_PAIR(r3);
gen_msubadm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
n, MODE_UU);
break;
case OPC2_32_RRR1_MSUBADMS_H_64_LL:
+ CHECK_REG_PAIR(r4);
+ CHECK_REG_PAIR(r3);
gen_msubadms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
n, MODE_LL);
break;
case OPC2_32_RRR1_MSUBADMS_H_64_LU:
+ CHECK_REG_PAIR(r4);
+ CHECK_REG_PAIR(r3);
gen_msubadms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
n, MODE_LU);
break;
case OPC2_32_RRR1_MSUBADMS_H_64_UL:
+ CHECK_REG_PAIR(r4);
+ CHECK_REG_PAIR(r3);
gen_msubadms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
n, MODE_UL);
break;
case OPC2_32_RRR1_MSUBADMS_H_64_UU:
+ CHECK_REG_PAIR(r4);
+ CHECK_REG_PAIR(r3);
gen_msubadms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
n, MODE_UU);
gen_msubadr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
cpu_gpr_d[r2], n, MODE_UU);
break;
+ default:
+ generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
}
break;
case OPC2_32_RRRR_EXTR:
case OPC2_32_RRRR_EXTR_U:
+ CHECK_REG_PAIR(r3);
tcg_gen_andi_tl(tmp_width, cpu_gpr_d[r3+1], 0x1f);
tcg_gen_andi_tl(tmp_pos, cpu_gpr_d[r3], 0x1f);
tcg_gen_add_tl(tmp_pos, tmp_pos, tmp_width);
}
break;
case OPC2_32_RRRR_INSERT:
+ CHECK_REG_PAIR(r3);
tcg_gen_andi_tl(tmp_width, cpu_gpr_d[r3+1], 0x1f);
tcg_gen_andi_tl(tmp_pos, cpu_gpr_d[r3], 0x1f);
gen_insert(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r2], tmp_width,
tmp_pos);
break;
+ default:
+ generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
tcg_temp_free(tmp_pos);
tcg_temp_free(tmp_width);
tcg_temp_free(temp2);
break;
+ default:
+ generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
tcg_temp_free(temp);
}
(ctx->hflags & TRICORE_HFLAG_KUU) == TRICORE_HFLAG_UM1) {
tcg_gen_deposit_tl(cpu_ICR, cpu_ICR, cpu_gpr_d[r1], 8, 1);
} /* else raise privilege trap */
- } /* else raise illegal opcode trap */
+ } else {
+ generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
+ }
break;
case OPC2_32_SYS_TRAPSV:
- /* TODO: raise sticky overflow trap */
+ l1 = gen_new_label();
+ tcg_gen_brcondi_tl(TCG_COND_GE, cpu_PSW_SV, 0, l1);
+ generate_trap(ctx, TRAPC_ASSERT, TIN5_SOVF);
+ gen_set_label(l1);
break;
case OPC2_32_SYS_TRAPV:
- /* TODO: raise overflow trap */
+ l1 = gen_new_label();
+ tcg_gen_brcondi_tl(TCG_COND_GE, cpu_PSW_V, 0, l1);
+ generate_trap(ctx, TRAPC_ASSERT, TIN5_OVF);
+ gen_set_label(l1);
break;
+ default:
+ generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
}
temp2 = tcg_temp_new(); /* width*/
temp3 = tcg_temp_new(); /* pos */
+ CHECK_REG_PAIR(r3);
+
tcg_gen_andi_tl(temp2, cpu_gpr_d[r3+1], 0x1f);
tcg_gen_andi_tl(temp3, cpu_gpr_d[r3], 0x1f);
break;
case OPCM_32_RRR_DIVIDE:
decode_rrr_divide(env, ctx);
+ break;
/* RRR2 Format */
case OPCM_32_RRR2_MADD:
decode_rrr2_madd(env, ctx);
/* RRRR format */
case OPCM_32_RRRR_EXTRACT_INSERT:
decode_rrrr_extract_insert(env, ctx);
+ break;
/* RRRW format */
case OPCM_32_RRRW_EXTRACT_INSERT:
decode_rrrw_extract_insert(env, ctx);
tcg_gen_mov_tl(cpu_PSW_AV, cpu_PSW_V);
tcg_gen_mov_tl(cpu_PSW_SAV, cpu_PSW_V);
break;
+ default:
+ generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
}
}
}
-static inline void
-gen_intermediate_code_internal(TriCoreCPU *cpu, struct TranslationBlock *tb,
- int search_pc)
+void gen_intermediate_code(CPUTriCoreState *env, struct TranslationBlock *tb)
{
+ TriCoreCPU *cpu = tricore_env_get_cpu(env);
CPUState *cs = CPU(cpu);
- CPUTriCoreState *env = &cpu->env;
DisasContext ctx;
target_ulong pc_start;
- int num_insns;
+ int num_insns, max_insns;
- if (search_pc) {
- qemu_log("search pc %d\n", search_pc);
+ num_insns = 0;
+ max_insns = tb->cflags & CF_COUNT_MASK;
+ if (max_insns == 0) {
+ max_insns = CF_COUNT_MASK;
+ }
+ if (singlestep) {
+ max_insns = 1;
+ }
+ if (max_insns > TCG_MAX_INSNS) {
+ max_insns = TCG_MAX_INSNS;
}
- num_insns = 0;
pc_start = tb->pc;
ctx.pc = pc_start;
ctx.saved_pc = -1;
ctx.tb = tb;
ctx.singlestep_enabled = cs->singlestep_enabled;
ctx.bstate = BS_NONE;
- ctx.mem_idx = cpu_mmu_index(env);
+ ctx.mem_idx = cpu_mmu_index(env, false);
tcg_clear_temp_count();
gen_tb_start(tb);
while (ctx.bstate == BS_NONE) {
+ tcg_gen_insn_start(ctx.pc);
+ num_insns++;
+
ctx.opcode = cpu_ldl_code(env, ctx.pc);
decode_opc(env, &ctx, 0);
- num_insns++;
-
- if (tcg_op_buf_full()) {
- gen_save_pc(ctx.next_pc);
- tcg_gen_exit_tb(0);
- break;
- }
- if (singlestep) {
+ if (num_insns >= max_insns || tcg_op_buf_full()) {
gen_save_pc(ctx.next_pc);
tcg_gen_exit_tb(0);
break;
}
gen_tb_end(tb, num_insns);
- if (search_pc) {
- printf("done_generating search pc\n");
- } else {
- tb->size = ctx.pc - pc_start;
- tb->icount = num_insns;
- }
+ tb->size = ctx.pc - pc_start;
+ tb->icount = num_insns;
+
if (tcg_check_temp_count()) {
printf("LEAK at %08x\n", env->PC);
}
}
void
-gen_intermediate_code(CPUTriCoreState *env, struct TranslationBlock *tb)
-{
- gen_intermediate_code_internal(tricore_env_get_cpu(env), tb, false);
-}
-
-void
-gen_intermediate_code_pc(CPUTriCoreState *env, struct TranslationBlock *tb)
-{
- gen_intermediate_code_internal(tricore_env_get_cpu(env), tb, true);
-}
-
-void
-restore_state_to_opc(CPUTriCoreState *env, TranslationBlock *tb, int pc_pos)
+restore_state_to_opc(CPUTriCoreState *env, TranslationBlock *tb,
+ target_ulong *data)
{
- env->PC = tcg_ctx.gen_opc_pc[pc_pos];
+ env->PC = data[0];
}
/*
*
{
/* Reset Regs to Default Value */
env->PSW = 0xb80;
+ fpu_set_state(env);
}
static void tricore_tcg_init_csfr(void)
{
- cpu_PCXI = tcg_global_mem_new(TCG_AREG0,
+ cpu_PCXI = tcg_global_mem_new(cpu_env,
offsetof(CPUTriCoreState, PCXI), "PCXI");
- cpu_PSW = tcg_global_mem_new(TCG_AREG0,
+ cpu_PSW = tcg_global_mem_new(cpu_env,
offsetof(CPUTriCoreState, PSW), "PSW");
- cpu_PC = tcg_global_mem_new(TCG_AREG0,
+ cpu_PC = tcg_global_mem_new(cpu_env,
offsetof(CPUTriCoreState, PC), "PC");
- cpu_ICR = tcg_global_mem_new(TCG_AREG0,
+ cpu_ICR = tcg_global_mem_new(cpu_env,
offsetof(CPUTriCoreState, ICR), "ICR");
}
cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
/* reg init */
for (i = 0 ; i < 16 ; i++) {
- cpu_gpr_a[i] = tcg_global_mem_new(TCG_AREG0,
+ cpu_gpr_a[i] = tcg_global_mem_new(cpu_env,
offsetof(CPUTriCoreState, gpr_a[i]),
regnames_a[i]);
}
for (i = 0 ; i < 16 ; i++) {
- cpu_gpr_d[i] = tcg_global_mem_new(TCG_AREG0,
+ cpu_gpr_d[i] = tcg_global_mem_new(cpu_env,
offsetof(CPUTriCoreState, gpr_d[i]),
regnames_d[i]);
}
tricore_tcg_init_csfr();
/* init PSW flag cache */
- cpu_PSW_C = tcg_global_mem_new(TCG_AREG0,
+ cpu_PSW_C = tcg_global_mem_new(cpu_env,
offsetof(CPUTriCoreState, PSW_USB_C),
"PSW_C");
- cpu_PSW_V = tcg_global_mem_new(TCG_AREG0,
+ cpu_PSW_V = tcg_global_mem_new(cpu_env,
offsetof(CPUTriCoreState, PSW_USB_V),
"PSW_V");
- cpu_PSW_SV = tcg_global_mem_new(TCG_AREG0,
+ cpu_PSW_SV = tcg_global_mem_new(cpu_env,
offsetof(CPUTriCoreState, PSW_USB_SV),
"PSW_SV");
- cpu_PSW_AV = tcg_global_mem_new(TCG_AREG0,
+ cpu_PSW_AV = tcg_global_mem_new(cpu_env,
offsetof(CPUTriCoreState, PSW_USB_AV),
"PSW_AV");
- cpu_PSW_SAV = tcg_global_mem_new(TCG_AREG0,
+ cpu_PSW_SAV = tcg_global_mem_new(cpu_env,
offsetof(CPUTriCoreState, PSW_USB_SAV),
"PSW_SAV");
}
Code Review / kvmfornfv.git / blobdiff