Add qemu 2.4.0

[kvmfornfv.git] / qemu / roms / u-boot / drivers / usb / host / xhci-omap.c

diff --git a/qemu/roms/u-boot/drivers/usb/host/xhci-omap.c b/qemu/roms/u-boot/drivers/usb/host/xhci-omap.c
new file mode 100644 (file)
index 0000000..e667810
--- /dev/null
+++ b/qemu/roms/u-boot/drivers/usb/host/xhci-omap.c
@@ -0,0 +1,158 @@
+/*
+ * OMAP USB HOST xHCI Controller
+ *
+ * (C) Copyright 2013
+ * Texas Instruments, <www.ti.com>
+ *
+ * Author: Dan Murphy <dmurphy@ti.com>
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include <common.h>
+#include <usb.h>
+#include <asm-generic/errno.h>
+#include <asm/omap_common.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/sys_proto.h>
+
+#include <linux/compat.h>
+#include <linux/usb/dwc3.h>
+#include <linux/usb/xhci-omap.h>
+
+#include "xhci.h"
+
+/* Declare global data pointer */
+DECLARE_GLOBAL_DATA_PTR;
+
+static struct omap_xhci omap;
+
+inline int __board_usb_init(int index, enum usb_init_type init)
+{
+       return 0;
+}
+int board_usb_init(int index, enum usb_init_type init)
+       __attribute__((weak, alias("__board_usb_init")));
+
+static void dwc3_set_mode(struct dwc3 *dwc3_reg, u32 mode)
+{
+       clrsetbits_le32(&dwc3_reg->g_ctl,
+                       DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG),
+                       DWC3_GCTL_PRTCAPDIR(mode));
+}
+
+static void dwc3_core_soft_reset(struct dwc3 *dwc3_reg)
+{
+       /* Before Resetting PHY, put Core in Reset */
+       setbits_le32(&dwc3_reg->g_ctl, DWC3_GCTL_CORESOFTRESET);
+
+       omap_reset_usb_phy(dwc3_reg);
+
+       /* After PHYs are stable we can take Core out of reset state */
+       clrbits_le32(&dwc3_reg->g_ctl, DWC3_GCTL_CORESOFTRESET);
+}
+
+static int dwc3_core_init(struct dwc3 *dwc3_reg)
+{
+       u32 reg;
+       u32 revision;
+       unsigned int dwc3_hwparams1;
+
+       revision = readl(&dwc3_reg->g_snpsid);
+       /* This should read as U3 followed by revision number */
+       if ((revision & DWC3_GSNPSID_MASK) != 0x55330000) {
+               puts("this is not a DesignWare USB3 DRD Core\n");
+               return -1;
+       }
+
+       dwc3_core_soft_reset(dwc3_reg);
+
+       dwc3_hwparams1 = readl(&dwc3_reg->g_hwparams1);
+
+       reg = readl(&dwc3_reg->g_ctl);
+       reg &= ~DWC3_GCTL_SCALEDOWN_MASK;
+       reg &= ~DWC3_GCTL_DISSCRAMBLE;
+       switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc3_hwparams1)) {
+       case DWC3_GHWPARAMS1_EN_PWROPT_CLK:
+               reg &= ~DWC3_GCTL_DSBLCLKGTNG;
+               break;
+       default:
+               debug("No power optimization available\n");
+       }
+
+       /*
+        * WORKAROUND: DWC3 revisions <1.90a have a bug
+        * where the device can fail to connect at SuperSpeed
+        * and falls back to high-speed mode which causes
+        * the device to enter a Connect/Disconnect loop
+        */
+       if ((revision & DWC3_REVISION_MASK) < 0x190a)
+               reg |= DWC3_GCTL_U2RSTECN;
+
+       writel(reg, &dwc3_reg->g_ctl);
+
+       return 0;
+}
+
+static int omap_xhci_core_init(struct omap_xhci *omap)
+{
+       int ret = 0;
+
+       omap_enable_phy(omap);
+
+       ret = dwc3_core_init(omap->dwc3_reg);
+       if (ret) {
+               debug("%s:failed to initialize core\n", __func__);
+               return ret;
+       }
+
+       /* We are hard-coding DWC3 core to Host Mode */
+       dwc3_set_mode(omap->dwc3_reg, DWC3_GCTL_PRTCAP_HOST);
+
+       return ret;
+}
+
+static void omap_xhci_core_exit(struct omap_xhci *omap)
+{
+       usb_phy_power(0);
+}
+
+int xhci_hcd_init(int index, struct xhci_hccr **hccr, struct xhci_hcor **hcor)
+{
+       struct omap_xhci *ctx = &omap;
+       int ret = 0;
+
+       ctx->hcd = (struct xhci_hccr *)OMAP_XHCI_BASE;
+       ctx->dwc3_reg = (struct dwc3 *)((char *)(ctx->hcd) + DWC3_REG_OFFSET);
+       ctx->usb3_phy = (struct omap_usb3_phy *)OMAP_OCP1_SCP_BASE;
+       ctx->otg_wrapper = (struct omap_dwc_wrapper *)OMAP_OTG_WRAPPER_BASE;
+
+       ret = board_usb_init(index, USB_INIT_HOST);
+       if (ret != 0) {
+               puts("Failed to initialize board for USB\n");
+               return ret;
+       }
+
+       ret = omap_xhci_core_init(ctx);
+       if (ret < 0) {
+               puts("Failed to initialize xhci\n");
+               return ret;
+       }
+
+       *hccr = (struct xhci_hccr *)(OMAP_XHCI_BASE);
+       *hcor = (struct xhci_hcor *)((uint32_t) *hccr
+                               + HC_LENGTH(xhci_readl(&(*hccr)->cr_capbase)));
+
+       debug("omap-xhci: init hccr %x and hcor %x hc_length %d\n",
+             (uint32_t)*hccr, (uint32_t)*hcor,
+             (uint32_t)HC_LENGTH(xhci_readl(&(*hccr)->cr_capbase)));
+
+       return ret;
+}
+
+void xhci_hcd_stop(int index)
+{
+       struct omap_xhci *ctx = &omap;
+
+       omap_xhci_core_exit(ctx);
+}