Add qemu 2.4.0

[kvmfornfv.git] / qemu / roms / u-boot / board / stx / stxgp3 / tlb.c

diff --git a/qemu/roms/u-boot/board/stx/stxgp3/tlb.c b/qemu/roms/u-boot/board/stx/stxgp3/tlb.c
new file mode 100644 (file)
index 0000000..7c877b2
--- /dev/null
+++ b/qemu/roms/u-boot/board/stx/stxgp3/tlb.c
@@ -0,0 +1,114 @@
+/*
+ * Copyright 2008 Freescale Semiconductor, Inc.
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/mmu.h>
+
+struct fsl_e_tlb_entry tlb_table[] = {
+       /* TLB 0 - for temp stack in cache */
+       SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
+                     MAS3_SX|MAS3_SW|MAS3_SR, 0,
+                     0, 0, BOOKE_PAGESZ_4K, 0),
+       SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
+                     MAS3_SX|MAS3_SW|MAS3_SR, 0,
+                     0, 0, BOOKE_PAGESZ_4K, 0),
+       SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
+                     MAS3_SX|MAS3_SW|MAS3_SR, 0,
+                     0, 0, BOOKE_PAGESZ_4K, 0),
+       SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
+                     MAS3_SX|MAS3_SW|MAS3_SR, 0,
+                     0, 0, BOOKE_PAGESZ_4K, 0),
+
+       /*
+        * TLB 0:       16M     Non-cacheable, guarded
+        * 0xff000000   16M     FLASH
+        * Out of reset this entry is only 4K.
+        */
+       SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE,
+                     MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+                     0, 0, BOOKE_PAGESZ_16M, 1),
+
+       /*
+        * TLB 1:       256M    Non-cacheable, guarded
+        * 0x80000000   256M    PCI1 MEM First half
+        */
+       SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_PHYS, CONFIG_SYS_PCI1_MEM_PHYS,
+                     MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+                     0, 1, BOOKE_PAGESZ_256M, 1),
+
+       /*
+        * TLB 2:       256M    Non-cacheable, guarded
+        * 0x90000000   256M    PCI1 MEM Second half
+        */
+       SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000,
+                     MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+                     0, 2, BOOKE_PAGESZ_256M, 1),
+
+       /*
+        * TLB 3:       256M    Non-cacheable, guarded
+        * 0xc0000000   256M    Rapid IO MEM First half
+        */
+       SET_TLB_ENTRY(1, CONFIG_SYS_RIO_MEM_BASE, CONFIG_SYS_RIO_MEM_BASE,
+                     MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+                     0, 3, BOOKE_PAGESZ_256M, 1),
+
+       /*
+        * TLB 4:       256M    Non-cacheable, guarded
+        * 0xd0000000   256M    Rapid IO MEM Second half
+        */
+       SET_TLB_ENTRY(1, CONFIG_SYS_RIO_MEM_BASE + 0x10000000, CONFIG_SYS_RIO_MEM_BASE + 0x10000000,
+                     MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+                     0, 4, BOOKE_PAGESZ_256M, 1),
+
+       /*
+        * TLB 5:       64M     Non-cacheable, guarded
+        * 0xe000_0000  1M      CCSRBAR
+        * 0xe200_0000  16M     PCI1 IO
+        */
+       SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
+                     MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+                     0, 5, BOOKE_PAGESZ_64M, 1),
+
+       /*
+        * TLB 6:       64M     Cacheable, non-guarded
+        * 0xf000_0000  64M     LBC SDRAM
+        */
+       SET_TLB_ENTRY(1, CONFIG_SYS_LBC_SDRAM_BASE, CONFIG_SYS_LBC_SDRAM_BASE,
+                     MAS3_SX|MAS3_SW|MAS3_SR, 0,
+                     0, 6, BOOKE_PAGESZ_64M, 1),
+
+       /*
+        * TLB 7:       16K     Non-cacheable, guarded
+        * 0xfc000000   16K     Configuration Latch register
+        */
+       SET_TLB_ENTRY(1, CONFIG_SYS_LBC_LCLDEVS_BASE, CONFIG_SYS_LBC_LCLDEVS_BASE,
+                     MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+                     0, 7, BOOKE_PAGESZ_16K, 1),
+
+#if !defined(CONFIG_SPD_EEPROM)
+       /*
+        * TLB 8, 9:    128M    DDR
+        * 0x00000000   64M     DDR System memory
+        * 0x04000000   64M     DDR System memory
+        * Without SPD EEPROM configured DDR, this must be setup manually.
+        * Make sure the TLB count at the top of this table is correct.
+        * Likely it needs to be increased by two for these entries.
+        */
+#error("Update the number of table entries in tlb1_entry")
+       SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
+                     MAS3_SX|MAS3_SW|MAS3_SR, 0,
+                     0, 8, BOOKE_PAGESZ_64M, 1),
+
+       SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x4000000, CONFIG_SYS_DDR_SDRAM_BASE + 0x4000000,
+                     MAS3_SX|MAS3_SW|MAS3_SR, 0,
+                     0, 9, BOOKE_PAGESZ_64M, 1),
+#endif
+};
+
+int num_tlb_entries = ARRAY_SIZE(tlb_table);