Add qemu 2.4.0

[kvmfornfv.git] / qemu / roms / u-boot / board / schulercontrol / sc_sps_1 / sc_sps_1.c

diff --git a/qemu/roms/u-boot/board/schulercontrol/sc_sps_1/sc_sps_1.c b/qemu/roms/u-boot/board/schulercontrol/sc_sps_1/sc_sps_1.c
new file mode 100644 (file)
index 0000000..7f0b591
--- /dev/null
+++ b/qemu/roms/u-boot/board/schulercontrol/sc_sps_1/sc_sps_1.c
@@ -0,0 +1,97 @@
+/*
+ * SchulerControl GmbH, SC_SPS_1 module
+ *
+ * Copyright (C) 2012 Marek Vasut <marex@denx.de>
+ * on behalf of DENX Software Engineering GmbH
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/gpio.h>
+#include <asm/io.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/iomux-mx28.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/sys_proto.h>
+#include <linux/mii.h>
+#include <miiphy.h>
+#include <netdev.h>
+#include <errno.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Functions
+ */
+int board_early_init_f(void)
+{
+       /* IO0 clock at 480MHz */
+       mxs_set_ioclk(MXC_IOCLK0, 480000);
+       /* IO1 clock at 480MHz */
+       mxs_set_ioclk(MXC_IOCLK1, 480000);
+
+       /* SSP0 clock at 96MHz */
+       mxs_set_sspclk(MXC_SSPCLK0, 96000, 0);
+       /* SSP2 clock at 96MHz */
+       mxs_set_sspclk(MXC_SSPCLK2, 96000, 0);
+
+#ifdef CONFIG_CMD_USB
+       mxs_iomux_setup_pad(MX28_PAD_AUART1_CTS__USB0_OVERCURRENT);
+       mxs_iomux_setup_pad(MX28_PAD_AUART2_TX__GPIO_3_9 |
+                       MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL);
+       gpio_direction_output(MX28_PAD_AUART2_TX__GPIO_3_9, 1);
+#endif
+
+       return 0;
+}
+
+int board_init(void)
+{
+       /* Adress of boot parameters */
+       gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
+
+       return 0;
+}
+
+int dram_init(void)
+{
+       return mxs_dram_init();
+}
+
+#ifdef CONFIG_CMD_MMC
+int board_mmc_init(bd_t *bis)
+{
+       return mxsmmc_initialize(bis, 0, NULL, NULL);
+}
+#endif
+
+#ifdef CONFIG_CMD_NET
+int board_eth_init(bd_t *bis)
+{
+       struct mxs_clkctrl_regs *clkctrl_regs =
+               (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
+       int ret;
+
+       ret = cpu_eth_init(bis);
+
+       clrsetbits_le32(&clkctrl_regs->hw_clkctrl_enet,
+               CLKCTRL_ENET_TIME_SEL_MASK,
+               CLKCTRL_ENET_TIME_SEL_RMII_CLK | CLKCTRL_ENET_CLK_OUT_EN);
+
+       ret = fecmxc_initialize_multi(bis, 0, 0, MXS_ENET0_BASE);
+       if (ret) {
+               printf("FEC MXS: Unable to init FEC0\n");
+               return ret;
+       }
+
+       ret = fecmxc_initialize_multi(bis, 1, 1, MXS_ENET1_BASE);
+       if (ret) {
+               printf("FEC MXS: Unable to init FEC1\n");
+               return ret;
+       }
+
+       return ret;
+}
+
+#endif