Add qemu 2.4.0

[kvmfornfv.git] / qemu / roms / u-boot / board / freescale / p2041rdb / ddr.c

diff --git a/qemu/roms/u-boot/board/freescale/p2041rdb/ddr.c b/qemu/roms/u-boot/board/freescale/p2041rdb/ddr.c
new file mode 100644 (file)
index 0000000..b8bbcdf
--- /dev/null
+++ b/qemu/roms/u-boot/board/freescale/p2041rdb/ddr.c
@@ -0,0 +1,140 @@
+/*
+ * Copyright 2011 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * Version 2 as published by the Free Software Foundation.
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <hwconfig.h>
+#include <asm/mmu.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
+#include <asm/fsl_law.h>
+
+struct board_specific_parameters {
+       u32 n_ranks;
+       u32 datarate_mhz_high;
+       u32 clk_adjust;
+       u32 wrlvl_start;
+       u32 cpo;
+       u32 write_data_delay;
+       u32 force_2t;
+};
+
+/*
+ * This table contains all valid speeds we want to override with board
+ * specific parameters. datarate_mhz_high values need to be in ascending order
+ * for each n_ranks group.
+ *
+ * ranges for parameters:
+ *  wr_data_delay = 0-6
+ *  clk adjust = 0-8
+ *  cpo 2-0x1E (30)
+ */
+static const struct board_specific_parameters dimm0[] = {
+       /*
+        * memory controller 0
+        *   num|  hi|  clk| wrlvl | cpo  |wrdata|2T
+        * ranks| mhz|adjst| start | delay|
+        */
+       {2,   750,    3,     5,   0xff,    2,  0},
+       {2,  1250,    4,     6,   0xff,    2,  0},
+       {2,  1350,    5,     7,   0xff,    2,  0},
+       {2,  1666,    5,     8,   0xff,    2,  0},
+       {}
+};
+
+void fsl_ddr_board_options(memctl_options_t *popts,
+                               dimm_params_t *pdimm,
+                               unsigned int ctrl_num)
+{
+       const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
+       ulong ddr_freq;
+
+       if (ctrl_num) {
+               printf("Wrong parameter for controller number %d", ctrl_num);
+               return;
+       }
+       if (!pdimm->n_ranks)
+               return;
+
+       pbsp = dimm0;
+
+       /*
+        * Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr
+        * freqency and n_banks specified in board_specific_parameters table.
+        */
+       ddr_freq = get_ddr_freq(0) / 1000000;
+       while (pbsp->datarate_mhz_high) {
+               if (pbsp->n_ranks == pdimm->n_ranks) {
+                       if (ddr_freq <= pbsp->datarate_mhz_high) {
+                               popts->cpo_override = pbsp->cpo;
+                               popts->write_data_delay =
+                                       pbsp->write_data_delay;
+                               popts->clk_adjust = pbsp->clk_adjust;
+                               popts->wrlvl_start = pbsp->wrlvl_start;
+                               popts->twot_en = pbsp->force_2t;
+                               goto found;
+                       }
+                       pbsp_highest = pbsp;
+               }
+               pbsp++;
+       }
+
+       if (pbsp_highest) {
+               printf("Error: board specific timing not found "
+                       "for data rate %lu MT/s!\n"
+                       "Trying to use the highest speed (%u) parameters\n",
+                       ddr_freq, pbsp_highest->datarate_mhz_high);
+               popts->cpo_override = pbsp_highest->cpo;
+               popts->write_data_delay = pbsp_highest->write_data_delay;
+               popts->clk_adjust = pbsp_highest->clk_adjust;
+               popts->wrlvl_start = pbsp_highest->wrlvl_start;
+               popts->twot_en = pbsp_highest->force_2t;
+       } else {
+               panic("DIMM is not supported by this board");
+       }
+
+found:
+       /*
+        * Factors to consider for half-strength driver enable:
+        *      - number of DIMMs installed
+        */
+       popts->half_strength_driver_enable = 0;
+       /* Write leveling override */
+       popts->wrlvl_override = 1;
+       popts->wrlvl_sample = 0xf;
+
+       /* Rtt and Rtt_WR override */
+       popts->rtt_override = 0;
+
+       /* Enable ZQ calibration */
+       popts->zq_en = 1;
+
+       /* DHC_EN =1, ODT = 60 Ohm */
+       popts->ddr_cdr1 = DDR_CDR1_DHC_EN;
+}
+
+phys_size_t initdram(int board_type)
+{
+       phys_size_t dram_size = 0;
+
+       puts("Initializing....");
+
+       if (fsl_use_spd()) {
+               puts("using SPD\n");
+               dram_size = fsl_ddr_sdram();
+       } else {
+               puts("no SPD and fixed parameters\n");
+               return dram_size;
+       }
+
+       dram_size = setup_ddr_tlbs(dram_size / 0x100000);
+       dram_size *= 0x100000;
+
+       debug("    DDR: ");
+       return dram_size;
+}