Add qemu 2.4.0

[kvmfornfv.git] / qemu / roms / u-boot / arch / powerpc / cpu / mpc512x / ide.c

diff --git a/qemu/roms/u-boot/arch/powerpc/cpu/mpc512x/ide.c b/qemu/roms/u-boot/arch/powerpc/cpu/mpc512x/ide.c
new file mode 100644 (file)
index 0000000..dd11306
--- /dev/null
+++ b/qemu/roms/u-boot/arch/powerpc/cpu/mpc512x/ide.c
@@ -0,0 +1,111 @@
+/*
+ * (C) Copyright 2007-2009 DENX Software Engineering
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/io.h>
+#include <asm/processor.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#if defined(CONFIG_IDE_RESET)
+
+void ide_set_reset (int idereset)
+{
+       volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
+       debug ("ide_set_reset(%d)\n", idereset);
+
+       if (idereset) {
+               out_be32(&im->pata.pata_ata_control, 0);
+       } else {
+               out_be32(&im->pata.pata_ata_control, FSL_ATA_CTRL_ATA_RST_B);
+       }
+       udelay(100);
+}
+
+void init_ide_reset (void)
+{
+       debug ("init_ide_reset\n");
+
+       /*
+        * Clear the reset bit to reset the interface
+        * cf. RefMan MPC5121EE: 28.4.1 Resetting the ATA Bus
+        */
+       ide_set_reset(1);
+
+       /* Assert the reset bit to enable the interface */
+       ide_set_reset(0);
+
+}
+
+#define CALC_TIMING(t) (t + period - 1) / period
+
+int ide_preinit (void)
+{
+       volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
+       long t;
+       const struct {
+               short t0;
+               short t1;
+               short t2_8;
+               short t2_16;
+               short t2i;
+               short t4;
+               short t9;
+               short tA;
+       } pio_specs = {
+               .t0    = 600,
+               .t1    =  70,
+               .t2_8  = 290,
+               .t2_16 = 165,
+               .t2i   =   0,
+               .t4    =  30,
+               .t9    =  20,
+               .tA    =  50,
+       };
+       union {
+               u32 config;
+               struct {
+                       u8 field1;
+                       u8 field2;
+                       u8 field3;
+                       u8 field4;
+               }bytes;
+       } cfg;
+
+       debug ("IDE preinit using PATA peripheral at IMMR-ADDR %08x\n",
+               (u32)&im->pata);
+
+       /* Set the reset bit to 1 to enable the interface */
+       ide_set_reset(0);
+
+       /* Init timings : we use PIO mode 0 timings */
+       t = 1000000000 / gd->arch.ips_clk;      /* period in ns */
+       cfg.bytes.field1 = 3;
+       cfg.bytes.field2 = 3;
+       cfg.bytes.field3 = (pio_specs.t1 + t) / t;
+       cfg.bytes.field4 = (pio_specs.t2_8 + t) / t;
+
+       out_be32(&im->pata.pata_time1, cfg.config);
+
+       cfg.bytes.field1 = (pio_specs.t2_8 + t) / t;
+       cfg.bytes.field2 = (pio_specs.tA + t) / t + 2;
+       cfg.bytes.field3 = 1;
+       cfg.bytes.field4 = (pio_specs.t4 + t) / t;
+
+       out_be32(&im->pata.pata_time2, cfg.config);
+
+       cfg.config = in_be32(&im->pata.pata_time3);
+       cfg.bytes.field1 = (pio_specs.t9 + t) / t;
+
+       out_be32(&im->pata.pata_time3, cfg.config);
+
+       debug ("PATA preinit complete.\n");
+
+       return 0;
+}
+
+#endif /* defined(CONFIG_IDE_RESET) */