Add qemu 2.4.0

[kvmfornfv.git] / qemu / roms / u-boot / arch / arm / include / asm / proc-armv / ptrace.h

diff --git a/qemu/roms/u-boot/arch/arm/include/asm/proc-armv/ptrace.h b/qemu/roms/u-boot/arch/arm/include/asm/proc-armv/ptrace.h
new file mode 100644 (file)
index 0000000..21aef58
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/proc-armv/ptrace.h
@@ -0,0 +1,128 @@
+/*
+ *  linux/include/asm-arm/proc-armv/ptrace.h
+ *
+ *  Copyright (C) 1996-1999 Russell King
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef __ASM_PROC_PTRACE_H
+#define __ASM_PROC_PTRACE_H
+
+#ifdef CONFIG_ARM64
+
+#define PCMASK         0
+
+#ifndef __ASSEMBLY__
+
+/*
+ * This struct defines the way the registers are stored
+ * on the stack during an exception.
+ */
+struct pt_regs {
+       unsigned long elr;
+       unsigned long regs[31];
+};
+
+#endif /* __ASSEMBLY__ */
+
+#else  /* CONFIG_ARM64 */
+
+#define USR26_MODE     0x00
+#define FIQ26_MODE     0x01
+#define IRQ26_MODE     0x02
+#define SVC26_MODE     0x03
+#define USR_MODE       0x10
+#define FIQ_MODE       0x11
+#define IRQ_MODE       0x12
+#define SVC_MODE       0x13
+#define ABT_MODE       0x17
+#define UND_MODE       0x1b
+#define SYSTEM_MODE    0x1f
+#define MODE_MASK      0x1f
+#define T_BIT          0x20
+#define F_BIT          0x40
+#define I_BIT          0x80
+#define CC_V_BIT       (1 << 28)
+#define CC_C_BIT       (1 << 29)
+#define CC_Z_BIT       (1 << 30)
+#define CC_N_BIT       (1 << 31)
+#define PCMASK         0
+
+#ifndef __ASSEMBLY__
+
+/* this struct defines the way the registers are stored on the
+   stack during a system call. */
+
+struct pt_regs {
+       long uregs[18];
+};
+
+#define ARM_cpsr       uregs[16]
+#define ARM_pc         uregs[15]
+#define ARM_lr         uregs[14]
+#define ARM_sp         uregs[13]
+#define ARM_ip         uregs[12]
+#define ARM_fp         uregs[11]
+#define ARM_r10                uregs[10]
+#define ARM_r9         uregs[9]
+#define ARM_r8         uregs[8]
+#define ARM_r7         uregs[7]
+#define ARM_r6         uregs[6]
+#define ARM_r5         uregs[5]
+#define ARM_r4         uregs[4]
+#define ARM_r3         uregs[3]
+#define ARM_r2         uregs[2]
+#define ARM_r1         uregs[1]
+#define ARM_r0         uregs[0]
+#define ARM_ORIG_r0    uregs[17]
+
+#ifdef __KERNEL__
+
+#define user_mode(regs)        \
+       (((regs)->ARM_cpsr & 0xf) == 0)
+
+#ifdef CONFIG_ARM_THUMB
+#define thumb_mode(regs) \
+       (((regs)->ARM_cpsr & T_BIT))
+#else
+#define thumb_mode(regs) (0)
+#endif
+
+#define processor_mode(regs) \
+       ((regs)->ARM_cpsr & MODE_MASK)
+
+#define interrupts_enabled(regs) \
+       (!((regs)->ARM_cpsr & I_BIT))
+
+#define fast_interrupts_enabled(regs) \
+       (!((regs)->ARM_cpsr & F_BIT))
+
+#define condition_codes(regs) \
+       ((regs)->ARM_cpsr & (CC_V_BIT|CC_C_BIT|CC_Z_BIT|CC_N_BIT))
+
+/* Are the current registers suitable for user mode?
+ * (used to maintain security in signal handlers)
+ */
+static inline int valid_user_regs(struct pt_regs *regs)
+{
+       if ((regs->ARM_cpsr & 0xf) == 0 &&
+           (regs->ARM_cpsr & (F_BIT|I_BIT)) == 0)
+               return 1;
+
+       /*
+        * Force CPSR to something logical...
+        */
+       regs->ARM_cpsr &= (CC_V_BIT|CC_C_BIT|CC_Z_BIT|CC_N_BIT|0x10);
+
+       return 0;
+}
+
+#endif /* __KERNEL__ */
+
+#endif /* __ASSEMBLY__ */
+
+#endif /* CONFIG_ARM64 */
+
+#endif