Add qemu 2.4.0

[kvmfornfv.git] / qemu / roms / u-boot / arch / arm / include / asm / arch-nomadik / mtu.h

diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-nomadik/mtu.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-nomadik/mtu.h
new file mode 100644 (file)
index 0000000..f89f242
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-nomadik/mtu.h
@@ -0,0 +1,50 @@
+/*
+ * (C) Copyright 2009 Alessandro Rubini
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#ifndef __ASM_ARCH_MTU_H
+#define __ASM_ARCH_MTU_H
+
+/*
+ * The MTU device hosts four different counters, with 4 set of
+ * registers. These are register names.
+ */
+
+#define MTU_IMSC       0x00    /* Interrupt mask set/clear */
+#define MTU_RIS                0x04    /* Raw interrupt status */
+#define MTU_MIS                0x08    /* Masked interrupt status */
+#define MTU_ICR                0x0C    /* Interrupt clear register */
+
+/* per-timer registers take 0..3 as argument */
+#define MTU_LR(x)      (0x10 + 0x10 * (x) + 0x00)      /* Load value */
+#define MTU_VAL(x)     (0x10 + 0x10 * (x) + 0x04)      /* Current value */
+#define MTU_CR(x)      (0x10 + 0x10 * (x) + 0x08)      /* Control reg */
+#define MTU_BGLR(x)    (0x10 + 0x10 * (x) + 0x0c)      /* At next overflow */
+
+/* bits for the control register */
+#define MTU_CRn_ENA            0x80
+#define MTU_CRn_PERIODIC       0x40    /* if 0 = free-running */
+#define MTU_CRn_PRESCALE_MASK  0x0c
+#define MTU_CRn_PRESCALE_1             0x00
+#define MTU_CRn_PRESCALE_16            0x04
+#define MTU_CRn_PRESCALE_256           0x08
+#define MTU_CRn_32BITS         0x02
+#define MTU_CRn_ONESHOT                0x01    /* if 0 = wraps reloading from BGLR*/
+
+/* Other registers are usual amba/primecell registers, currently not used */
+#define MTU_ITCR       0xff0
+#define MTU_ITOP       0xff4
+
+#define MTU_PERIPH_ID0 0xfe0
+#define MTU_PERIPH_ID1 0xfe4
+#define MTU_PERIPH_ID2 0xfe8
+#define MTU_PERIPH_ID3 0xfeC
+
+#define MTU_PCELL0     0xff0
+#define MTU_PCELL1     0xff4
+#define MTU_PCELL2     0xff8
+#define MTU_PCELL3     0xffC
+
+#endif /* __ASM_ARCH_MTU_H */