Add qemu 2.4.0

[kvmfornfv.git] / qemu / roms / u-boot / arch / arm / include / asm / arch-exynos / spl.h

diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-exynos/spl.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-exynos/spl.h
new file mode 100644 (file)
index 0000000..b1d68c3
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-exynos/spl.h
@@ -0,0 +1,83 @@
+/*
+ * Copyright (c) 2012 The Chromium OS Authors.
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#ifndef __ASM_ARCH_EXYNOS_SPL_H__
+#define __ASM_ARCH_EXYNOS_SPL_H__
+
+#include <asm/arch-exynos/dmc.h>
+
+enum boot_mode {
+       /*
+        * Assign the OM pin values for respective boot modes.
+        * Exynos4 does not support spi boot and the mmc boot OM
+        * pin values are the same across Exynos4 and Exynos5.
+        */
+       BOOT_MODE_MMC = 4,
+       BOOT_MODE_EMMC = 8,     /* EMMC4.4 */
+       BOOT_MODE_SERIAL = 20,
+       /* Boot based on Operating Mode pin settings */
+       BOOT_MODE_OM = 32,
+       BOOT_MODE_USB,  /* Boot using USB download */
+};
+
+#ifndef __ASSEMBLY__
+/* Parameters of early board initialization in SPL */
+struct spl_machine_param {
+       /* Add fields as and when required */
+       u32             signature;
+       u32             version;        /* Version number */
+       u32             size;           /* Size of block */
+       /**
+        * Parameters we expect, in order, terminated with \0. Each parameter
+        * is a single character representing one 32-bit word in this
+        * structure.
+        *
+        * Valid characters in this string are:
+        *
+        * Code         Name
+        * v            mem_iv_size
+        * m            mem_type
+        * u            uboot_size
+        * b            boot_source
+        * f            frequency_mhz (memory frequency in MHz)
+        * a            ARM clock frequency in MHz
+        * s            serial base address
+        * i            i2c base address for early access (meant for PMIC)
+        * r            board rev GPIO numbers used to read board revision
+        *                      (lower halfword=bit 0, upper=bit 1)
+        * M            Memory Manufacturer name
+        * \0           termination
+        */
+       char            params[12];     /* Length must be word-aligned */
+       u32             mem_iv_size;    /* Memory channel interleaving size */
+       enum ddr_mode   mem_type;       /* Type of on-board memory */
+       /*
+        * U-boot size - The iROM mmc copy function used by the SPL takes a
+        * block count paramter to describe the u-boot size unlike the spi
+        * boot copy function which just uses the u-boot size directly. Align
+        * the u-boot size to block size (512 bytes) when populating the SPL
+        * table only for mmc boot.
+        */
+       u32             uboot_size;
+       enum boot_mode  boot_source;    /* Boot device */
+       unsigned        frequency_mhz;  /* Frequency of memory in MHz */
+       unsigned        arm_freq_mhz;   /* ARM Frequency in MHz */
+       u32             serial_base;    /* Serial base address */
+       u32             i2c_base;       /* i2c base address */
+       u32             board_rev_gpios;        /* Board revision GPIOs */
+       enum mem_manuf  mem_manuf;      /* Memory Manufacturer */
+} __attribute__((__packed__));
+#endif
+
+/**
+ * Validate signature and return a pointer to the parameter table.  If the
+ * signature is invalid, call panic() and never return.
+ *
+ * @return pointer to the parameter table if signature matched or never return.
+ */
+struct spl_machine_param *spl_get_machine_params(void);
+
+#endif /* __ASM_ARCH_EXYNOS_SPL_H__ */