Add qemu 2.4.0

[kvmfornfv.git] / qemu / roms / u-boot / arch / arm / cpu / arm926ejs / lpc32xx / cpu.c

diff --git a/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/lpc32xx/cpu.c b/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/lpc32xx/cpu.c
new file mode 100644 (file)
index 0000000..35095a9
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/lpc32xx/cpu.c
@@ -0,0 +1,57 @@
+/*
+ * Copyright (C) 2011 by Vladimir Zapolskiy <vz@mleia.com>
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/clk.h>
+#include <asm/arch/wdt.h>
+#include <asm/io.h>
+
+static struct clk_pm_regs *clk = (struct clk_pm_regs *)CLK_PM_BASE;
+static struct wdt_regs  *wdt = (struct wdt_regs *)WDT_BASE;
+
+void reset_cpu(ulong addr)
+{
+       /* Enable watchdog clock */
+       setbits_le32(&clk->timclk_ctrl, CLK_TIMCLK_WATCHDOG);
+
+       /* Reset pulse length is 13005 peripheral clock frames */
+       writel(13000, &wdt->pulse);
+
+       /* Force WDOG_RESET2 and RESOUT_N signal active */
+       writel(WDTIM_MCTRL_RESFRC2 | WDTIM_MCTRL_RESFRC1 | WDTIM_MCTRL_M_RES2,
+              &wdt->mctrl);
+
+       while (1)
+               /* NOP */;
+}
+
+#if defined(CONFIG_ARCH_CPU_INIT)
+int arch_cpu_init(void)
+{
+       /*
+        * It might be necessary to flush data cache, if U-boot is loaded
+        * from kickstart bootloader, e.g. from S1L loader
+        */
+       flush_dcache_all();
+
+       return 0;
+}
+#else
+#error "You have to select CONFIG_ARCH_CPU_INIT"
+#endif
+
+#if defined(CONFIG_DISPLAY_CPUINFO)
+int print_cpuinfo(void)
+{
+       printf("CPU:   NXP LPC32XX\n");
+       printf("CPU clock:        %uMHz\n", get_hclk_pll_rate() / 1000000);
+       printf("AHB bus clock:    %uMHz\n", get_hclk_clk_rate() / 1000000);
+       printf("Peripheral clock: %uMHz\n", get_periph_clk_rate() / 1000000);
+
+       return 0;
+}
+#endif