#define TEGRA114 0x35
#define TEGRA124 0x40
#define TEGRA132 0x13
+#define TEGRA210 0x21
#define TEGRA_FUSE_SKU_CALIB_0 0xf0
#define TEGRA30_FUSE_SATA_CALIB 0x124
int cpu_speedo_id;
int cpu_speedo_value;
int cpu_iddq_value;
- int core_process_id;
+ int soc_process_id;
int soc_speedo_id;
- int gpu_speedo_id;
+ int soc_speedo_value;
int gpu_process_id;
+ int gpu_speedo_id;
int gpu_speedo_value;
enum tegra_revision revision;
};
u32 tegra_read_straps(void);
+u32 tegra_read_ram_code(void);
u32 tegra_read_chipid(void);
int tegra_fuse_readl(unsigned long offset, u32 *value);