These changes are the raw update to linux-4.4.6-rt14. Kernel sources

[kvmfornfv.git] / kernel / include / linux / serial_sci.h

diff --git a/kernel/include/linux/serial_sci.h b/kernel/include/linux/serial_sci.h
index 6c5e3bb..7c536ac 100644 (file)
--- a/kernel/include/linux/serial_sci.h
+++ b/kernel/include/linux/serial_sci.h
@@ -1,6 +1,7 @@
 #ifndef __LINUX_SERIAL_SCI_H
 #define __LINUX_SERIAL_SCI_H
 
+#include <linux/bitops.h>
 #include <linux/serial_core.h>
 #include <linux/sh_dma.h>
 
@@ -10,59 +11,16 @@
 
 #define SCIx_NOT_SUPPORTED     (-1)
 
-/* SCSMR (Serial Mode Register) */
-#define SCSMR_CHR      (1 << 6)        /* 7-bit Character Length */
-#define SCSMR_PE       (1 << 5)        /* Parity Enable */
-#define SCSMR_ODD      (1 << 4)        /* Odd Parity */
-#define SCSMR_STOP     (1 << 3)        /* Stop Bit Length */
-#define SCSMR_CKS      0x0003          /* Clock Select */
-
 /* Serial Control Register (@ = not supported by all parts) */
-#define SCSCR_TIE      (1 << 7)        /* Transmit Interrupt Enable */
-#define SCSCR_RIE      (1 << 6)        /* Receive Interrupt Enable */
-#define SCSCR_TE       (1 << 5)        /* Transmit Enable */
-#define SCSCR_RE       (1 << 4)        /* Receive Enable */
-#define SCSCR_REIE     (1 << 3)        /* Receive Error Interrupt Enable @ */
-#define SCSCR_TOIE     (1 << 2)        /* Timeout Interrupt Enable @ */
-#define SCSCR_CKE1     (1 << 1)        /* Clock Enable 1 */
-#define SCSCR_CKE0     (1 << 0)        /* Clock Enable 0 */
-/* SCIFA/SCIFB only */
-#define SCSCR_TDRQE    (1 << 15)       /* Tx Data Transfer Request Enable */
-#define SCSCR_RDRQE    (1 << 14)       /* Rx Data Transfer Request Enable */
-
-/* SCxSR (Serial Status Register) on SCI */
-#define SCI_TDRE  0x80                 /* Transmit Data Register Empty */
-#define SCI_RDRF  0x40                 /* Receive Data Register Full */
-#define SCI_ORER  0x20                 /* Overrun Error */
-#define SCI_FER   0x10                 /* Framing Error */
-#define SCI_PER   0x08                 /* Parity Error */
-#define SCI_TEND  0x04                 /* Transmit End */
-
-#define SCI_DEFAULT_ERROR_MASK (SCI_PER | SCI_FER)
-
-/* SCxSR (Serial Status Register) on SCIF, HSCIF */
-#define SCIF_ER    0x0080              /* Receive Error */
-#define SCIF_TEND  0x0040              /* Transmission End */
-#define SCIF_TDFE  0x0020              /* Transmit FIFO Data Empty */
-#define SCIF_BRK   0x0010              /* Break Detect */
-#define SCIF_FER   0x0008              /* Framing Error */
-#define SCIF_PER   0x0004              /* Parity Error */
-#define SCIF_RDF   0x0002              /* Receive FIFO Data Full */
-#define SCIF_DR    0x0001              /* Receive Data Ready */
-
-#define SCIF_DEFAULT_ERROR_MASK (SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK)
-
-/* SCFCR (FIFO Control Register) */
-#define SCFCR_LOOP     (1 << 0)        /* Loopback Test */
-
-/* SCSPTR (Serial Port Register), optional */
-#define SCSPTR_RTSIO   (1 << 7)        /* Serial Port RTS Pin Input/Output */
-#define SCSPTR_CTSIO   (1 << 5)        /* Serial Port CTS Pin Input/Output */
-#define SCSPTR_SPB2IO  (1 << 1)        /* Serial Port Break Input/Output */
-#define SCSPTR_SPB2DT  (1 << 0)        /* Serial Port Break Data */
-
-/* HSSRR HSCIF */
-#define HSCIF_SRE      0x8000          /* Sampling Rate Register Enable */
+#define SCSCR_TIE      BIT(7)  /* Transmit Interrupt Enable */
+#define SCSCR_RIE      BIT(6)  /* Receive Interrupt Enable */
+#define SCSCR_TE       BIT(5)  /* Transmit Enable */
+#define SCSCR_RE       BIT(4)  /* Receive Enable */
+#define SCSCR_REIE     BIT(3)  /* Receive Error Interrupt Enable @ */
+#define SCSCR_TOIE     BIT(2)  /* Timeout Interrupt Enable @ */
+#define SCSCR_CKE1     BIT(1)  /* Clock Enable 1 */
+#define SCSCR_CKE0     BIT(0)  /* Clock Enable 0 */
+
 
 enum {
        SCIx_PROBE_REGTYPE,
@@ -82,28 +40,6 @@ enum {
        SCIx_NR_REGTYPES,
 };
 
-/*
- * SCI register subset common for all port types.
- * Not all registers will exist on all parts.
- */
-enum {
-       SCSMR,                          /* Serial Mode Register */
-       SCBRR,                          /* Bit Rate Register */
-       SCSCR,                          /* Serial Control Register */
-       SCxSR,                          /* Serial Status Register */
-       SCFCR,                          /* FIFO Control Register */
-       SCFDR,                          /* FIFO Data Count Register */
-       SCxTDR,                         /* Transmit (FIFO) Data Register */
-       SCxRDR,                         /* Receive (FIFO) Data Register */
-       SCLSR,                          /* Line Status Register */
-       SCTFDR,                         /* Transmit FIFO Data Count Register */
-       SCRFDR,                         /* Receive FIFO Data Count Register */
-       SCSPTR,                         /* Serial Port Register */
-       HSSRR,                          /* Sampling Rate Register */
-
-       SCIx_NR_REGS,
-};
-
 struct device;
 
 struct plat_sci_port_ops {
@@ -113,7 +49,7 @@ struct plat_sci_port_ops {
 /*
  * Port-specific capabilities
  */
-#define SCIx_HAVE_RTSCTS       (1 << 0)
+#define SCIx_HAVE_RTSCTS       BIT(0)
 
 /*
  * Platform device specific platform_data struct