These changes are the raw update to linux-4.4.6-rt14. Kernel sources

[kvmfornfv.git] / kernel / include / linux / irqchip / mips-gic.h

diff --git a/kernel/include/linux/irqchip/mips-gic.h b/kernel/include/linux/irqchip/mips-gic.h
index 9b1ad37..ce824db 100644 (file)
--- a/kernel/include/linux/irqchip/mips-gic.h
+++ b/kernel/include/linux/irqchip/mips-gic.h
@@ -9,6 +9,7 @@
 #define __LINUX_IRQCHIP_MIPS_GIC_H
 
 #include <linux/clocksource.h>
+#include <linux/ioport.h>
 
 #define GIC_MAX_INTRS                  256
 
@@ -41,12 +42,20 @@
 
 /* Shared Global Counter */
 #define GIC_SH_COUNTER_31_00_OFS       0x0010
+/* 64-bit counter register for CM3 */
+#define GIC_SH_COUNTER_OFS             GIC_SH_COUNTER_31_00_OFS
 #define GIC_SH_COUNTER_63_32_OFS       0x0014
 #define GIC_SH_REVISIONID_OFS          0x0020
 
 /* Convert an interrupt number to a byte offset/bit for multi-word registers */
-#define GIC_INTR_OFS(intr)             (((intr) / 32) * 4)
-#define GIC_INTR_BIT(intr)             ((intr) % 32)
+#define GIC_INTR_OFS(intr) ({                          \
+       unsigned bits = mips_cm_is64 ? 64 : 32;         \
+       unsigned reg_idx = (intr) / bits;               \
+       unsigned reg_width = bits / 8;                  \
+                                                       \
+       reg_idx * reg_width;                            \
+})
+#define GIC_INTR_BIT(intr)             ((intr) % (mips_cm_is64 ? 64 : 32))
 
 /* Polarity : Reset Value is always 0 */
 #define GIC_SH_SET_POLARITY_OFS                0x0100
@@ -98,6 +107,8 @@
 #define GIC_VPE_WD_COUNT0_OFS          0x0094
 #define GIC_VPE_WD_INITIAL0_OFS                0x0098
 #define GIC_VPE_COMPARE_LO_OFS         0x00a0
+/* 64-bit Compare register on CM3 */
+#define GIC_VPE_COMPARE_OFS            GIC_VPE_COMPARE_LO_OFS
 #define GIC_VPE_COMPARE_HI_OFS         0x00a4
 
 #define GIC_VPE_EIC_SHADOW_SET_BASE_OFS        0x0100
@@ -235,6 +246,8 @@
 #define GIC_SHARED_TO_HWIRQ(x) (GIC_SHARED_HWIRQ_BASE + (x))
 #define GIC_HWIRQ_TO_SHARED(x) ((x) - GIC_SHARED_HWIRQ_BASE)
 
+#ifdef CONFIG_MIPS_GIC
+
 extern unsigned int gic_present;
 
 extern void gic_init(unsigned long gic_base_addr,
@@ -254,4 +267,18 @@ extern unsigned int plat_ipi_resched_int_xlate(unsigned int);
 extern int gic_get_c0_compare_int(void);
 extern int gic_get_c0_perfcount_int(void);
 extern int gic_get_c0_fdc_int(void);
+extern int gic_get_usm_range(struct resource *gic_usm_res);
+
+#else /* CONFIG_MIPS_GIC */
+
+#define gic_present    0
+
+static inline int gic_get_usm_range(struct resource *gic_usm_res)
+{
+       /* Shouldn't be called. */
+       return -1;
+}
+
+#endif /* CONFIG_MIPS_GIC */
+
 #endif /* __LINUX_IRQCHIP_MIPS_GIC_H */