These changes are the raw update to linux-4.4.6-rt14. Kernel sources

[kvmfornfv.git] / kernel / drivers / tty / serial / msm_serial.h

diff --git a/kernel/drivers/tty/serial/msm_serial.h b/kernel/drivers/tty/serial/msm_serial.h
index 737f69f..1786458 100644 (file)
--- a/kernel/drivers/tty/serial/msm_serial.h
+++ b/kernel/drivers/tty/serial/msm_serial.h
@@ -20,11 +20,12 @@
 
 #define UART_MR1_AUTO_RFR_LEVEL0       0x3F
 #define UART_MR1_AUTO_RFR_LEVEL1       0x3FF00
-#define UART_MR1_RX_RDY_CTL                    (1 << 7)
-#define UART_MR1_CTS_CTL                       (1 << 6)
+#define UART_DM_MR1_AUTO_RFR_LEVEL1    0xFFFFFF00
+#define UART_MR1_RX_RDY_CTL            BIT(7)
+#define UART_MR1_CTS_CTL               BIT(6)
 
 #define UART_MR2                       0x0004
-#define UART_MR2_ERROR_MODE            (1 << 6)
+#define UART_MR2_ERROR_MODE            BIT(6)
 #define UART_MR2_BITS_PER_CHAR         0x30
 #define UART_MR2_BITS_PER_CHAR_5       (0x0 << 4)
 #define UART_MR2_BITS_PER_CHAR_6       (0x1 << 4)
@@ -58,26 +59,28 @@
 #define UART_CR_CMD_SET_RFR            (13 << 4)
 #define UART_CR_CMD_RESET_RFR          (14 << 4)
 #define UART_CR_CMD_PROTECTION_EN      (16 << 4)
+#define UART_CR_CMD_STALE_EVENT_DISABLE        (6 << 8)
 #define UART_CR_CMD_STALE_EVENT_ENABLE (80 << 4)
 #define UART_CR_CMD_FORCE_STALE                (4 << 8)
 #define UART_CR_CMD_RESET_TX_READY     (3 << 8)
-#define UART_CR_TX_DISABLE             (1 << 3)
-#define UART_CR_TX_ENABLE              (1 << 2)
-#define UART_CR_RX_DISABLE             (1 << 1)
-#define UART_CR_RX_ENABLE              (1 << 0)
+#define UART_CR_TX_DISABLE             BIT(3)
+#define UART_CR_TX_ENABLE              BIT(2)
+#define UART_CR_RX_DISABLE             BIT(1)
+#define UART_CR_RX_ENABLE              BIT(0)
 #define UART_CR_CMD_RESET_RXBREAK_START        ((1 << 11) | (2 << 4))
 
 #define UART_IMR               0x0014
-#define UART_IMR_TXLEV         (1 << 0)
-#define UART_IMR_RXSTALE       (1 << 3)
-#define UART_IMR_RXLEV         (1 << 4)
-#define UART_IMR_DELTA_CTS     (1 << 5)
-#define UART_IMR_CURRENT_CTS   (1 << 6)
-#define UART_IMR_RXBREAK_START (1 << 10)
+#define UART_IMR_TXLEV                 BIT(0)
+#define UART_IMR_RXSTALE               BIT(3)
+#define UART_IMR_RXLEV                 BIT(4)
+#define UART_IMR_DELTA_CTS             BIT(5)
+#define UART_IMR_CURRENT_CTS           BIT(6)
+#define UART_IMR_RXBREAK_START         BIT(10)
 
 #define UART_IPR_RXSTALE_LAST          0x20
 #define UART_IPR_STALE_LSB             0x1F
 #define UART_IPR_STALE_TIMEOUT_MSB     0x3FF80
+#define UART_DM_IPR_STALE_TIMEOUT_MSB  0xFFFFFF80
 
 #define UART_IPR       0x0018
 #define UART_TFWR      0x001C
@@ -96,20 +99,20 @@
 #define UART_TEST_CTRL         0x0050
 
 #define UART_SR                        0x0008
-#define UART_SR_HUNT_CHAR      (1 << 7)
-#define UART_SR_RX_BREAK       (1 << 6)
-#define UART_SR_PAR_FRAME_ERR  (1 << 5)
-#define UART_SR_OVERRUN                (1 << 4)
-#define UART_SR_TX_EMPTY       (1 << 3)
-#define UART_SR_TX_READY       (1 << 2)
-#define UART_SR_RX_FULL                (1 << 1)
-#define UART_SR_RX_READY       (1 << 0)
+#define UART_SR_HUNT_CHAR      BIT(7)
+#define UART_SR_RX_BREAK       BIT(6)
+#define UART_SR_PAR_FRAME_ERR  BIT(5)
+#define UART_SR_OVERRUN                BIT(4)
+#define UART_SR_TX_EMPTY       BIT(3)
+#define UART_SR_TX_READY       BIT(2)
+#define UART_SR_RX_FULL                BIT(1)
+#define UART_SR_RX_READY       BIT(0)
 
 #define UART_RF                        0x000C
 #define UARTDM_RF              0x0070
 #define UART_MISR              0x0010
 #define UART_ISR               0x0014
-#define UART_ISR_TX_READY      (1 << 7)
+#define UART_ISR_TX_READY      BIT(7)
 
 #define UARTDM_RXFS            0x50
 #define UARTDM_RXFS_BUF_SHIFT  0x7
@@ -119,6 +122,12 @@
 #define UARTDM_DMEN_RX_SC_ENABLE BIT(5)
 #define UARTDM_DMEN_TX_SC_ENABLE BIT(4)
 
+#define UARTDM_DMEN_TX_BAM_ENABLE BIT(2)       /* UARTDM_1P4 */
+#define UARTDM_DMEN_TX_DM_ENABLE  BIT(0)       /* < UARTDM_1P4 */
+
+#define UARTDM_DMEN_RX_BAM_ENABLE BIT(3)       /* UARTDM_1P4 */
+#define UARTDM_DMEN_RX_DM_ENABLE  BIT(1)       /* < UARTDM_1P4 */
+
 #define UARTDM_DMRX            0x34
 #define UARTDM_NCF_TX          0x40
 #define UARTDM_RX_TOTAL_SNAP   0x38