These changes are the raw update to linux-4.4.6-rt14. Kernel sources

[kvmfornfv.git] / kernel / drivers / staging / rtl8188eu / include / pwrseq.h

diff --git a/kernel/drivers/staging/rtl8188eu/include/pwrseq.h b/kernel/drivers/staging/rtl8188eu/include/pwrseq.h
index 43db92d..8c876c6 100644 (file)
--- a/kernel/drivers/staging/rtl8188eu/include/pwrseq.h
+++ b/kernel/drivers/staging/rtl8188eu/include/pwrseq.h
@@ -65,31 +65,31 @@
         * comment here
         */                                                             \
        {0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
-       PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT1, BIT1},                 \
+       PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT(1), BIT(1)},             \
        /* wait till 0x04[17] = 1    power ready*/      \
        {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
-       PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0|BIT1, 0},                 \
+       PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0) | BIT(1), 0},           \
        /* 0x02[1:0] = 0        reset BB*/                              \
        {0x0026, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
-       PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, BIT7},                   \
+       PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(7), BIT(7)},               \
        /*0x24[23] = 2b'01 schmit trigger */                            \
        {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
-       PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0},                      \
+       PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(7), 0},                    \
        /* 0x04[15] = 0 disable HWPDN (control by DRV)*/                \
        {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
-       PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4|BIT3, 0},                 \
+       PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4) | BIT(3), 0},           \
        /*0x04[12:11] = 2b'00 disable WL suspend*/                      \
        {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
-       PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},                   \
+       PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), BIT(0)},               \
        /*0x04[8] = 1 polling until return 0*/                          \
        {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
-       PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT0, 0},                    \
+       PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT(0), 0},                  \
        /*wait till 0x04[8] = 0*/                                       \
        {0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
-       PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0},                      \
+       PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), 0},                    \
        /*LDO normal mode*/                                             \
        {0x0074, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,   \
-       PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, BIT4},                   \
+       PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), BIT(4)},               \
        /*SDIO Driving*/
 
 #define RTL8188E_TRANS_ACT_TO_CARDEMU                                  \
@@ -102,13 +102,13 @@
        PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0},                      \
        /*0x1F[7:0] = 0 turn off RF*/                                   \
        {0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
-       PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, BIT4},                   \
+       PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), BIT(4)},               \
        /*LDO Sleep mode*/                                              \
        {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
-       PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1},                   \
+       PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), BIT(1)},               \
        /*0x04[9] = 1 turn off MAC by HW state machine*/                \
        {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
-       PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT1, 0},                    \
+       PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT(1), 0},                  \
        /*wait till 0x04[9] = 0 polling until return 0 to disable*/
 
 #define RTL8188E_TRANS_CARDEMU_TO_SUS                                  \
@@ -119,28 +119,28 @@
         */                                                             \
        {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,                      \
        PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC,           \
-       PWR_CMD_WRITE, BIT3|BIT4, BIT3},                                \
+       PWR_CMD_WRITE, BIT(3) | BIT(4), BIT(3)},                        \
        /* 0x04[12:11] = 2b'01enable WL suspend */                      \
        {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,    \
-       PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3|BIT4, BIT3|BIT4},         \
+       PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3) | BIT(4), BIT(3) | BIT(4)}, \
        /* 0x04[12:11] = 2b'11enable WL suspend for PCIe */             \
        {0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,                      \
        PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC,           \
-       PWR_CMD_WRITE, 0xFF, BIT7},                                     \
+       PWR_CMD_WRITE, 0xFF, BIT(7)},                                   \
        /* 0x04[31:30] = 2b'10 enable enable bandgap mbias in suspend */\
        {0x0041, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,                      \
        PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC,           \
-       PWR_CMD_WRITE, BIT4, 0},                                        \
+       PWR_CMD_WRITE, BIT(4), 0},                                      \
        /*Clear SIC_EN register 0x40[12] = 1'b0 */                      \
        {0xfe10, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,                      \
        PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC,           \
-       PWR_CMD_WRITE, BIT4, BIT4},                                     \
+       PWR_CMD_WRITE, BIT(4), BIT(4)},                                 \
        /*Set USB suspend enable local register  0xfe10[4]=1 */         \
        {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,   \
-       PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, BIT0},                  \
+       PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT(0), BIT(0)},              \
        /*Set SDIO suspend local register*/                             \
        {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,   \
-       PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, 0},                   \
+       PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT(1), 0},                 \
        /*wait power state to suspend*/
 
 #define RTL8188E_TRANS_SUS_TO_CARDEMU                                  \
@@ -150,13 +150,13 @@
         * comments here
         */                                                             \
        {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,   \
-       PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, 0},                     \
+       PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT(0), 0},                   \
        /*Set SDIO suspend local register*/                             \
        {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,   \
-       PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, BIT1},                \
+       PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT(1), BIT(1)},            \
        /*wait power state to suspend*/                                 \
        {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
-       PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3|BIT4, 0},                 \
+       PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3) | BIT(4), 0},           \
        /*0x04[12:11] = 2b'01enable WL suspend*/
 
 #define RTL8188E_TRANS_CARDEMU_TO_CARDDIS                              \
@@ -166,11 +166,11 @@
         * comments here
         */                                                             \
        {0x0026, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
-       PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, BIT7},                   \
+       PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(7), BIT(7)},               \
        /*0x24[23] = 2b'01 schmit trigger */                            \
        {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,                      \
        PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC,           \
-       PWR_CMD_WRITE, BIT3|BIT4, BIT3},                                \
+       PWR_CMD_WRITE, BIT(3) | BIT(4), BIT(3)},                        \
        /*0x04[12:11] = 2b'01 enable WL suspend*/                       \
        {0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,                      \
        PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC,           \
@@ -178,16 +178,16 @@
        /* 0x04[31:30] = 2b'10 enable enable bandgap mbias in suspend */\
        {0x0041, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,                      \
        PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC,           \
-       PWR_CMD_WRITE, BIT4, 0},                                        \
+       PWR_CMD_WRITE, BIT(4), 0},                                      \
        /*Clear SIC_EN register 0x40[12] = 1'b0 */                      \
        {0xfe10, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,    \
-       PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, BIT4},                   \
+       PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), BIT(4)},               \
        /*Set USB suspend enable local register  0xfe10[4]=1 */         \
        {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,   \
-       PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, BIT0},                  \
+       PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT(0), BIT(0)},              \
        /*Set SDIO suspend local register*/                             \
        {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,   \
-       PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, 0},                   \
+       PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT(1), 0},                 \
        /*wait power state to suspend*/
 
 #define RTL8188E_TRANS_CARDDIS_TO_CARDEMU                              \
@@ -197,13 +197,13 @@
         * comments here
         */                                                             \
        {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,   \
-       PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, 0},                     \
+       PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT(0), 0},                   \
        /*Set SDIO suspend local register*/                             \
        {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,   \
-       PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, BIT1},                \
+       PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT(1), BIT(1)},            \
        /*wait power state to suspend*/                                 \
        {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
-       PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3|BIT4, 0},                 \
+       PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3) | BIT(4), 0},           \
        /*0x04[12:11] = 2b'01enable WL suspend*/
 
 #define RTL8188E_TRANS_CARDEMU_TO_PDN                                  \
@@ -213,10 +213,10 @@
         * comments here
         */                                                             \
        {0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
-       PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0},                      \
+       PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), 0},                    \
        /* 0x04[16] = 0*/                                               \
        {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
-       PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, BIT7},                   \
+       PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(7), BIT(7)},               \
        /* 0x04[15] = 1*/
 
 #define RTL8188E_TRANS_PDN_TO_CARDEMU                                  \
@@ -226,7 +226,7 @@
         * comments here
         */                                                             \
        {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
-       PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0},                      \
+       PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(7), 0},                    \
        /* 0x04[15] = 0*/
 
 /* This is used by driver for LPSRadioOff Procedure, not for FW LPS Step */
@@ -251,7 +251,7 @@
        PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},                    \
        /*Should be zero if no packet is transmitting*/                 \
        {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
-       PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0},                      \
+       PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), 0},                    \
        /*CCK and OFDM are disabled,and clock are gated*/               \
        {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
        PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0,                             \
@@ -259,9 +259,9 @@
        {0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
        PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x3F},/*Reset MAC TRX*/  \
        {0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
-       PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0},/*check if removed later*/\
+       PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), 0},/*check if removed later*/\
        {0x0553, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
-       PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, BIT5},                   \
+       PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(5), BIT(5)},               \
        /*Respond TxOK to scheduler*/
 
 
@@ -280,22 +280,22 @@
        {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
        PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_MS}, /*Delay*/ \
        {0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
-       PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0},                      \
+       PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), 0},                    \
        /* 0x08[4] = 0 switch TSF to 40M */                             \
        {0x0109, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
-       PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT7, 0},                    \
+       PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT(7), 0},                  \
        /* Polling 0x109[7]=0  TSF in 40M */                            \
        {0x0029, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
-       PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6|BIT7, 0},                 \
+       PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(6) | BIT(7), 0},           \
        /* 0x29[7:6] = 2b'00  enable BB clock */                        \
        {0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
-       PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1},                   \
+       PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), BIT(1)},               \
        /* 0x101[1] = 1 */                                              \
        {0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
        PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF},                   \
        /* 0x100[7:0] = 0xFF enable WMAC TRX */                         \
        {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
-       PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1|BIT0, BIT1|BIT0},         \
+       PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1) | BIT(0), BIT(1) | BIT(0)}, \
        /* 0x02[1:0] = 2b'11 enable BB macro */                         \
        {0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
        PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0}, /*.  0x522 = 0*/