#include <phy.h>
-#define read_next_pair(array, v1, v2, i) \
- do { \
- i += 2; \
- v1 = array[i]; \
- v2 = array[i+1]; \
- } while (0)
-
-
/* AGC_TAB_1T.TXT */
static u32 array_agc_tab_1t_8188e[] = {
static bool set_baseband_agc_config(struct adapter *adapt)
{
u32 i;
- u32 arraylen = sizeof(array_agc_tab_1t_8188e)/sizeof(u32);
+ const u32 arraylen = ARRAY_SIZE(array_agc_tab_1t_8188e);
u32 *array = array_agc_tab_1t_8188e;
for (i = 0; i < arraylen; i += 2) {
u32 v1 = array[i];
- u32 v2 = array[i+1];
+ u32 v2 = array[i + 1];
if (v1 < 0xCDCDCDCD) {
phy_set_bb_reg(adapt, v1, bMaskDWord, v2);
static bool set_baseband_phy_config(struct adapter *adapt)
{
u32 i;
- u32 arraylen = sizeof(array_phy_reg_1t_8188e)/sizeof(u32);
+ const u32 arraylen = ARRAY_SIZE(array_phy_reg_1t_8188e);
u32 *array = array_phy_reg_1t_8188e;
for (i = 0; i < arraylen; i += 2) {
u32 v1 = array[i];
- u32 v2 = array[i+1];
+ u32 v2 = array[i + 1];
if (v1 < 0xCDCDCDCD)
rtl_bb_delay(adapt, v1, v2);
};
-static void store_pwrindex_offset(struct adapter *Adapter, u32 regaddr, u32 bitmask, u32 data)
+static void store_pwrindex_offset(struct adapter *adapter,
+ u32 regaddr, u32 bitmask, u32 data)
{
- struct hal_data_8188e *hal_data = GET_HAL_DATA(Adapter);
- u8 pwrGrpCnt = hal_data->pwrGroupCnt;
+ struct hal_data_8188e *hal_data = GET_HAL_DATA(adapter);
+ u32 * const power_level_offset =
+ hal_data->MCSTxPowerLevelOriginalOffset[hal_data->pwrGroupCnt];
if (regaddr == rTxAGC_A_Rate18_06)
- hal_data->MCSTxPowerLevelOriginalOffset[pwrGrpCnt][0] = data;
+ power_level_offset[0] = data;
if (regaddr == rTxAGC_A_Rate54_24)
- hal_data->MCSTxPowerLevelOriginalOffset[pwrGrpCnt][1] = data;
+ power_level_offset[1] = data;
if (regaddr == rTxAGC_A_CCK1_Mcs32)
- hal_data->MCSTxPowerLevelOriginalOffset[pwrGrpCnt][6] = data;
+ power_level_offset[6] = data;
if (regaddr == rTxAGC_B_CCK11_A_CCK2_11 && bitmask == 0xffffff00)
- hal_data->MCSTxPowerLevelOriginalOffset[pwrGrpCnt][7] = data;
+ power_level_offset[7] = data;
if (regaddr == rTxAGC_A_Mcs03_Mcs00)
- hal_data->MCSTxPowerLevelOriginalOffset[pwrGrpCnt][2] = data;
+ power_level_offset[2] = data;
if (regaddr == rTxAGC_A_Mcs07_Mcs04)
- hal_data->MCSTxPowerLevelOriginalOffset[pwrGrpCnt][3] = data;
+ power_level_offset[3] = data;
if (regaddr == rTxAGC_A_Mcs11_Mcs08)
- hal_data->MCSTxPowerLevelOriginalOffset[pwrGrpCnt][4] = data;
+ power_level_offset[4] = data;
if (regaddr == rTxAGC_A_Mcs15_Mcs12) {
- hal_data->MCSTxPowerLevelOriginalOffset[pwrGrpCnt][5] = data;
+ power_level_offset[5] = data;
if (hal_data->rf_type == RF_1T1R)
hal_data->pwrGroupCnt++;
}
if (regaddr == rTxAGC_B_Rate18_06)
- hal_data->MCSTxPowerLevelOriginalOffset[pwrGrpCnt][8] = data;
+ power_level_offset[8] = data;
if (regaddr == rTxAGC_B_Rate54_24)
- hal_data->MCSTxPowerLevelOriginalOffset[pwrGrpCnt][9] = data;
+ power_level_offset[9] = data;
if (regaddr == rTxAGC_B_CCK1_55_Mcs32)
- hal_data->MCSTxPowerLevelOriginalOffset[pwrGrpCnt][14] = data;
+ power_level_offset[14] = data;
if (regaddr == rTxAGC_B_CCK11_A_CCK2_11 && bitmask == 0x000000ff)
- hal_data->MCSTxPowerLevelOriginalOffset[pwrGrpCnt][15] = data;
+ power_level_offset[15] = data;
if (regaddr == rTxAGC_B_Mcs03_Mcs00)
- hal_data->MCSTxPowerLevelOriginalOffset[pwrGrpCnt][10] = data;
+ power_level_offset[10] = data;
if (regaddr == rTxAGC_B_Mcs07_Mcs04)
- hal_data->MCSTxPowerLevelOriginalOffset[pwrGrpCnt][11] = data;
+ power_level_offset[11] = data;
if (regaddr == rTxAGC_B_Mcs11_Mcs08)
- hal_data->MCSTxPowerLevelOriginalOffset[pwrGrpCnt][12] = data;
+ power_level_offset[12] = data;
if (regaddr == rTxAGC_B_Mcs15_Mcs12) {
- hal_data->MCSTxPowerLevelOriginalOffset[pwrGrpCnt][13] = data;
+ power_level_offset[13] = data;
if (hal_data->rf_type != RF_1T1R)
hal_data->pwrGroupCnt++;
}
}
static void rtl_addr_delay(struct adapter *adapt,
- u32 addr, u32 bit_mask, u32 data)
+ u32 addr, u32 bit_mask, u32 data)
{
switch (addr) {
case 0xfe:
static bool config_bb_with_pgheader(struct adapter *adapt)
{
- u32 i = 0;
- u32 arraylen = sizeof(array_phy_reg_pg_8188e) / sizeof(u32);
+ u32 i;
+ const u32 arraylen = ARRAY_SIZE(array_phy_reg_pg_8188e);
u32 *array = array_phy_reg_pg_8188e;
for (i = 0; i < arraylen; i += 3) {
u32 v1 = array[i];
- u32 v2 = array[i+1];
- u32 v3 = array[i+2];
+ u32 v2 = array[i + 1];
+ u32 v3 = array[i + 2];
if (v1 < 0xCDCDCDCD)
rtl_addr_delay(adapt, v1, v2, v3);
return true;
}
-static void rtl88e_phy_init_bb_rf_register_definition(struct adapter *Adapter)
+static void rtl88e_phy_init_bb_rf_register_definition(struct adapter *adapter)
{
- struct hal_data_8188e *hal_data = GET_HAL_DATA(Adapter);
+ struct hal_data_8188e *hal_data = GET_HAL_DATA(adapter);
struct bb_reg_def *reg[4];
- reg[RF_PATH_A] = &(hal_data->PHYRegDef[RF_PATH_A]);
- reg[RF_PATH_B] = &(hal_data->PHYRegDef[RF_PATH_B]);
- reg[RF_PATH_C] = &(hal_data->PHYRegDef[RF_PATH_C]);
- reg[RF_PATH_D] = &(hal_data->PHYRegDef[RF_PATH_D]);
+ reg[RF_PATH_A] = &hal_data->PHYRegDef[RF_PATH_A];
+ reg[RF_PATH_B] = &hal_data->PHYRegDef[RF_PATH_B];
+ reg[RF_PATH_C] = &hal_data->PHYRegDef[RF_PATH_C];
+ reg[RF_PATH_D] = &hal_data->PHYRegDef[RF_PATH_D];
reg[RF_PATH_A]->rfintfs = rFPGA0_XAB_RFInterfaceSW;
reg[RF_PATH_B]->rfintfs = rFPGA0_XAB_RFInterfaceSW;
static bool config_parafile(struct adapter *adapt)
{
- struct eeprom_priv *pEEPROM = GET_EEPROM_EFUSE_PRIV(adapt);
+ struct eeprom_priv *eeprom = GET_EEPROM_EFUSE_PRIV(adapt);
struct hal_data_8188e *hal_data = GET_HAL_DATA(adapt);
set_baseband_phy_config(adapt);
/* If EEPROM or EFUSE autoload OK, We must config by PHY_REG_PG.txt */
- if (!pEEPROM->bautoload_fail_flag) {
+ if (!eeprom->bautoload_fail_flag) {
hal_data->pwrGroupCnt = 0;
config_bb_with_pgheader(adapt);
}
/* Enable BB and RF */
regval = usb_read16(adapt, REG_SYS_FUNC_EN);
- usb_write16(adapt, REG_SYS_FUNC_EN, (u16)(regval|BIT13|BIT0|BIT1));
+ usb_write16(adapt, REG_SYS_FUNC_EN,
+ (u16)(regval | BIT(13) | BIT(0) | BIT(1)));
- usb_write8(adapt, REG_RF_CTRL, RF_EN|RF_RSTB|RF_SDMRSTB);
+ usb_write8(adapt, REG_RF_CTRL, RF_EN | RF_RSTB | RF_SDMRSTB);
- usb_write8(adapt, REG_SYS_FUNC_EN, FEN_USBA | FEN_USBD | FEN_BB_GLB_RSTn | FEN_BBRSTB);
+ usb_write8(adapt, REG_SYS_FUNC_EN, FEN_USBA |
+ FEN_USBD | FEN_BB_GLB_RSTn | FEN_BBRSTB);
/* Config BB and AGC */
rtstatus = config_parafile(adapt);
/* write 0x24[16:11] = 0x24[22:17] = crystal_cap */
crystal_cap = hal_data->CrystalCap & 0x3F;
- phy_set_bb_reg(adapt, REG_AFE_XTAL_CTRL, 0x7ff800, (crystal_cap | (crystal_cap << 6)));
+ phy_set_bb_reg(adapt, REG_AFE_XTAL_CTRL, 0x7ff800,
+ (crystal_cap | (crystal_cap << 6)));
return rtstatus;
}
Code Review / kvmfornfv.git / blobdiff